CYPRESS CY7C1354BV25, CY7C1356BV25 User Manual
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查询CY7C1354BV25-166BGC供应商
256K x 36/512K x 18 Pipelined SRAM with
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 225-MHz bus operations with zero wait states
— Available speed grades are 225, 200 and 166 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 2.5V power supply
• Fast clock-to-output times
— 2.8 ns (for 225-MHz device)
— 3.2ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
• Clock Enable (CEN
• Synchronous self-timed writes
• Available in 100 TQFP, 119 BGA, and 165 fBGA packages
• IEEE 1149.1 JTAG Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
) pin to suspend operation
CY7C1354BV25
CY7C1356BV25
NoBL™ Architecture
Functional Description
The CY7C1354BV25 and CY7C1356BV25 are 2.5V, 256K x
36 and 512K x 18 Synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL) logic, respectively. They are
designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1354BV25 and
CY7C1356BV25 are equipped with the advanced (NoBL) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data in systems that
require frequent Write/Read transitions. The CY7C1354BV25
and CY7C1356BV25 are pin compatible and functionally
equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BW
–BWd for CY7C1354BV25 and BWa–BWb for
a
CY7C1356BV25) and a Write Enable (WE
) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
, CE2, CE3) and an
1
) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
) signal,
Logic Block Diagram-CY7C1354BV25 (256K x 36)
A0, A1, A
MODE
ADV/LD
C
BW
a
BW
b
BW
c
BW
d
WE
OE
CE1
CE2
CE3
ZZ
CLK
EN
REGISTER 0
WRITE ADDRESS
REGISTER 1
ADDRESS
CONTROL
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
ADV/LD
C
WRITE ADDRESS
REGISTER 2
A1
D1
A0
D0
BURST
LOGIC
A1'
Q1
A0'
Q0
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
S
U
T
E
P
N
U
T
S
E
R
E
G
A
I
M
S
T
P
E
S
R
S
E
E
INPUT
REGISTER 0
O
D
U
T
A
P
T
U
A
T
B
S
U
T
F
E
F
E
E
R
R
S
I
E
N
G
E
DQs
DQP
DQP
DQP
DQP
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05292 Rev. *E Revised August 10, 2004
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Logic Block Diagram-CY7C1356BV25 (512K x 18)
CY7C1354BV25
CY7C1356BV25
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
Sleep
Control
ADV/LD
C
WRITE ADDRESS
REGISTER 2
A1
D1D0Q1
A0
BURST
LOGIC
A1'
A0'
Q0
O
U
T
P
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
E
D
U
A
T
T
A
R
E
S
G
T
I
E
S
E
T
R
E
I
R
N
S
G
E
INPUT
REGISTER 0
CLK
A0, A1, A
MODE
ADV/LD
BW
BW
ZZ
C
a
b
WE
OE
CE1
CE2
CE3
EN
Selection Guide
CY7C1354BV25-225
CY7C1356BV25-225
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
2.8 3.2 3.5 ns
250 220 180 mA
35 35 35 mA
CY7C1354BV25-200
CY7C1356BV25-200
CY7C1354BV25-166
CY7C1356BV25-166 Unit
O
U
T
P
U
T
B
U
F
F
E
R
S
E
E
DQs
DQP
DQP
Document #: 38-05292 Rev. *E Page 2 of 27
Pin Configurations
a
100-pin TQFP Packages
CY7C1354BV25
CY7C1356BV25
DQPc
DQc
DQc
V
DDQ
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DDQ
DQc
DQc
NC
V
DD
NC
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DDQ
DQd
DQd
DQPd
1CE2
A
A
CE
BWd
BWc
3
SS
CE
BWa
VDDV
BWb
CLKWECENOEE(18)
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CY7C1354BV25
(256K × 36)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
A
ADV/LD
A
A
81
DDQ
SS
SS
DDQ
SS
DD
ZZ
DDQ
SS
DQa
SS
DDQ
DQPa
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQb
DQb
V
SS
V
DDQ
DQb
DQb
NC
V
DD
NC
V
SS
DQb
DQb
V
DDQ
V
SS
DQb
DQb
DQPb
NC
V
SS
V
DDQ
NC
NC
NC
DQPb
80
DQb
79
DQb
78
V
77
V
76
DQb
75
DQb
74
DQb
73
DQb
72
V
71
V
70
DQb
69
DQb
68
V
67
NC
66
V
65
64
DQa
63
DQa
62
V
61
V
60
DQa
59
DQa
58
DQa
57
56
V
55
V
54
DQa
53
DQa
52
51
50
1CE2
A
A
CE
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
bBWa
3
NC
NC
BW
CE
VDDV
SS
CLKWECENOEE(18)
CY7C1356BV25
(512K × 18)
ADV/LD
A
A
A
81
A
80
NC
79
NC
78
V
77
DDQ
V
SS
76
NC
75
DQP
74
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
AAA
MODE
1A0
A
A
E(288)
V
E(144)
SS
DD
V
E(72)
E(36)
A
AAA
A
A
A
A
AAA
MODE
1A0
A
E(144)
E(288)
AAA
A
E(72)
A
E(36)
DD
SS
V
V
A
A
Document #: 38-05292 Rev. *E Page 3 of 27
Pin Configurations (continued)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
119-ball BGA Pinout
CY7C1354BV25 (256K × 36) – 14 × 22 BGA
2345 671
V
V
V
V
V
DDQ
NC
NC
DQ
DQ
DDQ
DQ
DQ
DDQ
DQ
DQ
DDQ
DQ
DQ
NC
NC
DDQ
c
c
c
c
d
d
d
d
AA AAE(18) V
CE
A
DQP
DQ
DQ
DQ
DQ
V
DD
DQ
DQ
DQd
DQ
DQP
A
E(72)
TMS
2
c
c
c
c
d
d
d
A
ADV/LD
A
V
c
SS
V
SS
V
SS
BW
V
SS
NC
V
SS
BW
V
SS
V
SS
V
d
SS
MODE
A
V
DD
NC DQP
CE
1
OE
c
A
WE
V
DD
CLK
NC
d
CEN
A1
A0 V
V
DD
A
ACE3NC
AANC
V
SS
V
SS
V
SS
BW
V
SS
NC V
V
SS
BW
V
SS
V
SS
SS
NC
A
TCK
CY7C1354BV25
CY7C1356BV25
DDQ
DQ
b
DQ
b
DQ
b
DQ
DQ
DD
DQ
DQ
DQ
DQ
DQP
b
b
a
a
a
a
a
b
a
E(36)
NCTDI TDO V
DQ
V
DQ
V
DQ
V
DQ
DDQ
DQ
DDQ
DQ
DDQ
DQ
NCA
ZZ
DDQ
b
b
b
b
a
a
a
a
CY7C1356BV25 (512K x 18)–14 x 22 BGA
2345671
V
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
DDQ
NC
NC
NC
V
DDQ
NC
DQ
V
DDQ
NC
DQ
V
DDQ
DQ
NC
NC
E(72)
V
DDQ
b
b
b
b
AA AAE(18) V
CE
A
NCDQ
DQ
NC
DQ
NC
V
DD
DQ
NC
DQ
NC
DQP
A
A
TMS
2
b
b
b
b
b
A
A
V
SS
V
SS
V
SS
BW
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
A
ADV/LD
V
DD
NC NCDQP
CE
1
OE
b
AVSSNC
WE
V
DD
CLK
NC NC
CEN
A1
A0 V
V
DD
E(36)
A
AANC
V
SS
V
SS
V
SS
V
SS
NC V
SS
BW
a
V
SS
V
SS
SS
NC
A
TCK
CE
3
a
NC
DQ
a
DQ
a
DD
NCV
DQ
a
NC V
DQ
a
NC
A
A
NCTDI TDO V
V
V
DDQ
NC
DQ
DDQ
DQ
NC
DDQ
DQ
DDQ
NC
DQ
NC
ZZ
DDQ
a
a
a
a
Document #: 38-05292 Rev. *E Page 4 of 27
Pin Configurations (continued)
234 5671
A
A
NC
DQ
c
DQ
c
DQ
c
DQ
c
NC
DQ
d
DQ
d
DQ
d
DQ
d
NC
E(72)
E(36)
234 5671
A
A
NC
DQ
b
DQ
b
DQ
b
DQ
b
NC
NC
NC
NC
NC
NC
E(72)
E(36)
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
M
A
B
C
D
E
F
G
H
K
L
N
P
R
A
B
C
D
G
H
K
M
N
R
E(288)
NC
DQP
c
DQ
c
DQ
c
DQ
c
DQ
c
NC
J
DQ
DQ
DQ
DQ
DQP
d
d
d
d
d
NC
MODE
E(288)
NC
NC
NC
E
F
NC V
NC
NC
NC
J
L
P
DQ
DQ
DQ
DQ
DQP
NC
b
b
b
b
b
MODE
165-Ball fBGA Pinout
CY7C1354BV25 (256K × 36) – 13 × 15 fBGA
CE
CE2
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
BW
1
BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
CY7C1356BV25 (512K × 18) – 13 × 15 fBGA
CE
CE2
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
BW
1
NC BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
BW
c
d
BW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
b
NC
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
NC
TDI
TMS
CE
b
CLK
a
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
CEN
3
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCKA0
CE
CLK
a
V
SS
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
CEN
3
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCKA0
CY7C1354BV25
CY7C1356BV25
891011
ADV/LD
A
OE E(18)
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
891011
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
A
A
A
E(18)
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC
E(144)
NC DQP
DQ
DQ
DQ
DQ
NC
DQ
DQ
DQ
DQ
NC
A
DQ
b
DQ
b
DQ
b
DQ
b
ZZ
DQ
a
DQ
a
DQ
a
DQ
a
DQP
NC
A
A
E(144)
NC DQP
NC
NC
NC
NC
NC
DQ
DQ
DQ
DQ
NC
A
DQ
DQ
DQ
DQ
ZZ
a
a
a
a
NCV
NC
NC
NC
NC
NC
b
b
b
b
b
a
a
a
a
a
AA
A
a
a
a
a
a
AA
Document #: 38-05292 Rev. *E Page 5 of 27
CY7C1354BV25
CY7C1356BV25
Pin Definitions
Pin Name I/O Type Pin Description
A0, A1, A Input-
Synchronous
BW
a, BWb, BWc, BWd
WE
Input-
Synchronous
Input-
Synchronous
ADV/LD
Input-
Synchronous
CLK Input-
Clock
CE
CE
CE
OE
1
2
3
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CEN
Input-
Synchronous
DQ
a, DQb, DQc, DQd
DQP
DQP
a,
DQP
d
b,
DQP
c
I/O-
Synchronous
I/O-
Synchronous
MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
TDO JTAG serial
output
Synchronous
TDI JTAG serial input
Synchronous
TMS Test Mode Select
Synchronous
TCK JTAG-Clock Clock input to the JTAG circuitry.
V
V
DD
DDQ
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Address Inputs used to select one of the address locations. Sampled at the rising
edge of the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BW
DQ
and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd.
b
controls DQa and DQPa, BWb controls
a
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN
is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN
. CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
and CE3 to select/deselect the device.
2
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
and CE3 to select/deselect the device.
1
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
and CE2 to select/deselect the device.
1
Output Enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE
is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state and when the device has been
deselected.
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized
by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting
CEN
does not deselect the device, CEN can be used to extend the previous cycle when
required.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A
The direction of the pins is controlled by OE
asserted LOW, the pins can behave as outputs. When HIGH, DQ
a three-state condition. The outputs are automatically three-stated during the data
during the previous clock rise of the read cycle.
[17:0]
and the internal control logic. When OE is
–DQd are placed in
a
portion of a write sequence, during the first clock when emerging from a deselected
state, and when the device is deselected, regardless of the state of OE
.
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to
DQ
BW
. During write sequences, DQPa is controlled by BWa, DQPb is controlled by
[31:0]
, DQPc is controlled by BWc, and DQPd is controlled by BWd.
b
burst order. Pulled LOW selects the linear burst order. MODE should not change states
during operation. When left floating MODE will default HIGH, to an interleaved burst
order.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
This pin controls the Test Access Port state machine. Sampled on the rising edge
of TCK.
Document #: 38-05292 Rev. *E Page 6 of 27
CY7C1354BV25
CY7C1356BV25
Pin Definitions (continued)
Pin Name I/O Type Pin Description
V
SS
NC – No connects. This pin is not connected to the die.
E(18,36,72, 144, 288) – These pins are not connected. They will be used for expansion to the 18M, 36M,
ZZ Input-
Ground Ground for the device. Should be connected to ground of the system.
72M, 144M and 288M densities.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
Asynchronous
condition with data integrity preserved. During normal operation, this pin can be
connected to Vss or left floating.
Functional Overview
The CY7C1354BV25 and CY7C1356BV25 are
synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(t
) is 3.2 ns (200-MHz device).
CO
Accesses can be initiated by asserting all three Chip Enables
, CE2, CE3) active at the rising edge of the clock. If Clock
(CE
1
Enable (CEN
) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE
conduct byte write operations.
Write operations are qualified by the Write Enable (WE
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD
should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
are ALL asserted active, (3) the Write Enable input
3
is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 3.2 ns
(200-MHz device) provided OE
clock of the read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will three-state following
the next clock rise.
). If CEN is HIGH, the clock
). BW
can be used to
[d:a]
). All
) simplify depth expansion.
is asserted LOW, (2) CE1, CE2,
is active LOW. After the first
Burst Read Accesses
The CY7C1354BV25 and CY7C1356BV25 have an on-chip
burst counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD
must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD
will increment the internal
burst counter regardless of the state of chip enables inputs or
WE
. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented to A0–A16 is loaded
are ALL asserted active, and (3) the write signal WE
3
is asserted LOW, (2) CE1, CE2,
into the Address Register. The write signals are latched into
the Control Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE
allows the external logic to present the data on DQ
(DQ
for CY7C1356BV25). In addition, the address for the subse-
a,b,c,d
/DQP
for CY7C1354BV25 and DQ
a,b,c,d
input signal. This
and DQP
/DQP
a,b
a,b
quent access (Read/Write/Deselect) is latched into the
Address Register (provided the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ
(DQ
CY7C1356BV25) (or a subset for byte write operations, see
a,b,c,d
/DQP
for CY7C1354BV25 & DQ
a,b,c,d
a,b
/DQP
and DQP
for
a,b
Write Cycle Description table for details) inputs is latched into
the device and the write is complete.
The data written during the Write operation is controlled by BW
(BW
signals. The CY7C1354BV25/ CY7C1356BV25 provides byte
for CY7C1354BV25 and BW
a,b,c,d
for CY7C1356BV25)
a,b
write capability that is described in the Write Cycle Description
table. Asserting the Write Enable input (WE
Byte Write Select (BW
) input will selectively write to only the
) with the selected
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
Byte write capability has been included in order to greatly
simplify Read/Modify/Write sequences, which can be reduced
to simple byte write operations.
Document #: 38-05292 Rev. *E Page 7 of 27
CY7C1354BV25
CY7C1356BV25
Because the CY7C1354BV25 and CY7C1356BV25 are
common I/O devices, data should not be driven into the device
while the outputs are active. The Output Enable (OE) can be
deasserted HIGH before presenting data to the DQ
a,b,c,d
/DQP
(DQ
for CY7C1356BV25) inputs. Doing so will three-state the
output drivers. As a safety precaution, DQ
DQP
CY7C1356BV25) are automatically three-stated during the
for CY7C1354BV25 and DQ
a,b,c,d
for CY7C1354BV25 and DQ
a,b,c,d
and DQP (DQ
a,b
a,b
/DQP
and DQP
/DQP
a,b
a,b,c,d
for
a,b
data portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1354BV25/CY7C1356BV25 has an on-chip burst
counter that allows the user the ability to supply a single
address and conduct up to four WRITE operations without
reasserting the address inputs. ADV/LD
must be driven LOW
in order to load the initial address, as described in the Single
Write Access section above. When ADV/LD
is driven HIGH on
the subsequent clock rise, the chip enables (CE
) and WE inputs are ignored and the burst counter is incre-
CE
3
mented. The correct BW
BW
for CY7C1356BV25) inputs must be driven in each
a,b
cycle of the burst write in order to write the correct bytes of
(BW
for CY7C1354BV25 and
a,b,c,d
data.
/
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
for the duration of t
, CE2, and CE3, must remain inactive
1
after the ZZ input returns LOW.
ZZREC
, CE2, and
1
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Truth Table
Operation
Deselect Cycle None H L L X X X L L-H Three-State
Continue Deselect Cycle None X L H X X X L L-H Three-State
Sleep mode standby current ZZ > VDD − 0.2V 35 mA
Device operation to ZZ ZZ > VDD − 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to sleep current This parameter is sampled 2t
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
[1, 2, 3, 4, 5, 6, 7]
Address
Used CE ZZ ADV/LD WE BWx OE CEN CLK DQ
CYC
CYC
ns
ns
ns
Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q)
Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q)
NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Three-State
Dummy Read (Continue Burst) Next X L H X X H L L-H Three-State
Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D)
Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D)
NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Three-State
WRITE ABORT (Continue Burst) Next X L H X H X L L-H Three-State
IGNORE CLOCK EDGE (Stall) Current X L X X X X H L-H -
SLEEP MODE None X H X X X X X X Three-State
Notes:
1. X = “Don't Care”, 1 = Logic HIGH, 0 = Logic LOW, CE
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE
3. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE
= 1 inserts wait states.
5. CEN
6. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
7. OE
OE
is inactive or when the device is deselected, and DQs = data when OE is active
and BW
. See Write Cycle Description table for details.
[a:d]
stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid
signal.
.
= Three-state when
[a:d]
Document #: 38-05292 Rev. *E Page 8 of 27
CY7C1354BV25
CY7C1356BV25
Interleaved Burst Address Table
(MODE = Floating or V
First
Address
Second
Address
DD
)
Third
Address
A[1:0] A[1:0] A[1:0] A[1:0]
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Partial Write Cycle Description
[1, 2, 3, 8]
Function (CY7C1354BV25)
Fourth
Address
Linear Burst Address Table
(MODE = GND)
WE
First
Address
A[1:0] A[1:0] A[1:0] A[1:0]
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
BW
Second
Address
d
BW
Third
Address
c
BW
b
Fourth
Address
BW
a
Read H X X X X
Write –No bytes written L H H H H
Write Byte a– (DQ
Write Byte b – (DQ
and DQP
a
and DQP
b
a)
b)
LHHHL
LHHLH
Write Bytes b, a L H H L L
Write Byte c – (DQ
and DQP
c
c)
LHLHH
Write Bytes c, a L H L H L
Write Bytes c, b L H L L H
Write Bytes c, b, a L H L L L
Write Byte d – (DQ
and DQP
d
d)
LLHHH
Write Bytes d, a L L H H L
Write Bytes d, b LLHLH
Write Bytes d, b, a L L H L L
Write Bytes d, c L L L H H
Write Bytes d, c, a L L L H L
Write Bytes d, c, b L L L L H
Write All Bytes L L L L L
Function (CY7C1356BV25) WE
BW
b
BW
a
Read Hxx
Write – No Bytes Written L H H
Write Byte a − (DQ
Write Byte b – (DQ
and DQP
a
and DQP
b
a)
b)
LHL
LLH
Write Both Bytes L L L
Note:
8. Table only lists a partial listing of the byte write combinations. Any combination of BW
is valid. Appropriate write will be done based on which byte write is active.
[a:d]
Document #: 38-05292 Rev. *E Page 9 of 27
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