CYPRESS CY7C1354B, CY7C1356B User Manual
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查询CY7C1354B-166AC供应商
CY7C1354B
CY7C1356B
9-Mb (256K x 36/512K x 18) Pipelined SRAM
with NoBL™ Architecture
Features
• Pin-compatible and functionally equivalent to ZBT
• Supports 225-MHz bus operations with zero wait states
— Available speed grades are 225, 200, and 166 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte Write capability
• Separate V
• Single 3.3V power supply
• Fast clock-to-output times
— 2.8 ns (for 225-MHz device)
— 3.2ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
• Clock Enable (CEN
• Synchronous self-timed writes
• Available in 100 TQFP, 119 BGA, and 165 fBGA packages
• IEEE 1149.1 JTAG Boundary Scan
• Burst capability–linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
for 3.3V or 2.5V I/O
DDQ
) pin to suspend operation
Functional Description
The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and
512K x 18 Synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL) logic, respectively. They are designed to
support unlimited true back-to-back Read/Write operations
with no wait states. The CY7C1354B and CY7C1356B are
equipped with the advanced (NoBL) logic required to enable
consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The CY7C1354B and CY7C1356B are
pin compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BW
–BWd for CY7C1354B and BWa–BWb for CY7C1356B)
a
and a Write Enable (WE
) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
, CE2, CE3) and an
1
) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
) signal,
Logic Block Diagram-CY7C1354B (256K x 36)
A0, A1, A
MODE
C
CLK
EN
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
ADV/LD
WRITE ADDRESS
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
C
REGISTER 2
A1
D1D0Q1
A0
BURST
LOGIC
A1'
A0'
Q0
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
S
U
T
E
P
N
U
T
S
E
R
E
G
A
I
M
S
T
P
E
S
R
S
E
E
REGISTER 0
INPUT
O
D
U
T
A
P
T
U
A
T
B
S
T
E
E
R
I
N
G
E
DQs
U
DQP
F
DQP
F
DQP
E
DQP
R
S
E
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05114 Rev. *C Revised June 16, 2004
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Logic Block Diagram-CY7C1356B (512K x 18)
CY7C1354B
CY7C1356B
CLK
A0, A1, A
MODE
C
EN
ADV/LD
BW
a
BW
b
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
ADV/LD
WRITE ADDRESS
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
Sleep
Control
C
REGISTER 2
A1
D1D0Q1
A0
BURST
LOGIC
A1'
A0'
Q0
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
U
T
P
S
U
E
T
N
S
R
E
E
G
A
I
M
S
P
T
S
E
R
S
E
E
REGISTER 0
INPUT
O
U
T
P
D
U
A
T
T
A
B
DQs
U
S
F
T
E
E
R
I
N
G
E
DQP
F
DQP
E
R
S
E
Selection Guide
CY7C1354B-225
CY7C1356B-225
Maximum Access Time 2.8 3.2 3.5 ns
Maximum Operating Current 250 220 180 mA
Maximum CMOS Standby Current
Shaded areas contain advance information.
Please contact your local Cypress sales representative for availability of these parts.
35 35 35 mA
CY7C1354B-200
CY7C1356B-200
CY7C1354B-166
CY7C1356B-166
Unit
Document #: 38-05114 Rev. *C Page 2 of 29
Pin Configurations
a
CY7C1354B
CY7C1356B
100-pin TQFP Packages
DQPc
DQc
DQc
V
DDQ
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DDQ
DQc
DQc
NC
V
DD
NC
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DDQ
DQd
DQd
DQPd
1CE2
A
A
CE
BWd
BWc
BWa
BWb
CE3VDDV
SS
CLKWECENOEE(18)
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CY7C1354B
(256K × 36)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
A
ADV/LD
A
A
81
DDQ
SS
SS
DDQ
SS
DD
ZZ
DDQ
SS
DQa
SS
DDQ
DQPa
NC
NC
NC
V
DDQ
V
NC
NC
DQb
DQb
V
SS
V
DDQ
DQb
DQb
NC
V
DD
NC
V
SS
DQb
DQb
V
DDQ
V
SS
DQb
DQb
DQPb
NC
V
SS
V
DDQ
NC
NC
NC
SS
DQPb
80
DQb
79
DQb
78
V
77
V
76
DQb
75
DQb
74
DQb
73
DQb
72
V
71
V
70
DQb
69
DQb
68
V
67
NC
66
V
65
64
DQa
63
DQa
62
V
61
V
60
DQa
59
DQa
58
DQa
57
56
V
55
V
54
DQa
53
DQa
52
51
50
1CE2
A
A
CE
NC
NC
BWb
BWa
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CY7C1356B
(512K × 18)
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
CE3VDDV
SS
CLKWECENOEE(18)
ADV/LD
A
A
A
81
A
80
NC
79
NC
78
V
77
DDQ
V
SS
76
NC
75
DQP
74
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
AAA
MODE
1A0
A
A
E(288)
V
E(144)
SS
DD
V
E(72)
E(36)
A
AAA
A
A
A
A
AAA
MODE
1A0
A
E(144)
E(288)
AAA
A
E(72)
A
E(36)
DD
SS
V
V
A
A
Document #: 38-05114 Rev. *C Page 3 of 29
Pin Configurations (continued)
V
A
B
C
D
E
V
F
G
H
V
J
K
L
V
M
N
P
R
T
V
U
119-ball BGA Pinout
CY7C1354B (256K × 36) – 14 × 22 BGA
2345 671
DDQ
NC
NC
DQ
DQ
DDQ
DQ
DQ
DDQ
DQ
DQ
DDQ
DQ
DQ
NC
NC
DDQ
c
c
c
c
d
d
d
d
AA AAE(18) V
CE
A
DQP
DQ
DQ
DQ
DQ
V
DD
DQ
DQ
DQd
DQ
DQP
A
E(72)
TMS
2
c
c
c
c
c
d
d
d
d
A
A
V
SS
V
SS
V
SS
BW
V
SS
NC
V
SS
BW
V
SS
V
SS
V
SS
MODE
A
ADV/LD
V
DD
NC DQP
CE
1
OE
c
A
WE
V
DD
CLK
NC
d
CEN
A1
A0 V
V
DD
AE(36)
TCK
DDQ
ACE3NC
AANC
V
SS
V
SS
V
SS
BW
b
V
SS
NC V
V
SS
BW
a
V
SS
V
SS
SS
NC
A
DQ
DQ
DQ
DQ
DD
DQ
DQ
DQ
DQ
DQP
NCTDI TDO V
DQ
b
b
b
b
b
a
a
a
a
a
DQ
V
DQ
DQ
V
DQ
DQ
V
DQ
DQ
b
b
DDQ
b
b
DDQ
a
a
DDQ
a
a
NCA
ZZ
DDQ
CY7C1354B
CY7C1356B
CY7C1356B (512K x 18)–14 x 22 BGA
2345671
V
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
DDQ
NC
NC
NC
V
DDQ
NC
DQ
V
DDQ
NC
DQ
V
DDQ
DQ
NC
NC
E(72)
V
DDQ
b
b
b
b
AA AAE(18) V
CE
A
NCDQ
DQ
NC
DQ
NC
V
DD
DQ
NC
DQ
NC
DQP
A
A
TMS
2
b
b
b
b
b
A
A
V
SS
V
SS
V
SS
BW
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
A
ADV/LD
V
DD
NC NCDQP
CE
1
OE
b
AVSSNC
WE
V
DD
CLK
NC NC
CEN
A1
A0 V
V
DD
E(36)
A
AANC
V
SS
V
SS
V
SS
V
SS
NC V
SS
BW
a
V
SS
V
SS
SS
NC
A
TCK
CE
3
a
NC
DQ
a
DQ
a
DD
NCV
DQ
a
NC V
DQ
a
NC
A
A
NCTDI TDO V
V
V
DDQ
NC
DQ
DDQ
DQ
NC
DDQ
DQ
DDQ
NC
DQ
NC
ZZ
DDQ
a
a
a
a
Document #: 38-05114 Rev. *C Page 4 of 29
Pin Configurations (continued)
234 5671
A
A
NC
DQ
DQ
DQ
DQ
NC
DQ
DQ
DQ
DQ
NC
E(72)
E(36)
234 5671
A
A
NC
DQ
DQ
DQ
DQ
NC
NC
NC
NC
NC
NC
E(72)
E(36)
CE
CE2
V
V
c
V
c
V
c
V
c
NC
V
d
V
d
V
d
V
d
V
CE
CE2
V
V
b
V
b
V
b
V
b
NC
V
V
V
V
V
M
N
R
M
E(288)
A
B
C
D
E
F
G
H
J
K
L
P
NC
DQP
DQ
DQ
DQ
DQ
NC
DQ
DQ
DQ
DQ
DQP
NC
c
c
c
c
c
d
d
d
d
d
MODE
E(288)
A
B
C
D
E
F
G
H
J
K
L
N
P
R
NC
NC
NC
NC V
NC
NC
NC
DQ
b
DQ
b
DQ
b
DQ
b
DQP
b
NC
MODE
165-Ball fBGA Pinout
CY7C1354B (256K × 36) – 13 × 15 fBGA
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
BW
1
BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
BW
c
BW
d
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
CE
b
a
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
3
NC
A1
CY7C1356B (512K × 18) – 13 × 15 fBGA
CE
3
CLK
a
V
SS
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
BW
1
b
NC
NC BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
CEN
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCKA0
CEN
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCKA0
CY7C1354B
CY7C1356B
891011
A AADV/LD
OE E(18)
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
A
NC DQP
DQ
b
DQ
b
DQ
b
DQ
b
NC
DQ
a
DQ
a
DQ
a
DQ
a
NC
A
891011
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
A
A
A A
E(18)
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
NC DQP
NC
NC
NC
NC
NC
DQ
a
DQ
a
DQ
a
DQ
a
NC
A
NC
E(144)
DQ
b
DQ
b
DQ
b
DQ
b
ZZ
DQ
a
DQ
a
DQ
a
DQ
a
DQP
NC
AA
A
E(144)
DQ
a
DQ
a
DQ
a
DQ
a
ZZ
NCV
NC
NC
NC
NC
NC
AA
b
a
a
Document #: 38-05114 Rev. *C Page 5 of 29
CY7C1354B
CY7C1356B
Pin Definitions
Pin Name I/O Type Pin Description
A0
A1
Input-
Synchronous
A
BW
BW
BW
BW
WE
a
b
c
d
Input-
Synchronous
Input-
Synchronous
ADV/LD
Input-
Synchronous
CLK Input-
Clock
CE
CE
CE
OE
1
2
3
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CEN
Input-
Synchronous
DQ
DQ
DQ
DQ
DQP
DQP
DQP
DQP
a
b
c
d
a
b
c
d
I/O-
Synchronous
I/O-
Synchronous
MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
TDO JTAG serial output
Synchronous
TDI JTAG serial input
Synchronous
TMS Test Mode Select
Synchronous
TCK JTAG-Clock Clock input to the JTAG circuitry.
V
V
V
DD
DDQ
SS
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Ground Ground for the device. Should be connected to ground of the system.
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BW
controls DQ
and DQPc, BWd controls DQd and DQPd.
c
controls DQa and DQPa, BWb controls DQb and DQPb, BWc
a
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN
new address can be loaded into the device for an access. After being deselected, ADV/LD
is asserted LOW) the internal burst counter is advanced. When LOW, a
should
be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN
CLK is only recognized if CEN
is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE3 to select/deselect the device.
2
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE3 to select/deselect the device.
1
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE2 to select/deselect the device.
1
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the data portion of a Write sequence, during the first clock when emerging from a deselected state and when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN
deselect the device, CEN
can be used to extend the previous cycle when required.
does not
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by addresses during the previous clock rise of the Read cycle. The direction of the pins
is controlled by OE
as outputs. When HIGH, DQ
matically three-stated during the data portion of a write sequence, during the first clock when
and the internal control logic. When OE is asserted LOW, the pins can behave
–DQd are placed in a three-state condition. The outputs are auto-
a
emerging from a deselected state, and when the device is deselected, regardless of the state of
OE
.
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ
write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled
[a:d].
During
by BWc, and DQPd is controlled by BWd.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
.
Document #: 38-05114 Rev. *C Page 6 of 29
Pin Definitions (continued)
Pin Name I/O Type Pin Description
NC – No connects. This pin is not connected to the die.
E(18,36,
72, 144,
288)
ZZ Input-
– These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M
and 288M densities.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
Asynchronous
with data integrity preserved. During normal operation, this pin can be connected to V
floating.
CY7C1354B
CY7C1356B
or left
SS
Introduction
Functional Overview
The CY7C1354B and CY7C1356B are synchronous-pipelined
Burst NoBL SRAMs designed specifically to eliminate wait
states during Write/Read transitions. All synchronous inputs
pass through input registers controlled by the rising edge of
the clock. The clock signal is qualified with the Clock Enable
input signal (CEN
recognized and all internal states are maintained. All
synchronous operations are qualified with CEN
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(t
) is 2.8 ns (225-MHz device).
CO
Accesses can be initiated by asserting all three Chip Enables
(CE
, CE2, CE3) active at the rising edge of the clock. If Clock
1
Enable (CEN
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE
Writes are simplified with on-chip synchronous self-timed
Write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
are ALL asserted active, (3) the Write Enable input
3
is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the address register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.8 ns
(225-MHz device) provided OE
clock of the read access the output buffers are controlled by
OE
and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
). If CEN is HIGH, the clock signal is not
. All data
) is active LOW and ADV/LD is asserted LOW,
). BW
can be used to
[d:a]
). All
, CE2, CE3) and an
1
) simplify depth expansion.
is asserted LOW, (2) CE1, CE2,
is active LOW. After the first
of the chip enable signals, its output will three-state following
the next clock rise.
Burst Read Accesses
The CY7C1354B and CY7C1356B have an on-chip burst
counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD
must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD
will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented to A0∠A16 is loaded
are ALL asserted active, and (3) the Write signal WE
3
is asserted LOW, (2) CE1, CE2,
into the Address Register. The write signals are latched into
the Control Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE
allows the external logic to present the data on DQ
(DQ
CY7C1356B). In addition, the address for the subsequent
a,b,c,d
/DQP
for CY7C1354B and DQ
a,b,c,d
input signal. This
and DQP
a,b
/DQP
a,b
for
access (Read/Write/Deselect) is latched into the address
register (provided the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ
(DQ
CY7C1356B) (or a subset for byte write operations, see Write
a,b,c,d
/DQP
for CY7C1354B and DQ
a,b,c,d
a,b
and DQP
/DQP
a,b
for
Cycle Description table for details) inputs is latched into the
device and the Write is complete.
The data written during the Write operation is controlled by BW
(BW
signals. The CY7C1354B/56B provides Byte Write capability
for CY7C1354B and BW
a,b,c,d
for CY7C1356B)
a,b
that is described in the Write Cycle Description table. Asserting
the Write Enable input (WE
Select (BW
) input will selectively write to only the desired
) with the selected Byte Write
bytes. Bytes not selected during a Byte Write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the Write operations. Byte Write
capability has been included in order to greatly simplify
Document #: 38-05114 Rev. *C Page 7 of 29
CY7C1354B
CY7C1356B
Read/Modify/Write sequences, which can be reduced to
simple Byte Write operations.
Because the CY7C1354B and CY7C1356B are common I/O
devices, data should not be driven into the device while the
outputs are active. The Output Enable (OE
HIGH before presenting data to the DQ
(DQ
CY7C1356B) inputs. Doing so will three-state the output
a,b,c,d
/DQP
for CY7C1354B and DQ
a,b,c,d
drivers. As a safety precaution, DQ
DQP
CY7C1356B) are automatically three-stated during the data
for CY7C1354B and DQ
a,b,c,d
) can be deasserted
and DQP
/DQP
a,b
and DQP
a,b
(DQ
/DQP
a,b
a,b
a,b,c,d
for
for
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1354B/56B has an on-chip burst counter that allows
the user the ability to supply a single address and conduct up
to four WRITE operations without reasserting the address
inputs. ADV/LD
must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD
rise, the chip enables (CE
ignored and the burst counter is incremented. The correct BW
(BW
must be driven in each cycle of the burst write in order to write
for CY7C1354B and BW
a,b,c,d
is driven HIGH on the subsequent clock
, CE2, and CE3) and WE inputs are
1
for CY7C1356B) inputs
a,b
the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
the duration of t
, CE2, and CE3, must remain inactive for
1
after the ZZ input returns LOW.
ZZREC
Interleaved Burst Address Table
(MODE = Floating or V
/
First
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Second
Address
DD
)
Third
Address
Linear Burst Address Table
(MODE = GND)
First
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
Third
Address
Fourth
Address
Fourth
Address
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Sleep mode standby current ZZ > VDD − 0.2V 35 mA
Device operation to ZZ ZZ > VDD − 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to sleep current This parameter is sampled 2t
CYC
CYC
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
ns
ns
ns
Document #: 38-05114 Rev. *C Page 8 of 29
CY7C1354B
CY7C1356B
Truth Table
[1, 2, 3, 4, 5, 6, 7]
Address
Operation
Used CE ZZ ADV/LD WE BWx OE CEN CLK DQ
Deselect Cycle None H L L X X X L L-H Three-State
Continue
None X L H X X X L L-H Three-State
Deselect Cycle
Read Cycle
External L L L H X L L L-H Data Out (Q)
(Begin Burst)
Read Cycle
Next X L H X X L L L-H Data Out (Q)
(Continue Burst)
NOP/Dummy
External L L L H X H L L-H Three-State
Read
(Begin Burst)
Dummy Read
Next X L H X X H L L-H Three-State
(Continue Burst)
Write Cycle
External L L L L L X L L-H Data In (D)
(Begin Burst)
Write Cycle
Next X L H X L X L L-H Data In (D)
(Continue Burst)
NOP/WRITE
None L L L L H X L L-H Three-State
ABORT
(Begin Burst)
WRITE ABORT
Next X L H X H X L L-H Three-State
(Continue Burst)
IGNORE
Current X L X X X X H L-H CLOCK EDGE
(Stall)
Sleep MODE None X H X X X X X X Three-State
Notes:
1. X = “Don't Care”, 1 = Logic HIGH, 0 = Logic LOW, CE
Valid signifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE
3. When a write cycle is detected, all I/Os are three-stated, even during Byte Writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE
= H inserts wait states.
5. CEN
6. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
7. OE
OE
is inactive or when the device is deselected, and DQs = data when OE is active.
and BW
. See Write Cycle Description table for details.
[a:d]
stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx =
signal.
.
[a:d]
= Three-state when
Document #: 38-05114 Rev. *C Page 9 of 29
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