Cypress CY7C1353G User Manual

t

tecture

CY7C1353G

A
B

4-Mbit (256K x 18) Flow-through SRAM

h NoBL™ Archi

wi

Features

• Supports up to 133-MHz bus operations with zero wait
states

— Data is transferred on every clock

• Pin compatible and functionally equivalent to ZBT™ devices

• Internally self timed output buffer control to eliminate the
need to use OE

• Registered inputs for flow-through operation

• Byte Write capability

• 256K x 18 common IO architecture

• 2.5V/3.3V IO power supply (V

DDQ

)

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

• Clock Enable (CEN

) pin to suspend operation

• Synchronous self timed writes

• Asynchronous Output Enable

• Available in Pb-free 100-Pin TQFP package

• Burst Capability — linear or interleaved burst order

• Low standby power

Logic Block Diagram

ADDRESS
REGISTER

A1

D1

A0

D0

ADV/LD

C

WRITE ADDRESS

REGISTER

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

CLK

CEN

A0, A1, A

MODE

C

ADV/LD

BW

BW

WE

CE

A

B

Functional Description

[1]

The CY7C1353G is a 3.3V, 256K x 18 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1353G is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN

) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).

Write operations are controlled by the two Byte Write Select
(BW
conducted with on-chip synchronous self timed write circuitry.

Three synchronous Chip Enables (CE
asynchronous Output Enable (OE

) and a Write Enable (WE) input. All writes are

[A:B]

, CE2, CE3) and an

1

) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.

A1'

Q1

A0'

Q0

BURST
LOGIC

O
U

T
P

D

U

A

T

T
A

B
U

S

F

T

F

E

E

E

R

R

S

I
N
G

WRITE

DRIVERS

MEMORY

ARRAY

S
E

N

S

E
A

M

P

S

DQs
DQP
DQP

E

INPUT

OE

CE

1

CE

2

CE

3

ZZ

Note:

1.For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

READ LOGIC

SLEEP

CONTROL

REGISTER

E

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05515 Rev. *E Revised July 09, 2007

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CY7C1353G

Selection Guide

133 MHz 100 MHz Unit

Maximum Access Time 6.5 8.0 ns
Maximum Operating Current 225 205 mA
Maximum CMOS Standby Current 40 40 mA

Pin Configuration

100-Pin TQFP Pinout

BYTE B

V

DDQ

V

DQ
DQ

V

V

DDQ

DQ
DQ

V

V
DQ
DQ

V

DDQ

V
DQ
DQ

DQP

V

V

DDQ

NC
NC
NC

SS

NC
NC

SS

NC

DD

NC

SS

SS

NC

SS

NC
NC
NC

NC

NC

BBWA

BW

CE3VDDV

9291908988

CY7C1353G

SS

CLKWECEN

OE

878685

ADV/LD

NC/9M

NC/18M

848382

A

A

81

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58

57
56

55
54
53
52
51

A
NC
NC
V

DDQ

V

SS

NC
DQP
DQ
DQ
V

SS

V

DDQ

DQ
DQ
V

SS

NC
V

DD

ZZ

DQ
DQ
V

DDQ

V

SS

DQ
DQ
NC
NC
V

SS

V

DDQ

NC
NC
NC

A

A

A

A

A

BYTE A

A

A

A

A

A

100

1CE2

A

CE

99

98

9796959493

1

2
3

4
5
6
7
8

B

9

B

10

11
12

B

13

B

14
15
16
17
18

B

19

B

20
21

22

B

23

B

24

B

25

26
27

28
29

30

313233343536373839

A

A

A

A

A1

A0

MODE

NC/288M

40

414243444546474849

SS

NC/144M

DD

V

V

NC/36M

NC/72M

A

50

A

A

A

A

A

A

Document #: 38-05515 Rev. *E Page 2 of 13

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CY7C1353G

Pin Definitions

Name IO Description

, A1, A Input-

A

0

BW

WE

[A:B]

Synchronous

Input-

Synchronous

Input-

Synchronous

ADV/LD Input-

Synchronous

CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK

CE

CE

CE

1

2

3

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

OE Input-

Asynchronous

CEN

Input-

Synchronous

ZZ Input-

Asynchronous

DQ

DQP

s

[A:B]

IO-

Synchronous

IO-

Synchronous

MODE Input

Strap P in

V

DD

V

DDQ

V

SS

NC,NC/9M,

Power Supply Power supply inputs to the core of the device.

IO Power

Supply

Ground Ground for the device.

– No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/72M, NC/144M, NC/288M,
NC/18M,
NC/36M
NC/72M,
NC/144M,
NC/288M,

Address Inputs used to select one of the 256K address locations. Sampled at the rising edge
of the CLK. A

are fed to the two-bit burst counter.

[1:0]

Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
the rising edge of CLK.

Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.

Advance/Load Input. Used to advance the on-chip address counter or load a new address. When
HIGH (and CEN
address can be loaded into the device for an access. After being deselected, ADV/LD

is asserted LOW) the internal burst counter is advanced. When LOW, a new

must be

driven LOW to load a new address.

is only recognized if CEN

is active LOW.

Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE

, and CE3 to select/deselect the device.

2

Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE

and CE3 to select/deselect the device.

1

Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with

and CE2 to select/deselect the device.

CE

1

Output Enable, asynchronous input, Active LOW. Combined with the synchronous logic block
inside the device to control the direction of the IO pins. When LOW, the IO pins are allowed to
behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE
is masked during the data portion of a write sequence, during the first clock when emerging from
a deselected state, when the device has been deselected.

Clock Enable Input, Active LOW. When asserted LOW the Clock signal is recognized by the
SRAM. When deasserted HIGH the Clock signal is masked. While deasserting CEN
deselect the device, CEN

can be used to extend the previous cycle when required.

does not

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin
has an internal pull down.

Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by address during the clock rise of the read cycle. The direction of the pins is controlled by OE and
the internal control logic. When OE

and DQP

DQ

s

the data portion of a write sequence, during the first clock when emerging from a deselected state,

are placed in a tri-state condition. The outputs are automatically tri-stated during

[A:B]

and when the device is deselected, regardless of the state of OE

is asserted LOW, the pins can behave as outputs. When HIGH,

.

Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs. During write
sequences, DQP

is controlled by BWx correspondingly.

[A:B]

MODE Input. Selects the burst order of the device.

When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved
burst sequence.

Power supply for the IO circuitry.

are address expansion pins are not internally connected to the die.

Document #: 38-05515 Rev. *E Page 3 of 13

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CY7C1353G

Functional Overview

The CY7C1353G is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN

). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
rise (t

Accesses can be initiated by asserting all three Chip Enables
(CE
Enable (CEN
the address presented to the device is latched. The access
can either be a read or write operation, depending on the
status of the Write Enable (WE
conduct byte write operations.

Write operations are qualified by the Write Enable (WE
writes are simplified with on-chip synchronous self timed write
circuitry.

Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipe lined.
ADV/LD must be driven LOW after the device has been
deselected to load a new address for the next operation.

Single Read Accesses

A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE
clock of the read access, the output buffers are controlled by
OE
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output is tri-stated
immediately.

Burst Read Accesses

The CY7C1353G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW to load a new address into the SRAM, as
described in the Single Read Access section. The sequence
of the burst counter is determined by the MODE input signal.
A LOW input on MODE selects a linear burst mode, a HIGH
selects an interleaved burst sequence. Both burst counters
use A0 and A1 in the burst sequence, and wraps around when
incremented sufficiently. A HIGH input on ADV/LD
the internal burst counter regardless of the state of chip enable
inputs or WE

) is 6.5 ns (133-MHz device).

CDV

, CE2, CE3) active at the rising edge of the clock. If Clock

1

) is active LOW and ADV/LD is asserted LOW,

). BW

can be used to

[A:B]

). All

, CE2, CE3) and an

1

) simplify depth expansion.

is asserted LOW, (2) CE1, CE2,

are ALL asserted active, (3) the Write Enable input

3

is deasserted HIGH, and 4) ADV/LD is asserted

is active LOW. After the first

and the internal control logic. OE must be driven LOW in

increments

. WE is latched at the beginning of a burst cycle.

Therefore, the type of access (Read or Write) is maintained
throughout the burst sequence.

Single Write Accesses

Write access are initiated when these conditions are satisfied
at clock rise:

is asserted LOW

•CEN

•CE

, CE2, and CE3 are ALL asserted active

1

• The write signal WE is asserted LOW.

The address presented to the address bus is loaded into the
Address Register. The write signals are latched into the
Control Logic block. The data lines are automatically tri-stated
regardless of the state of the OE
external logic to present the data on DQs and DQP

On the next clock rise the data presented to DQs and DQP
(or a subset for byte write operations, see truth table for

input signal. This allows the

.

[A:B]

[A:B]

details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.

The data written during the Write operation is controlled by
BW

signals. The CY7C1353G provides byte write

[A:B]

capability that is described in the truth table. Asserting the
Write Enable input (WE) with the selected Byte Write Select
input selectively writes to only the desired bytes. Bytes not
selected during a byte write operation remains unaltered. A
synchronous self timed write mechanism has been provided
to simplify the write operations. Byte write capability has been
included to greatly simplify Read/Modify/Write sequences,
which can be reduced to simple byte write operations.

Because the CY7C1353G is a common IO device, data must
not be driven into the device while the outputs are active. The
Output Enable (OE
presenting data to the DQs and DQP
tri-states the output drivers. As a safety precaution, DQs and
DQP
a write cycle, regardless of the state of OE

.are automatically tri-stated during the data portion of

[A:B]

) can be deasserted HIGH before

inputs. Doing so

[A:B]

.

Burst Write Accesses

The CY7C1353G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD

must be driven LOW to load the initial address, as
described in the Single Write Access section. When ADV/LD
is driven HIGH on the subsequent clock rise, the Chip Enables
(CE

, CE2, and CE3) and WE inputs are ignored and the burst

1

counter is incremented. The correct BW
driven in each cycle of the burst write, to write the correct bytes

inputs must be

[A:B]

of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
for the duration of t

, CE2, and CE3, must remain inactive

1

after the ZZ input returns LOW.

ZZREC

Document #: 38-05515 Rev. *E Page 4 of 13

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