Cypress CY7C1352G User Manual

CY7C1352G

A
B

C

4-Mbit (256K x 18) Pipelined SRAM with

NoBL™ Architecture

Features

• Pin compatible and functionally equivalent to ZBT™
devices

• Internally self-timed output buffer control to eliminate
the need to use OE

• Byte Write capability

• 256K x 18 common I/O architecture

• 3.3V core power supply (V

• 2.5V/3.3V I/O power supply (V

• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)

• Clock Enable (CEN

) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous output enable (OE

• Available in lead-free 100-Pin TQFP package

• Burst Capability—linear or interleaved burst order

• ZZ” Sleep Mode Option and Stop Clock option

DD

)

DDQ

)

)

Functional Description

[1]

The CY7C1352G is a 3.3V , 256K x 18 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1352G is equipped with the advanced
No Bus Latency™ (NoBL™) logic required to enable consec­utive Read/Write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of the SRAM, especially in systems that require
frequent Write/Read transitions.

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN

) signal,
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 2.6 ns (250-MHz device).

Write operations are controlled by the two Byte Write Select
(BW
conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE
asynchronous Output Enable (OE

) and a Write Enable (WE) input. All writes are

[A:B]

, CE2, CE3) and an

1

) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.

Logic Block Diagram

A0, A1, A

MODE

ADV/LD

BW
BW

ZZ

C

A

B

WE

OE
CE1
CE2
CE3

CLK

EN

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

REGISTER 0

WRITE ADDRESS

REGISTER 1

ADDRESS

READ LOGIC

Control

ADV/LD

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

Sleep

C

REGISTER 2

A1

D1

A0

D0

BURST
LOGIC

A1'

Q1

A0'

Q0

WRITE

DRIVERS

MEMORY

ARRAY

INPUT

REGISTER 1

O
U
T
P

S

U

E

T

N
S

R

E

E
G

A

I

M

S

P

T

S

E
R

S

E

E

INPUT

REGISTER 0

O
U
T
P

D

U

A

T

T
A

B
U

S

F

T

F

E

E

E

R

R

S

I
N
G

E

E

DQs
DQP
DQP

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05514 Rev. *D Revised July 4, 2006

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CY7C1352G

Selection Guide

250 MHz 200 MHz 166 MHz 133 MHz Unit

Maximum Access Time 2.6 2.8 3.5 4.0 ns
Maximum Operating Current 325 265 240 225 mA
Maximum CMOS Standby Current 40 40 40 40 mA

Pin Configuration

100-Pin TQFP Pinout

BYTE B

NC
NC
NC

V

DDQ

V
NC

NC
DQ
DQ

V

V

DDQ

DQ
DQ

NC

V

NC

V
DQ
DQ

V

DDQ

V
DQ

DQ

DQP

NC

V

V

DDQ

NC

NC
NC

SS

SS

DD

SS

SS

SS

1CE2

A

A

CE

NC

99

98

100

1
2
3
4
5
6
7

B
B

B
B

B
B

B
B
B

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

9796959493

BWBBWACE3VDDV

NC

9291908988

CY7C1352G

SS

WE

CLK

CEN

OE

ADV/LD

87868584838281

NC/18M

NC/9M

A

A

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

A
NC
NC

V

DDQ

V

SS

NC

DQP
DQ
DQ

V

SS

V

DQ

DQ

V
NC

V

ZZ

DQ

DQ

V

V

DQ

DQ
NC
NC

V

SS

V

DDQ

NC
NC
NC

A
A

DDQ

SS

DD

DDQ
SS

A
A

A

A
A

BYTE A

A
A

313233

MODE

A

343536

A

A

373839404142434445

A1A

0

A

NC/288M

NC/144M

SS

V

V

DD

NC/72M

NC/36M

4647484950

A

A

A

A

A

A

A

Document #: 38-05514 Rev. *D Page 2 of 12

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CY7C1352G

Pin Definitions

Name I/O Description

A0, A1, A Input-

Synchronous

BW

WE

[A:B]

Input-

Synchronous

Input-

Synchronous

ADV/LD Input-

Synchronous

CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.

CE

CE

CE

1

2

3

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

OE Input-

Asynchronous

CEN Input-

Synchronous

ZZ Input-

Asynchronous

DQs I/O-

Synchronous

DQP

[A:B]

I/O-

Synchronous

MODE Input Strap Pin Mode Input. Selects the burst order of the device.

V
V
V

DD
DDQ
SS

Power Supply Power supply inputs to the core of the device.

I/O Power Supply Power supply for the I/O circuitry.

Ground Ground for the device.
NC – No Connects. Not internally connected to the die.
NC/36M,

– No Connects. Not internally connected to the die. NC/36M, NC/72M, NC/144M, NC/288M are
NC/72M,
NC/144M,
NC/288M

Address Inputs used to select one of the 256K address locations. Sampled at the rising
edge of the CLK. A

are fed to the two-bit burst counter.

[1:0]

Byte Write Inputs, active LOW . Qualified with WE to conduct writes to the SRAM. Sampled
on the rising edge of CLK.

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a write sequence.

Advance/Load Input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN

is asserted LOW) the internal burst counter is advanced. When LOW,
a new address can be loaded into the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.

CLK is only recognized if CEN

is active LOW.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE

and CE3 to select/deselect the device.

2

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE

and CE3 to select/deselect the device.

1

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE

and CE2 to select/deselect the device.

1

Output Enable, asynchronous input, active LOW. Combined with the synchronous logic
block inside the device to control the direction of the I/O pins. When LOW, the DQ pins are
allowed to behave as outputs. When deasserted HIGH, DQ pins are tri-stated, and act as input
data pins. OE

is masked during the data portion of a write sequence, during the first clock when

emerging from a deselected state, when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the

SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN
deselect the device, CEN

can be used to extend the previous cycle when required.

does not

ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical “sleep”
condition with data integrity preserved. During normal operation, this pin has to be low or left
floating. ZZ pin has an internal pull-down.

Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the address during the clock rise of the read cycle. The direction of the pins is
controlled by OE
as outputs. When HIGH, DQ
automatically tri-stated during the data portion of a write sequence, during the first clock when

and the internal control logic. When OE is asserted LOW, the pins can behave

and DQP

s

are placed in a tri-state condition. The outputs are

[A:B]

emerging from a deselected state, and when the device is deselected, regardless of the state
of OE

.

Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During
write sequences, DQP

When tied to Gnd selects linear burst sequence. When tied to V
interleaved burst sequence.

is controlled by BW

[A:B]

correspondingly.

[A:B]

or left floating selects

DD

address expansion pins are not internally connected to the die.

Document #: 38-05514 Rev. *D Page 3 of 12

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CY7C1352G

Functional Overview

The CY7C1352G is a synchronous-pipelined Burst SRAM
designed specifically to eliminate wait states during
Write/Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN

). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (t
device).

Accesses can be initiated by asserting all three Chip Enables

, CE2, CE3) active at the rising edge of the clock. If Clock

(CE

1

Enable (CEN

) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE
conduct byte write operations.

Write operations are qualified by the Write Enable (WE
writes are simplified with on-chip synchronous self-timed write
circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD

should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.

Single Read Accesses

A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE

are ALL asserted active, (3) the Write Enable input

3

is deasserted HIGH, and (4) ADV/LD is asserted

is asserted LOW, (2) CE1, CE2,

LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus, provided OE
is active LOW. After the first clock of the read access the output
buffers are controlled by OE

and the internal control logic. OE
must be driven LOW in order for the device to drive out the
requested data. During the second clock, a subsequent
operation (Read/Write/Deselect) can be initiated. Deselecting
the device is also pipelined. Therefore, when the SRAM is
deselected at clock rise by one of the chip enable signals, its
output will tri-state following the next clock rise.

Burst Read Accesses

The CY7C1352G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new addre ss into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap-around when incremented sufficiently. A HIGH input on
ADV/LD

will increment the internal burst counter regardless of

) is 2.6 ns (250-MHz

CO

). BW

can be used to

[A:B]

). All

) simplify depth expansion.

the state of chip enables inputs or WE

. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented to the address inputs

are ALL asserted active, and (3) the write signal WE

3

is asserted LOW, (2) CE1, CE2,

is loaded into the Address Register. The write signals are
latched into the Control Logic block.

On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE

input signal. This
allows the external logic to present the data on DQs and
DQP
(Read/Write/Deselect) is latched into the Address Register

. In addition, the address for the subsequent access

[A:B]

(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQs and

DQP[A:B] (or a subset for byte write operations, see Write
Cycle Description table for details) inputs is latched into the
device and the write is complete.

The data written during the Write operation is controlled by
BW

signals. The CY7C1352G provides byte write

[A:B]

capability that is described in the Write Cycle Description table.
Asserting the Write Enable input (WE) with the selected Byte
Write Select (BW
desired bytes. Bytes not selected during a byte write operation

) input will selectively write to only the

[A:B]

will remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
Byte write capability has been included in order to greatly
simplify Read/Modify/Write sequences, which can be reduced
to simple byte write operations.

Because the CY7C1352G is a common I/O device, data
should not be driven into the device while the outputs are
active. The Output Enable (OE
before presenting data to the DQs
so will tri-state the output drivers. As a safety precaution, DQs
and DQP
portion of a write cycle, regardless of the state of OE

are automatically tri-stated during the data

[A:B]

) can be deasserted HIGH

and DQP

inputs. Doing

[A:B]

.

Burst Write Accesses

The CY7C1352G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD

must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD
rise, the chip enables (CE
ignored and the burst counter is incremented. The correct
BW
in order to write the correct bytes of data.

inputs must be driven in each cycle of the burst write

[A:B]

is driven HIGH on the subsequent clock

, CE2, and CE3) and WE inputs are

1

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
the duration of t

1, CE2, and CE3, must remain inactive for

ZZREC after the ZZ input returns LOW.

Document #: 38-05514 Rev. *D Page 4 of 12

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