Cypress CY7C1350G User Manual

A
B
C
D

C

Logic Block Di

CY7C1350G

4-Mbit (128K x 36) Pipelined SRAM

with NoBL™ Architecture

Features

• Pin compatible and functionally equivalent to ZBT™
devices

• Internally self-timed output buffer control to eliminate
the need to use OE

• Byte Write capability

• 128K x 36 common I/O architecture

• 3.3V power supply (V

• 2.5V/3.3V I/O power supply (V

DD

)

)

DDQ

• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)

• Clock Enable (CEN

) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous output enable (OE

)

• Available in lead-free 100-Pin TQFP package, lead-free
and non-lead-free 119-Ball BGA package

• Burst Capability—linear or interleaved burst order

• “ZZ” Sleep mode option

agram

REGISTER 0

WRITE ADDRESS

REGISTER 1

ADDRESS

ADV/LD

C

WRITE ADDRESS

REGISTER 2

A1

D1

A0

D0

CLK

A0, A1, A

MODE

EN

C

BURST
LOGIC

Functional Description

[1]

The CY7C1350G is a 3.3V , 128K x 36 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1350G is equipped with the advanced
No Bus Latency™ (NoBL™) logic required to enable consec­utive Read/Write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of the SRAM, especially in systems that require
frequent Write/Read transitions.

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 2.6 ns (250-MHz device)

Write operations are controlled by the four Byte Write Select
(BW
conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE
asynchronous Output Enable (OE

) and a Write Enable (WE) input. All writes are

[A:D]

, CE2, CE3) and an

1

) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.

A1'

Q1

A0'

Q0

) signal,

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05524 Rev. *F Revised July 5, 2006

ADV/LD

BW

BW
BW

O

S

U
T

E

P

N

U
T

S

WRITE REGISTRY

A
B

C

BW

D

WE

OE
CE1
CE2
CE3

ZZ

AND DATA COHERENCY

CONTROL LOGIC

READ LOGIC

SLEEP

CONTROL

WRITE

DRIVERS

MEMORY

ARRAY

INPUT

REGISTER 1

E

R
E
G

A

I

M

S

T

P

E

S

R

S

E

E

INPUT

REGISTER 0

O

D

U
T

A

P

T

U

A

T
B

S

U

T

F

E

F

E

E

R

R

S

I

E

N
G

E

DQs
DQP
DQP

DQP
DQP

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CY7C1350G

Selection Guide

250 MHz 200 MHz 166 MHz 133 MHz 100 MHz Unit

Maximum Access Time 2.6 2.8 3.5 4.0 4.5 ns
Maximum Operating Current 325 265 240 225 205 mA
Maximum CMOS Standby Current 40 40 40 40 40 mA

Pin Configurations

100-Pin TQFP Pinout

BYTE C

BYTE D

DQP

DQ
DQ

V

DDQ

V
DQ
DQ
DQ
DQ

V

V

DDQ

DQ
DQ

V

NC

V
DQ
DQ

V

DDQ

V
DQ
DQ
DQ
DQ

V

V

DDQ

DQ
DQ

DQP

NC

SS

SS

DD

SS

SS

SS

1CE2

A

A

99989796959493

100

C
C
C

1
2
3

BWDBWCBWBBWACE3VDDV

CE

92

4
5

C
C
C
C

6
7
8
9
10
11

C
C

12
13
14

CY7C1350G

15
16
17

D
D

18
19
20
21

D
D
D
D

22
23
24
25
26
27

D
D
D

28
29
30

SS

CLKWECEN

OE

NC/18M

ADV/LD

NC/9M

A

A

9190898887868584838281

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DQPB
DQ

B

DQ

B

V

DDQ

V

SS

DQ

B

DQ

B

DQ

B

DQ

B

V

SS

V

DDQ

DQ

B

DQ

B

V

SS

NC
V

DD

ZZ
DQ

A

DQ

A

V

DDQ

V

SS

DQ

A

DQ

A

DQ

A

DQ

A

V

SS

V

DDQ

DQ

A

DQ

A

DQP

BYTE B

BYTE A

A

313233343536373839

A

A

A

A

A1A

0

4041424344454647484950

SS

DD

V

V

A

A

A

A

A

A

A

MODE

NC/72M

NC/288M

NC/144M

NC/36M

Document #: 38-05524 Rev. *F Page 2 of 15

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Pin Configurations (continued)

V

A
B
C

D
E
F
G

H

J

K
L

M

N
P

R
T
U

DDQ

NC/576M

NC/1G

DQ
DQ

V

DDQ

DQ
DQ

V

DDQ

DQ
DQ

V

DDQ

DQ
DQ

NC/144M

NC

V

DDQ

C
C

C
C

D
D

D
D

119-Ball BGA Pinout

234 5671

AA AANC/18M V

CE

2

A

DQP

C

DQ

C

DQ

C

DQ

C

DQ

C

V

DD

DQ

D

DQ

D

DQ

D

DQ

D

DQP

D

A

NC/72M

NC

A
A

V

SS

V

SS

V

SS

BW

V

SS

V

SS

V

SS

BW

V

SS

V

SS

V

SS

MODE

A

ADV/LD

V

DD

NC DQP

CE

1

OE

NC/9M

C

WE

V

DD

CLK

D

NC

CEN

A1
A0 V

V

DD

A NC/36M

A
AANC

V

SS

V

SS

V

SS

BW

V

SS

V

SS

V

SS

BW

V

SS

V

SS
SS

NC

A

NC

B

A

CE

DQ
DQ
DQ

DQ

V

DD

DQ
DQ

DQ
DQ

DQP

NCNC NC V

CY7C1350G

DDQ

3

B
B
B

B

A
A

A
A

NC

DQ

B

A

DQ

V

DQ
DQ

V

DQ
DQ

V

DQ
DQ

B
B

DDQ

B
B

DDQ

A
A

DDQ

A
A

NC/288MA

ZZ

DDQ

Pin Definitions

Name I/O Description

A0, A1, A Input-

Synchronous

BW

[A:D]

Input-

Synchronous

WE Input-

Synchronous

ADV/LD Input-

Synchronous

CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN

CE

CE

CE

OE

1

2

3

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Asynchronous

CEN

Input-

Synchronous

Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
of the CLK. A

are fed to the two-bit burst counter.

[1:0]

Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
the rising edge of CLK.

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.

Advance/Load Input. Used to advance the on-chip address counter or load a new address. When
HIGH (and CEN
address can be loaded into the device for an access. After being deselected, ADV/LD

is asserted LOW) the internal burst counter is advanced. When LOW, a new

should be

driven LOW in order to load a new address.

CLK is only recognized if CEN

is active LOW.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE

and CE3 to select/deselect the device.

2

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE

and CE3 to select/deselect the device.

1

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

and CE2 to select/deselect the device.

CE

1

Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block
inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE
is masked during the data portion of a write sequence, during the first clock when emerging from
a deselected state, when the device has been deselected.

Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the
SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN
deselect the device, CEN

can be used to extend the previous cycle when required.

does not

.

Document #: 38-05524 Rev. *F Page 3 of 15

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CY7C1350G

Pin Definitions (continued)

Name I/O Description

ZZ Input-

Asynchronous

DQs I/O-

Synchronous

DQP

[A:D]

I/O-

Synchronous

MODE Input

Strap pin
V
V
V

DD
DDQ
SS

Power Supply Power supply inputs to the core of the device.

I/O Power Supply Power supply for the I/O circuitry.

Ground Ground for the device.

NC No Connects. Not internally connected to the die. 9M, 18M, 36M, 72M, 144M and 288M are

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved.During normal operation, this pin has to be low or left floating. ZZ pin
has an internal pull-down.

Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the address during the clock rise of the read cycle. The direction of the pins is
controlled by OE
outputs. When HIGH, DQ
cally tri-stated during the data po rtion of a write sequence, during the first clock when emerging from

and the internal control logic. When OE is asserted LOW, the pins can behave as

and DQPX are placed in a tri-state condition. The outputs are automati-

s

a deselected state, and when the device is deselected, regardless of the state of OE.
Bidirectional Data Parity I/O Li nes. Functionally , these signals are identical to DQs. During write

sequences, DQP

is controlled by BW

[A:D]

correspondingly.

[A:D]

Mode Input. Selects the burst order of the device. When tied to GND selects linear burst
sequence. When tied to VDD or left floating selects interleaved burst sequence.

address expansion pins in this device and will be used as address pins in their respective densities.

Functional Overview

The CY7C1350G is a synchronous-pipelined Burst SRAM
designed specifically to eliminate wait states during
Write/Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN

). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (t
device).

Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN

) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE
conduct Byte Write operations.

Write operations are qualified by the Write Enable (WE
writes are simplified with on-chip synchronous self-timed write
circuitry.

Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD

should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.

Single Read Accesses

A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE

are ALL asserted active, (3) the Write Enable input

3

is deasserted HIGH, and (4) ADV/LD is asserted

is asserted LOW, (2) CE1, CE2,

LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core

) is 2.6 ns (250-MHz

CO

). BW

can be used to

[A:D]

). All

, CE2, CE3) and an

1

) simplify depth expansion.

and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus, provided OE
is active LOW. After the first clock of the read access the output
buffers are controlled by OE

and the internal control logic. OE
must be driven LOW in order for the device to drive out the
requested data. During the second clock, a subsequent
operation (Read/Write/Deselect) can be initiated. Deselecting
the device is also pipelined. Therefore, when the SRAM is
deselected at clock rise by one of the chip enable signals, its
output will tri-state following the next clock rise.

Burst Read Accesses

The CY7C1350G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD
the state of chip enables inputs or WE

will increment the internal burst counter regardless of

. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented to the address inputs

are ALL asserted active, and (3) the Write signal WE

3

is asserted LOW, (2) CE1, CE2,

is loaded into the Address Register. The write signals are
latched into the Control Logic block.

Document #: 38-05524 Rev. *F Page 4 of 15

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CY7C1350G

On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE
allows the external logic to present the data on DQs
DQP
(Read/Write/Deselect) is latched into the Address Register

. In addition, the address for the subsequent access

[A:D]

input signal. This

and

(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQs

(or a subset for Byte Write operations, see Write Cycle

and DQP

[A:D]

Description table for details) inputs is latched into the device
and the write is complete.

The data written during the Write operation is controlled by
BW
capability that is described in the Write Cycle Description table.

signals. The CY7C1350G provides byte write

[A:D]

Asserting the Write Enable input (WE) with the selected Byte
Write Select (BW
desired bytes. Bytes not selected during a Byte Write

) input will selectively write to only the

[A:D]

operation will remain unaltered. A synchronous self-timed
write mechanism has been provided to simplify the write
operations. Byte write capability has been included in order to
greatly simplify Read/Modify/Write sequences, which can be
reduced to simple byte write operations.

Because the CY7C1350G is a common I/O device, data
should not be driven into the device while the outputs are
active. The Output Enable (OE
before presenting data to the DQs
so will tri-state the output drivers. As a safety precaution, DQs
and DQP
portion of a write cycle, regardless of the state of OE

are automatically tri-stated during the data

[A:D]

) can be deasserted HIGH

and DQP

inputs. Doing

[A:D]

.

Burst Write Accesses

The CY7C1350G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD

must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE

Truth Table

[2, 3, 4, 5, 6, 7, 8]

, CE2, and CE3) and WE inputs are

1

ignored and the burst counter is incremented. The correct
BW
in order to write the correct bytes of data.

inputs must be driven in each cycle of the burst write

[A:D]

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
for the duration of t

, CE2, and CE3, must remain inactive

1

after the ZZ input returns LOW.

ZZREC

Interleaved Burst Address Table
(MODE = Floating or V

First Address

A1, A0

00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

Second

Address

A1, A0

DD

)

Third

Address

A1, A0

Fourth

Address

A1, A0

Linear Burst Address Table (MODE = GND)

First Address

A1, A0

Address

A1, A0

00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10

Second

Third

Address

A1, A0

Fourth

Address

A1, A0

Operation Address Used CE ZZ ADV/LD WE BWxOE CEN CLK DQ

Deselect Cycle None H L L X X X L L-H Tri-State
Continue Deselect Cycle None X L H X X X L L-H Tri-State
Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q)
Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q)
NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Tri-State
Dummy Read (Continue Burst) Next X L H X X H L L-H Tri-State
Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D)
Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D)

Notes:

2. X =”Don't Care.” H = Logic HIGH, L = Logic LOW. CE
signifies that the desired byte write selects are asserted, see Write Cycle Descript i on table for details.

3. Write is defined by BW

4. When a write cycle is detected, all DQs are tri-stated, even during byte writes.

5. The DQ and DQP pins are controlled by the current cycle and the OE

= H, inserts wait states.

6. CEN

7. Device will power-up deselected and the DQs in a tri-state condition, regardless of OE

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP

8. OE
OE

is inactive or when the device is deselected, and DQs and DQP

, and WE. See Write Cycle Descriptions table.

X

stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid

signal. OE is asynchronous and is not sampled with the clock.

.

= data when OE is active.

[A:D]

= tri-state when

[A:D]

Document #: 38-05524 Rev. *F Page 5 of 15

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