CYPRESS CY7C135, CY7C1342 User Manual

CY7C135

CY7C1342

4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port

Features

• True Dual-Ported memory cells which allow simulta-

neous reads of the same memory location

• 4K x 8 organization

• 0.65-micron CMOS for optimum speed/power

• High-speed access: 15 ns

• Low operating power: ICC = 160 mA (max.)

• Fully asynchronous operation

• Automatic power-down

• Semaphores included on the 7C1342 to permit software

handshaking between ports

• Available in 52-pin PLCC

Logic Block Diagram

R/W

SRAM with Sema

hores

Functional Description

The CY7C135 and CY7C1342 are high-speed CMOS 4K x 8 dual-port static RAMs. The CY7C1342 includes semaphores that provide a means to allocate portions of the dual-port RAM or any shared resource. Two ports are provided permitting in dependent, asynchronous access for reads and writes to any location in memory. Application areas include interproces sor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.

Each port has independent control pins: chip enable (CE), read or write enable (R/ CY7C135 is suited for those systems that do not require on-chip arbitration or are intolerant of wait states. Therefore, the user must be aware that simultaneous access to a location is possible. Semaphores are offered on the CY7C1342 to as sist in arbitrating between ports. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore in di cates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip enable (

CE) pin or SEM pin (CY7C1342 only).

The CY7C135 and CY7C1342 are available in 52-pin PLCC.

W), and output enable (OE). The

R/W

I/O

11L

(7C1342 only)

SEM

I/O

CONTROL

ADDRESS

DECODER

R/W

MEMORY

ARRAY

SEMAPHORE ARBITRATION (7C1342 only)

I/O

CONTROL

ADDRESS DECODER

R/W

(7C1342 only)

SEM

I/O

11R

1342–1

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

Document #: 38-06038 Rev. *B Revised June 22, 2004

CY7C135

CY7C1342

Selection Guide

7C135–15

7C1342–15

Maximum Access Time (ns) 15 20 25 35 55 Maximum Operating

Commercial 220 190 180 160 160

Current (mA) Maximum St andby

Current for I

SB1

(mA)

Commercial 60 50 40 30 30

Pin Configurations

PLCC

Top View

10L

11L

N/C

A A A A A A A A

A I/O I/O I/O I/O

A A A A A A A A

A I/O I/O I/O I/O

7 6 5 4 3 2 52 51 50 49 48 47

2122 23 24 25 26 27 28 29 30 31 32 33

4L5L6L

I/O

765432 525150494847

2122 23 24 25 26 27 28 29 30 31 32 33

4L5L6L

I/O

10L

I/O

7C135

PLCC

Top View

11L

SEM

7C1342

GND

Pin Definitions

Left Port Right Port Description

0L–11L

R/W

SEM

(CY7C1342 only)

0R–11R

R/W

SEM

(CY7C1342 only)

Address Lines Chip Enable Output Enable Read/Write Enable Semaphore Enable. When asserted LOW, allows access to eight semaphores. The

three least significant bits of the address lines will determine which semaphore to write or read. The I/O by writing a 0 into the respective location.

pin is used when writing to a semaphore. Semaphores are requested

7C135–20

7C1342–20

R/W

GND

R/W

I/O

LCER

R/W

0R1R2R3R4R5R6R

I/O

LCER

R/W

0R1R2R3R4R5R6R

I/O

7C135–25

7C1342–25

10R

11R

N/C

I/O

11R

SEM

I/O

1342–3

10R

I/O

1342–4

7C135–35

7C1342–35

7C135–55

7C1342–55

Document #: 38-06038 Rev. *B Page 2 of 12

CY7C135

CY7C1342

Maximum Ratings

[1]

Static Discharge Voltage...........................................> 2001V

(per MIL-STD-883, Method 3015)

Storage Temperature ..................................–65°C to +150°C

Ambient Temperature with

Power Applied..............................................–55°C to +125°C

Supply Voltage to Ground Potential

(Pin 48 to Pin 24)............................................–0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State................................................–0.5V to +7.0V

DC Input Voltage

[2]

.........................................–3.0V to +7.0V

Electrical Characteristics Over the Operating Range

Latch-Up Current....................................................> 200 mA

Operating Range

Range

Commercial 0°C to +70°C 5V ± 10%

Industrial –40°C to +85°C 5V ± 10%

[4]

7C135–15 7C1342–1

Ambient

Temperature V

7C135–20 7C1342–207C135–25

7C1342–25

Max.Min.Max

Parameter Description Test Conditions Min.

SB1

SB2

SB3

Ind. 30

Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 2.4 V Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 0.4 V Input HIGH Volt age 2.2 2.2 2.2 V Input LOW Volt age 0.8 0.8 0.8 V Input Load Current GND ≤ VI ≤ V

Output Leakage Current Outputs Disabled,

GND ≤ VO ≤ V

Operating Current VCC = Max.,

= 0 mA

OUT

Standby Current (Both Ports TTL Levels)

Standby Current (One Port TTL Level)

Standby Current (Both Ports CMOS Levels)

CEL and CER ≥ VIH, f = f

MAX

[5]

Both Ports CE and CER ≥ V

– 0.2V ,

VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, f = 0

[5]

Com’l 220 190 180 mA

Ind. 190

Com’l 60 50 40 mA

Ind. 50

Com’l 130 120 110 mA

Ind. 120

Com’l 15 15 15 mA

–10 +10 –10 +10 –10 +10 µA –10 +10 –10 +10 –10 +10 µA

. Min.

Max.Uni

SB4

Notes:

1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.

2. Pulse width < 20 ns.

3. TA is the “instant on” case temper ature.

4. See the last page of this specification for Group A subgroup testing information.

5. f

MAX

Standby Current (One Port CMOS Level)

= 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address o r control lines cha nge. This applies only to input s at CMOS level st andby I

One Port CEL or CER ≥ VCC – 0.2V , VIN ≥VCC – 0.2V or VIN ≤ 0.2V, Active Port Outputs, f =

[5]

MAX

Com’l 125 115 100 mA

Ind. 115

SB3

Document #: 38-06038 Rev. *B Page 3 of 12

CY7C135

CY7C1342

Electrical Characteristics Over the Operating Range

[4]

(continued)

7C135–35

7C1342–35

7C135–55

7C1342–55

Parameter Description Test Conditions Min. Max. Min. Max. Unit

V V V V I

SB1

SB2

SB3

SB4

OH OL IH IL

Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V

2.2 2.2 V Input LOW Volt age 0.8 0.8 V Input Load Current GND ≤ VI ≤ V

Output Leakage Current Outputs Disabled, GND ≤ VO ≤ V Operating Current VCC = Max., I

VCC = Max., I

Standby Current

CEL and CER ≥ VIH, f = f

(Both Ports TTL Levels) Standby Current

CEL and CER ≥ VIH, f = f

(One Port TTL Level) Standby Current

(Both Ports CMOS Levels)

Both Ports CE and CER ≥ VCC – 0.2V , VIN ≥ VCC – 0.2V or VIN ≤ 0.2V , f = 0

Standby Current (One Port CMOS Level)

One Port CEL or CER ≥ VCC – 0.2V , VIN ≥ VCC – 0.2V or VIN ≤ 0.2V , Active Port Outputs, f = f

= 0 mA Com’l 160 160 mA

OUT

= 0 mA Ind. 180 180

OUT

[5]

MAX

[5]

Com’l 30 30 mA

Ind. 40 40

Com’l 100 100 mA

Ind. 110 110

Com’l 15 15 mA

Ind. 30 30

Com’l 90 90 mA

Ind. 100 100

–10 +10 –10 +10 µA –10 +10 –10 +10 µA

Capacitance

[6]

Parameter Description Test Conditions Max. Unit

C C

IN OUT

Input Capacitanc e TA = 25°C, f = 1 MHz, Output Capacitance 10 pF

VCC = 5.0V

AC Test Loads and Waveforms

R1= 893Ω

OUTPUT

30pF

(a) Normal Load (Load 1)

Note:

6. Tested initially and after any design or process changes that may affect these parameters.

R1= 347Ω

1342–5 1342–6 1342–7

3.0V

GND

OUTPUT

(b) Thévenin Equivalent (Load 1)

10%

≤ 3ns

= 250Ω

30pF

ALL INPUT PULSES

90%

=1.4V

10%

≤3

10 pF

OUTPUT

C= 5pF

1342–8

= 250Ω

Document #: 38-06038 Rev. *B Page 4 of 12

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CYPRESS CY7C135, CY7C1342 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual