Cypress CY7C1347G User Manual
CY7C1347G
4-Mbit (128K x 36) Pipelined Sync SRAM
Features
Note
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
■ Fully registered inputs and outputs for pipelined operation
■ 128K x 36 common IO architecture
■ 3.3V core power supply (V
■ 2.5V/3.3V IO power supply (V
■ Fast clock to output times: 2.6 ns (for 250 MHz device)
■ User-selectable burst counter supporting Intel
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed writes
■ Asynchronous output enable
■ Offered in Pb-free 100-Pin TQFP, Pb-free and non Pb-free
119-Ball BGA package, and 165-Ball FBGA package
■ “ZZ” sleep mode option and stop clock option
■ Available in industrial and commercial temperature ranges
DD
)
DDQ
)
®
Pentium
®
Functional Description
[1]
The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined
SRAM designed to support zero-wait-state secondary cache
with minimal glue logic. CY7C1347G IO pins can operate at
either the 2.5V or the 3.3V level. The IO pins are 3.3V tolerant
when V
registers controlled by the rising edge of the clock. All data
= 2.5V. All synchronous inputs pass through input
DDQ
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise is
2.6 ns (250 MHz device). CY7C1347G supports either the
interleaved burst sequence used by the Intel Pentium processor
or a linear burst sequence used by processors such as the
PowerPC
®
. The burst sequence is selected through the MODE
pin. Accesses can be initiated by asserting either the Address
Strobe from Processor (ADSP) or the Address Strobe from
Controller (ADSC
the burst sequence is controlled by the ADV
) at clock rise. Address advancement through
input. A 2-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte write operations are qualified with the four Byte Write Select
(BW
write inputs and writes data to all four bytes. All writes are
) inputs. A Global Write Enable (GW) overrides all byte
[A:D]
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE
asynchronous Output Enable (OE
, CE2, CE3) and an
1
) provide for easy bank
selection and output tri-state control. To provide proper data
during depth expansion, OE is masked during the first clock of a
read cycle when emerging from a deselect ed state.
Selection Guide
Specification 250 MHz 200 MHz 166 MHz 133 MHz Unit
Maximum Access Time 2.6 2.8 3.5
Maximum Operating Current 325 265 240
Maximum CMOS Standby Cur rent 40 40 40 40 mA
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05516 Rev. *F Revised January 15, 2009
4.0 ns
225 mA
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CY7C1347G
Block Diagram
ADDRESS
REGISTER
ADV
CLK
BURST
COUNTER
AND
LOGIC
CLR
Q1
Q0
ADSP
ADSC
MODE
BWE
GW
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
OUTPUT
REGISTERS
SENSE
AMPS
OUTPUT
BUFFERS
E
PIPELINED
ENABLE
INPUT
REGISTERS
A 0, A1, A
BW
B
BW
C
BW
D
BW
A
MEMORY
ARRAY
DQs
DQP
A
DQP
B
DQP
C
DQP
D
SLEEP
CONTROL
ZZ
A
[1:0]
2
DQA,DQP
A
BYTE
WRITE REGISTER
DQ
B,
DQP
B
BYTE
WRITE REGISTER
DQ
C,
DQP
C
BYTE
WRITE REGISTER
DQ
D,
DQP
D
BYTE
WRITE REGISTER
DQ
A,
DQP
A
BYTE
WRITE DRIVER
DQ
B,
DQP
B
BYTE
WRITE DRIVER
DQ
C,
DQP
C
BYTE
WRITE DRIVER
DQ
D
,DQP
D
BYTE
WRITE DRIVER
Document #: 38-05516 Rev. *F Page 2 of 22
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CY7C1347G
Pinouts
AAAAA1A
0
NC/72M
NC/36M
V
SS
V
DD
NC/18M
NC/9M
AAAAAAA
DQP
B
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SSQ
DQ
A
DQ
A
DQ
A
DQ
A
V
SSQ
V
DDQ
DQ
A
DQ
A
DQP
A
DQP
C
DQ
C
DQ
C
V
DDQ
V
SSQ
DQ
C
DQ
C
DQ
C
DQ
C
V
SSQ
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SSQ
DQ
D
DQ
D
DQ
D
DQ
D
V
SSQ
V
DDQ
DQ
D
DQ
D
DQP
D
AACE1CE2BWDBWCBWBBWACE3VDDVSSCLKGWBWEOEADSC
ADSP
ADVAA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100999897969594939291908988878685848382
81
MODE
BYTE A
BYTE B
BYTE D
BYTE C
CY7C1347G
Figure 1. 100-Pin TQFP
Document #: 38-05516 Rev. *F Page 3 of 22
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CY7C1347G
Pinouts (continued)
2
345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/288M
NC/144M
DQP
C
DQ
C
DQ
D
DQ
C
DQ
D
AA AAADSP V
DDQ
CE
2
A
DQ
C
V
DDQ
DQ
C
V
DDQ
V
DDQ
V
DDQ
DQ
D
DQ
D
NC
NC
V
DDQ
V
DD
CLK
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC/576M
NC/1G
NC
NC
NCNCNCNC
NC/36MNC/72M
NC
V
DDQ
V
DDQ
V
DDQ
AAA
A
CE
3
AA
A
AA
A
A0
A1
DQ
A
DQ
C
DQ
A
DQ
A
DQ
A
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
A
DQ
A
DQ
A
DQ
A
DQ
B
V
DD
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
ADSC
NC
CE
1
OE
ADV
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
DQP
A
MODE
DQP
D
DQP
B
BW
B
BW
C
NC V
DD
NC
BW
A
NC
BWE
BW
D
ZZ
A
Figure 2. 119-Ball BGA
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC/288M
NC/144M
DQP
C
DQ
C
DQP
D
NC
DQ
D
CE1BW
B
CE
3
BW
C
BWE
A
CE2
DQ
C
DQ
D
DQ
D
MODE
NC
DQ
C
DQ
C
DQ
D
DQ
D
DQ
D
NC/36M
NC/72M
V
DDQ
BW
D
BW
A
CLK
GW
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
SS
V
SS
NC/18M
V
SS
V
SS
V
SS
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
V
DD
V
SS
V
DD
V
SS
V
SS
V
DDQ
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
SS
NC
NC
V
SS
NC
A
A
DQ
C
V
SS
DQ
C
V
SS
DQ
C
DQ
C
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A1
DQ
D
DQ
D
NC
NC
V
DDQ
V
SS
NC
891011
NC/9M
ADV
A
ADSC
NC
OE ADSP
A
NC/576M
V
SS
V
DDQ
NC/1G DQP
B
V
DDQ
V
DD
DQ
B
DQ
B
DQ
B
NC
DQ
B
NC
DQ
A
DQ
A
V
DD
V
DDQ
V
DD
V
DDQ
DQ
B
V
DD
NC
V
DD
DQ
A
V
DD
V
DDQ
DQ
A
V
DDQ
V
DD
V
DD
V
DDQ
V
DD
V
DDQ
DQ
A
V
DDQ
AA
V
SS
A
A
A
DQ
B
DQ
B
DQ
B
ZZ
DQ
A
DQ
A
DQP
A
DQ
A
A
V
DDQ
A
A0
A
V
SS
Figure 3. 165-Ball FBGA
Document #: 38-05516 Rev. *F Page 4 of 22
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CY7C1347G
Table 1. Pin Definitions
Name IO Description
A0,A1,A Input-
Synchronous
BWA,BW
BWC,BW
B,
D
InputSynchronous
GW Input-
Synchronous
BWE Input-
Synchronous
Address Inputs Used to Select One of the 128K Address Locations. Sampled at the rising edge
of the CLK if ADSP
the 2-bit counter.
or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A
[1:0]
feeds
Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW
and BWE).
[A:D]
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byt e wri te .
CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
CE
CE
CE
1
2
3
InputSynchronous
InputSynchronous
InputSynchronous
OE Input-
Asynchronous
ADV Input-
Synchronous
ADSP Input-
Synchronous
ADSC Input-
Synchronous
ZZ Input-
Asynchronous
counter when ADV
Chip Enable 1 Input, Active LOW. Sampled on the risin g edge of CLK. Used in conjunction with CE2
and CE
a new external address is loaded.
to select or deselect the device. ADSP is ignore d if CE1 is HIGH. CE1 is sampled only when
3
Chip Enable 2 Input, Active HIGH. Sampled on the risi ng edge of CLK. Used in conj unction with CE1
and CE
to select or deselect the device. CE2 is sampled only when a new external address is loaded.
3
Chip Enable 3 Input, Active LOW. Sampled on th e rising edge of CL K. Used in conjunctio n with CE
and CE2 to select or deselect the device. CE3 is sampled only when a new external address is l oaded.
Output Enable, Asynchronous Input, Active LOW. Controls the direction of the IO pins. When LOW ,
the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data
pins. OE
is masked during the first clock of a read cycle when emerging from a deselected state.
Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
Address Strobe from Processor, Sampled on the Rising Edge of CLK. When asserted LOW,
addresses presented to the device are captured in the address registers. A
burst counter. When ADSP
when CE
is deasserted HIGH.
1
Address Strobe from Controller, Sampled on the Rising Edge of CLK. When asserted LOW,
addresses presented to the device are captured in the address registers. A
burst counter. When ADSP
ZZ “Sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition with
data integrity preserved. During normal operat ion, this pin must be LOW o r lef t floating. ZZ p in has an
is asserted LOW, during a burst operation.
and ADSC are both asserted, only ADSP is recognized. ASDP is ignored
and ADSC are both asserted, onl y AD SP is recognized.
are also loaded into the
[1:0]
are also loaded into the
[1:0]
internal pull down.
DQ
DQ
DQP
DQP
A, DQB
C, DQD
DQP
A,
DQP
C,
IOSynchronous
B,
D
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is t riggered by the
rising edge of CLK. As outputs , they deliver the dat a contained in the memory location spec ified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE
. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPs
are placed in a tri-state condition.
V
DD
V
SS
V
DDQ
V
SSQ
MODE Input-
Power Supply Power Supply Inputs to the Core of the Device
Ground Ground for the Core of the Device
IO Power Supply Power Supply for the IO circuitry
IO Ground Ground for the IO circuitry
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
Static
floating selects interleaved burst sequence. This is a strap pin and must remain static during device
DDQ
or left
operation. Mode pin has an internal pull up.
NC, NC/9M,
NC/18M,
NC/36M,
– No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M,
NC/288M, NC/576M, and NC/1G are address expansion pins that are not int ernall y conn ected to the
die.
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
1
Document #: 38-05516 Rev. *F Page 5 of 22
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CY7C1347G
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (t
The CY7C1347G supports secondary cache in systems using
either a linear or interleaved burst sequence. The linear burst
sequence is suited for processors that use a linear burst
sequence. The burst order is user selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the Address S trobe from Processor (ADSP
Strobe from Controller (ADSC
the burst sequence is controlled by the ADV
on-chip wraparound burst counter captures the first address in a
burst sequence and automatically increments the address for the
rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE
) and Byte Write Select (BW
Enable (GW
) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous Chip Selects (CE
asynchronous Output Enable (OE
selection and output tri-state control. ADSP
HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP
, CE2, CE3 are all asserted active, and (3) the write signals
CE
1
(GW
, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is
HIGH. The address presented to the address inputs (A
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output
Registers. At the rising edge of the next clock the data is allowed
to propagate through the Output Register and onto the data bus
within 2.6 ns (250 MHz device) if OE
exception occurs when the SRAM is emerging from a deselected
state to a selected state, its outputs are always tri-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE
read cycles are supported. After the SRAM is deselected at clock
rise by the chip select and either ADSP
output tri-states immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP
CE
, CE3 are all asserted active. The address presented to
2
is loaded into the Address Register and the address
A
[16:0]
advancement logic while being delivered to the RAM core. The
write signals (GW
ignored during this first cycle.
ADSP
-triggered write accesses require two clock cycles to
complete. If GW
data presented to the DQs and DQPs inputs is written into the
corresponding address location in the RAM core. If GW
then the write operation is controlled by BWE
signals. The CY7C1347G provides byte write capability that is
, BWE, and BW
is asserted LOW on the second clock rise, the
) is 2.6 ns (250 MHz device).
CO
) or the Address
). Address advancement through
input. A two-bit
) inputs. A Global Write
[A:D]
, CE2, CE3) and an
1
) provide for easy bank
is ignored if CE1 is
or ADSC is asserted LOW, (2)
) is
[16:0]
is active LOW. The only
signal. Consecutive single
or ADSC signals, its
is asserted LOW, and (2) CE1,
) and ADV inputs are
[A:D]
is HIGH,
and BW
[A:D]
described in Table 6 on page 8. Asserting the Byte Write Enable
input (BWE
) with the selected Byte Write (BW
tively writes to only the desired bytes.
) input selec-
[A:D]
Bytes not selected during a byte write operation remain
unaltered. A synchronous self-timed write mechanism is
provided to simplify the write operations.
Because the CY7C1347G is a common IO device, the Output
Enable (OE
) must be deasserted HIGH before presenting data
to the DQs and DQPs inputs. Doing so tri-states the output
drivers. As a safety precaution, DQs and DQPs are automatically
tri-stated whenever a write cycle is detected, regardless of the
state of OE
.
Single Write Accesse s Initiated by ADSC
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC
HIGH, (3) CE
appropriate combination of the write inputs (GW
BW
[A:D]
byte(s). ADSC
, CE2, CE3 are all asserted active, and (4) the
1
) are asserted active to conduct a write to the desired
-triggered write accesses require a single clock
cycle to complete. The address presented to A
the address register and the address advancement logic while
being delivered to the RAM core. The ADV input is ignored
during this cycle. If a global write is conducted, the data
presented to the DQs and DQPs is written into the corresponding
address location in the RAM core. If a byte write is conducted,
only the selected bytes are written. Bytes not selected during a
byte write operation remain unaltered. A synchronous self-timed
write mechanism has been provided to simplify the write ope rations.
Because the CY7C1347G is a common IO device, the Output
Enable (OE
) must be deasserted HIGH before presenting data
to the DQs and DQPs inputs. Doing so tri-states the output
drivers. As a safety precaution, DQs and DQPs are automatically
tri-stated whenever a write cycle is detected, regardless of the
state of OE.
is asserted LOW , (2) ADSP is deasserted
, BWE, and
is loaded into
[16:0]
Burst Sequences
The CY7C1347G provides a two-bit wraparound counter, fed by
A
, that implements either an interleaved or linear burst
[1:0]
sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors tha t follow a
linear burst sequence. The burst sequence is user-selectable
through the MODE input.
Asserting ADV
LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected before entering the “sleep” mode. CE
CE
, ADSP, and ADSC must remain inactive for the duration of
3
t
after the ZZ input returns LOW.
ZZREC
, CE2,
1
Document #: 38-05516 Rev. *F Page 6 of 22
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CY7C1347G
Table 2. Interleaved Burst Sequence
Note
2. X = “Do Not Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE
= L when any one or more Byte Write Enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BWA,
BW
B
, BWC, BWD), BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE
signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP
is asserted, regardless of the state of GW, BWE, or BW
[A:D]
. Writes may occur only on subsequent clocks after
the ADSP
or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to allow th e outputs to tri -state. OE is a don't care for
the remainder of the write cycle.
6. OE
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive
or when the device is deselected, and all data bits behave as output when OE
is active (LOW).
Address
A
[1:0]
First
Second
Address
A
[1:0]
Address
A
[1:0]
Third
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Fourth
Address
A
[1:0]
Table 3. Linear Burst Sequence
Address
A
[1:0]
First
Second
Address
A
[1:0]
Address
A
[1:0]
Third
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Fourth
Address
A
[1:0]
Table 4. ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min Max Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Table 5. Truth Table
Snooze mode standby current ZZ > VDD − 0.2V 40 mA
Device operation to ZZ ZZ > VDD − 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ Active to snooze current This parameter is sampled 2t
CYC
CYC
ZZ Inactive to exit snooze current This parameter is sampled 0 ns
[2, 3, 4, 5, 6]
Next Cycle
Add.
Used
CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ
ns
ns
ns
Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State
Deselect Cycle, Power Down None L L X L L X X X X L-H Tri-State
Deselect Cycle, Power Down None L X H L L X X X X L-H Tri-State
Deselect Cycle, Power Down None L L X L H L X X X L-H Tri-State
Deselect Cycle, Power Down None L X H L H L X X X L-H Tri-State
Snooze Mode, Power Down None X X X H X X X X X X Tri-State
Read Cycle, Begin Burst External L H L L L X X X L L-H Q
Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-State
Write Cycle, Begin Burst External L H L L H L X L X L-H D
Read Cycle, Begin Burst External L H L L H L X H L L-H Q
Read Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
Read Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q
Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
Document #: 38-05516 Rev. *F Page 7 of 22
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