Cypress CY7C1345G User Manual

CY7C1345G

4-Mbit (128K x 36) Flow Through Sync SRAM

Features

■ 128K x 36 common IO

■ 3.3V core power supply (V

■ 2.5V or 3.3V IO supply (V

■ Fast clock-to-output times
❐ 6.5 ns (133 MHz version)

■ Provide high performance 2-1-1-1 access rate

■ User selectable burst counter supporting Intel Pentium inter-

leaved or linear burst sequences

■ Separate processor and controller address strobes

■ Synchronous self-timed write

■ Asynchronous output enable

■ Available in Pb-free 100-Pin TQFP package, Pb-free and

non-Pb-free 119-Ball BGA package

■ ZZ Sleep Mode option

DD

DDQ

)

)

Functional Description

The CY7C1345G is a 128K x 36 synchronous cache RAM
designed to interface with high speed microprocessors with
minimum glue logic. The maximum access delay from clock rise
is 6.5 ns (133 MHz version). A two-bit on-chip counter captures
the first address in a burst and increments the address automat­ically for the rest of the burst access. All synchronous inputs are
gated by registers controlled by a positive edge triggered Clock
Input (CLK). The synchronous inputs include all addresses, all
data inputs, address pipelining Chip Enable (CE
expansion Chip Enables (CE
(ADSC

, ADSP,
Global Write (GW
Enable (OE

) and the ZZ pin.

ADV), Write Enables (BW

and

). Asynchronous inputs include the Output

and CE3), Burst Control inputs

2

,

x

The CY7C1345G enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses are initiated with the Processor
Address Strobe (ADSP

) inputs.

(ADSC

) or the cache Controller Address Strobe

Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
Strobe Controller (

) is active. Subsequent burst addresses

ADSC

are internally generated as controlled by the Advance pin (ADV
The CY7C1345G operates from a +3.3V core power supply

while all outputs operate with either a +2.5 or +3.3V supply. All
inputs and outputs are JEDEC standard JESD8-5 compatible.

For best practice recommendations, refer to the Cypress appli­cation note AN1064, SRAM System Guidelines.

), depth

1

and BWE

) or Address

), and

).

Selection Guide

Parameter 133 MHz 100 MHz Unit

Maximum Access Time 6.5 8.0 ns

Maximum Operating Current 225 205 mA

Maximum Standby Current 40 40 mA

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-05517 Rev. *E Revised July 15, 2007

Logic Block Diagram

CY7C1345G

A0, A1, A

MODE

ADV

CLK

ADSC

ADSP

BW

BW

BW

BW

BWE

GW

CE1

CE2

CE3

ADDRESS
REGISTER

BURST

COUNTER

AND LOGIC

CLR

D

D

DQ

,

D

C

B

A

DQP

BYTE

BYTE

WRITE REGISTER

WRITE REGISTER

DQ

C

DQP

,

BYTE

WRITE REGISTER

B

DQP

DQ

,

BYTE

WRITE REGISTER

DQ

A

DQP

,

BYTE

WRITE REGISTER

ENABLE

REGISTER

C

B

A

[1:0]

A

Q1

Q0

DQ

DQP

D

,

D

BYTE

WRITE REGISTER

DQ

C

DQP

C

,

BYTE

WRITE REGISTER

B

DQP

DQ

,

BYTE

WRITE REGISTER

A

DQP

DQ

,

BYTE

WRITE REGISTER

MEMORY

B

A

ARRAY

SENSE
AMPS

OUTPUT
BUFFERS

INPUT

REGISTERS

DQP

DQP

DQP

DQP

DQ s

A

B

C

D

OE

ZZ

SLEEP

CONTROL

Document Number: 38-05517 Rev. *E Page 2 of 20

Pin Configurations

CY7C1345G

100-Pin TQFP Pinout

BYTE C

BYTE D

DQP

DQ

DQ

V

DDQ

V

SSQ

DQ

DQ

DQ

DQ

V

SSQ

V

DDQ

DQ

DQ

V

NC

V

DQ

DQ

V

DDQ

V

SSQ

DQ

DQ

DQ

DQ

V

SSQ

V

DDQ

DQ

DQ

DQP

NC

DD

SS

A

100

1

C

2

C

3

C

CE

CE

99989796959493929190898887868584838281

2BWDBWC

1

A

4

5

6

C

7

C

8

C

9

C

10

11

12

C

13

C

14

15

16

17

18

D

19

D

20

21

22

D

23

D

24

D

25

D

26

27

28

D

29

D

30

D

3

A

CE

BWBBW

VDDV

CY7C1345G

SS

CLK

GW

BWE

OE

ADSC

ADSP

ADV

A

A

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQP

DQ

B

DQ

B

V

DDQ

V

SSQ

DQ

B

DQ

B

DQ

B

DQ

B

V

SSQ

V

DDQ

DQ

B

DQ

B

V

SS

NC

V

DD

ZZ

DQ

A

DQ

A

V

DDQ

V

SSQ

DQ

A

DQ

A

DQ

A

DQ

A

V

SSQ

V

DDQ

DQ

A

DQ

A

DQPA

B

BYTE B

BYTE A

31323334353637383940414243444546474849

AAAAA1A

MODE

0

NC/72M

SS

V

NC/36M

DD

V

NC/18M

NC/9M

AAAAA

50

A

A

Document Number: 38-05517 Rev. *E Page 3 of 20

Pin Configurations (continued)

CY7C1345G

119-Ball BGA Pinout

A

B

C

D

E

F

G

H

J

K

L

M
N

P

R

T

U

V

DDQ

NC/288M

NC/144M

DQ

C

DQ

C

V

DDQ

DQ

C

DQ

C

V

DDQ

DQ

D

DQ

D

V

DDQ

DQ

D

DQ

D

NC

NC

V

DDQ

2

AA AA

CE

2

DQP

C

DQ

C

DQ

C

DQ

C

DQ

C

V

DD

DQ

D

DQ

D

DQ

D

DQ

D

DQP

D

A

345671

ADSP

A

AA

V

SS

V

SS

V

SS

BW

C

V

SS

NC V

V

SS

BW

D

V

SS

V

SS

V

SS

MODE

ADSC

V

DD

NC

CE

1

OE

ADV

GW

DD

CLK

NC

BWE

A1

A0

V

DD

A

V

V

V

BW

V

NC

V

BW

V

V

V

NC

SS

SS

SS

B

SS

SS

A

SS

SS

SS

AAA

NCNCNCNC

DQP

DQP

NC/36MNC/72M

CE

DQ

DQ

DQ

DQ

V

DQ

DQ

DQ

DQ

NC

A

3

AA

B

B

B

B

B

DD

A

A

A

A

A

A

V

DDQ

NC/576M

NC/1G

DQ

B

DQ

B

V

DDQ

DQ

B

DQ

B

V

DDQ

DQ

A

DQ

A

V

DDQ

DQ

A

DQ

A

NC

ZZ

V

DDQ

Document Number: 38-05517 Rev. *E Page 4 of 20

CY7C1345G

Pin Definitions

Name IO Description

A0, A1, A Input

Synchronous

BW

A, BWB

BWC, BW

D

Input

Synchronous

GW Input

Synchronous

BWE

Input

Synchronous

CLK Input Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst

CE

1

Input

Synchronous

Address Inputs Used to Select One of the 128K Address Locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A
the two-bit counter.

[1:0]

feed

Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.

Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW

and BWE).

[A:D]

Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal is asserted
LOW to conduct a byte write.

counter when ADV

is asserted LOW, during a burst operation.

Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE

and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only

2

when a new external address is loaded.

CE

CE

2

3

Input

Synchronous

Input

Synchronous

OE Input

Asynchronous

ADV

Input

Synchronous

ADSP Input

Synchronous

ADSC

Input

Synchronous

ZZ Input

Asynchronous

DQs
DQP
DQP

V

DD

V

SS

V

DDQ

V

SSQ

A,
C,

DQP

DQP

B

D

IO

Synchronous

Power Supply Power supply inputs to the core of the device.

Ground Ground for the core of the device.

IO Power

Supply

IO Ground Ground for the IO circuitry.

Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

and CE3 to select or deselect the device. CE2 is sampled only when a new external address is

CE

1

loaded.

Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE

and CE2 to select or deselect the device. CE3 is sampled only when a new external address is

1

loaded.

Output Enable, asynchronous Input, Active LOW. Controls the direction of the IO pins. When
LOW, the IO pins act as outputs. When deasserted HIGH, IO pins are tri-stated and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.

Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically incre­ments the address in a burst cycle.

Address Strobe from Processor, sampled on the rising edge of CLK, Active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A
also loaded into the burst counter. When ADSP
nized. ASDP

is ignored when CE1 is deasserted HIGH.

and ADSC are both asserted, only ADSP is recog-

[1:0]

are

Address Strobe from Controller, sampled on the rising edge of CLK, Active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A
also loaded into the burst counter. When ADSP

and ADSC are both asserted, only ADSP is recog-

[1:0]

are

nized.

ZZ sleep Input, Active HIGH. When asserted HIGH places the device in a non-time critical sleep
condition with data integrity preserved. During normal operation, this pin is low or left floating. ZZ pin
has an internal pull down.

Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by the addresses presented during the previous clock rise of the read cycle. The direction of the pins
is controlled by
DQP

are placed in a tri-state condition.

[A:D]

. When OE is asserted LOW, the pins act as outputs. When HIGH, DQs and

OE

Power supply for the IO circuitry.

Document Number: 38-05517 Rev. *E Page 5 of 20

Pin Definitions (continued)

Name IO Description

MODE Input

Static

NC No Connects. Not Internally connected to the die.

NC/9M,

– No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M,
NC/18M,
NC/36M
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
floating selects interleaved burst sequence. This is a strap pin and must remain static during device
operation. Mode Pin has an internal pull up.

NC/288M, NC/576M, and NC/1G are address expansion pins and are not internally connected to the
die.

CY7C1345G

or left

DD

Functional Overview

All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (tCO) is 6.5 ns (133 MHz device).

The CY7C1345G supports secondary cache in systems using
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486™ processors. The linear
burst sequence is suited for processors that use a linear burst
sequence. The burst order is user selectable and is determined
by sampling the MODE input. Accesses are initiated with either
the Processor Address Strobe (ADSP
Strobe (ADSC

). Address advancement through the burst
sequence is controlled by the ADV
around burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.

Byte write operations are qualified with the Byte Write Enable
(BWE

) and Byte Write Select (BW

Enable (GW

) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.

Three synchronous Chip Selects (CE
asynchronous Output Enable (OE
selection and output tri-state control. ADSP
HIGH.

Single Read Accesses

A single read access is initiated when the following conditions
are satisfied at clock rise:

1. CE

, CE2, and CE3 are all asserted active.

1

2. ADSP

The address presented to the address inputs is latched into the
address register and the burst counter or control logic and
presented to the memory core. If the OE input is asserted LOW,
the requested data is available at the data outputs a maximum
to t

or ADSC is asserted LOW (if the access is initiated by

ADSC

, the write inputs are deasserted during this first cycle).

after clock rise. ADSP is ignored if CE1 is HIGH.

CDV

) or the Controller Address

input. A two-bit on-chip wrap

) inputs. A Global Write

[A:D]

, CE2, and CE3) and an

1

) provide for easy bank

is ignored if CE1 is

Single Write Accesses Initiated by ADSP

Single write access is initiated when the following conditions are
satisfied at clock rise:

1. CE

, CE2, and CE3 are all asserted active

1

2. ADSP

is asserted LOW.

The addresses presented are loaded into the address register
and the burst inputs (GW

, BWE, and BWx) are ignored during this
first clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data is latched and
written into the device. Byte writes are allowed. During byte
writes, BW
DQ

C

write. Since this is a common IO device, the asynchronous OE

controls DQA and BWB controls DQB, BWC controls

A

, and BWD controls DQD. All IOs are tri-stated during a byte

input signal is deasserted and the IOs are tri-stated prior to the
presentation of data to DQ
lines are tri-stated once a write cycle is detected, regardless of
the state of OE

.

. As a safety precaution, the data

s

Single Write Accesses Initiated by ADSC

This write access is initiated when the following conditions are
satisfied at clock rise:

1. CE

, CE2, and CE3 are all asserted active.

1

2. ADSC

3. ADSP

4. The write input signals (GW

The addresses presented are loaded into the address register
and the burst counter or control logic and delivered to the
memory core. The information presented to DQ
into the specified address location. Byte writes are allowed.
During byte writes, BW
controls DQC, and BWD controls DQD. All IOs and even a byte
write are tri-stated when a write is detected. Since this is a
common IO device, the asynchronous OE
deasserted and the IOs are tri-stated prior to the presentation of
data to DQs. As a safety precaution, the data lines are tri-stated
once a write cycle is detected, regardless

is asserted LOW.

is deasserted HIGH

access. ADSC

is ignored if ADSP is active LOW.

, BWE, and BWx) indicate a write

[D:A]

controls DQA, BWB controls DQB, BW

A

input signal is

of the state of OE

is written

.

C

Document Number: 38-05517 Rev. *E Page 6 of 20