Cypress CY7C1339G User Manual

CY7C1339G

4-Mbit (128K x 32) Pipelined Sync SRAM

Features

• Registered inputs and outputs for pipelined operation

• 128K × 32 common I/O architecture

• 3.3V core power supply (V

• 2.5V/3.3V I/O power supply (V

• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel
Pentium

®

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Available in lead-free 100-Pin TQFP package, lead-free
and non-lead-free 119-Ball BGA package

• “ZZ” Sleep Mode Option

DD

)

DDQ

)

®

Functional Description

[1]

The CY7C1339G SRAM integrates 128K x 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE

), depth-expansion Chip Enables (CE2 and CE3), Burst

1

Control inputs (ADSC
(BW
inputs include the Output Enable (OE

, and BWE), and Global Write (GW). Asynchronous

[A:D]

, ADSP,

ADV), Write Enables

and

) and the ZZ pin.

Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
Address Strobe Controller (ADSC

) are active. Subsequent

) or

burst addresses can be internally generated as controlled by
the Advance pin (ADV

).

Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. GW

causes all bytes to be written.

LOW

when active

The CY7C1339G operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.

Logic Block Diagram

A0,A1, A

MODE

ADV

CLK

ADSC

ADSP

BW

D

BW

C

BW

B

BW

A

BWE

GW

CE

1

CE

2

CE

3

OE

ZZ

1

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

WRITE REGISTER

WRITE REGISTER

WRITE REGISTER

WRITE REGISTER

SLEEP

CONTRO L

D

DQ

BYTE

C

DQ
BYTE

B

DQ

BYTE

DQ
BYTE

ENABLE

REGISTER

A

ADDRESS
REGISTER

2

BURST

COUNTE R

CLR

LOGIC

PIPELINED

ENABLE

AND

A

[1:0]

Q1

Q0

D

DQ
BYTE

WRITE DRIVER

C

DQ

BYTE

WRITE DRIVER

B

DQ

BYTE

WRITE DRIVER

DQ

A

BYTE

WRITE DRIVER

MEMORY

ARRAY

SENSE
AMPS

OUTPUT

REGISTERS

OUTPUT
BUFFE R S

E

INPUT

REGISTERS

DQs

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05520 Rev. *F Revised July 5, 2006

[+] Feedback

CY7C1339G

Selection Guide

250 MHz 200 MHz 166 MHz 133 MHz Unit

Maximum Access Time 2.6 2.8 3.5 4.0 ns
Maximum Operating Current 325 265 240 225 mA
Maximum CMOS Standby Current 40 40 40 40 mA

Pin Configurations

100-Pin TQFP Pinout

BYTE C

BYTE D

V

V

V

V

V

V

V

V

DQ
DQ

DDQ
SSQ

DQ
DQ
DQ
DQ

SSQ
DDQ

DQ
DQ

V

V
DQ
DQ

DDQ

SSQ

DQ
DQ
DQ
DQ

SSQ

DDQ

DQ
DQ

NC

NC

DD

NC

SS

NC

AACE1CE2BWDBWCBWBBWACE3VDDVSSCLKGWBWEOEADSC

100999897969594939291908988878685848382

1

C
C

2
3
4
5

C
C
C
C

6
7
8
9
10
11

C
C

12
13
14
15
16
17

D
D

18
19

CY7C1339G

20
21

D
D
D
D

22
23
24
25
26
27

D
D

28
29
30

ADSP

ADVAA

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

81

NC
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
V
NC
V
ZZ
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
NC

DDQ
SSQ

SSQ
DDQ

SS

DD

DDQ
SSQ

SSQ
DDQ

B
B

B

BYTE B

B
B
B

B
B

A
A

A
A

BYTE A

A
A

A
A

31323334353637383940414243444546474849

1

A

MODE

AAA

0

A

A

NC/72M

NC/36M

SS

V

V

DD

NC/18M

AAA

NC/9M

AAA

50

A

Document #: 38-05520 Rev. *F Page 2 of 18

[+] Feedback

Pin Configurations (continued)

A

NC/288M

B

NC/144M

C
D

E
F
G
H
J
K
L

M

N
P

R
T
U

V

DQ

V

DQ
DQ

V

DQ
DQ

V

DQ
DQ

V

DDQ

DDQ

DDQ

DDQ

NC
NC

DDQ

CY7C1339G

119-Ball BGA Pinout

2345671

AA AA

CE

2

A
AA

C
C

C
C

D
D

D
D

NCDQ
DQ
DQ
DQ
DQ

V

DQ
DQ

DQ
DQ

NC

C
C
C
C

DD

D
D

D
D

A

V

SS

V

SS

V

SS

BW

V

SS

NC V

V

SS

BW

V

SS

V

SS

V

SS

MODE

AAA

ADSP

NC/9M

V
V
V

BW

V

NC

V

BW

V
V

V

NC

A

SS
SS
SS

SS

SS

SS
SS

SS

AA

NC
DQ
DQ
DQ

B

DQ
V

DD

DQ
DQ

A

DQ
DQ

NC

A

ADSC

V

DD

NC

CE

1

OE

ADV

c

GW

DD

CLK

D

NC

BWE

A1
A0

V

DD

NC/36MNC/72M

NCNCNCNC

NC

B
B
B
B

A
A

A
A

V

DDQ

NC/576M

NC/1G

DQ

B

DQ

B

V

DDQ

DQ

B

DQ

B

V

DDQ

DQ

A

DQ

A

V

DDQ

DQ

A

DQ

A

NC

ZZ

V

DDQ

Pin Definitions

Name I/O Description

A0, A1, A Input-

Synchronous

BW

, BW

A

BWC, BW
GW

B
D

Input-

Synchronous

Input-

Synchronous

BWE

Input-

Synchronous

CLK Input-

Clock

CE

CE

CE

OE

1

2

3

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Asynchronous

Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
of the CLK if ADSP
are fed to the two-bit counter.

or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1, A0

.

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV

is asserted LOW, during a burst operation.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1

CE

2

when a new external address is loaded.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

CE

and CE3 to select/deselect the device.CE

1

loaded.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE

and CE2 to select/deselect the device. CE3 is sampled only when a new external address is

1

loaded. Not connected for BGA. Where referenced, CE
document for BGA.

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE

is masked during the first clock of a read cycle when emerging from a

deselected state.

and BWE).

[A:D]

is sampled only

is sampled only when a new external address is

2

is assumed active throughout this

3

Document #: 38-05520 Rev. *F Page 3 of 18

[+] Feedback

Pin Definitions (continued)

Name I/O Description

ADV Input-

Synchronous

ADSP

Input-

Synchronous

ADSC

Input-

Synchronous

ZZ Input-

Asynchronous

DQs

I/O-

Synchronous

V
V
V

V

DD
SS
DDQ

SSQ

Power Supply Power supply inputs to the core of the device.

Ground Gro un d f or the co r e of the device.

I/O Power

Supply

I/O Ground Ground for the I/O circuitry.

MODE Input-

Static

NC,NC/9M,

– No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/72M, NC/144M,
NC/18M.
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G

Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst cycle.

Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1, A0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP

is ignored when CE1 is deasserted HIGH.

Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1, A0
are also loaded into the burst counter. When ADSP
recognized.

ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The direction
of the pins is controlled by OE

. When OE is asserted LOW, the pins behave as outputs. When

HIGH, DQs are placed in a tri-state condition.

Power supply for the I/O circuitry.

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V

floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode Pin has an internal pull-up.

NC/288M, NC/576M and NC/1G are address expansion pins are not internally connected to the
die.

CY7C1339G

and ADSC are both asserted, only ADSP is

or left

DD

Functional Overview

all four bytes. All writes are simplified with on-chip

synchronous self-timed Write circuitry.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t
(250-MHz device).

) is 2.6 ns

CO

The CY7C1339G supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP

) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.

Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
Enable (GW

) overrides all Byte Write inputs and writes data to

) inputs. A Global Write

[A:D]

Three synchronous Chip Selects (CE
asynchronous Output Enable (OE
selection and output tri-state control. ADSP
is HIGH.

Single Read Accesses

This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP

, CE2, CE3 are all asserted active, and (3) the Write

CE

1

signals (GW
CE

is HIGH. The address presented to the address inputs (A)

1

is stored into the address advancement logic and the Address

, BWE) are all deserted HIGH. ADSP is ignored if

or ADSC is asserted LOW, (2)

Register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 2.6 ns (250-MHz device) if OE
LOW. T he only exce ption oc curs when the SRAM is emergin g
from a deselected state to a selected state, its outputs are
always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE

, CE2, CE3) and an

1

) provide for easy bank

is ignored if CE

is active

Document #: 38-05520 Rev. *F Page 4 of 18

1

[+] Feedback

CY7C1339G

signal. Consecutive single Read cycles are supported. Once
the SRAM is deselected at clock rise by the chip select and
either ADSP or ADSC signals, its output will tri-state immedi­ately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP
(2) CE
presented to A is loaded into the address register and the

, CE2, CE3 are all asserted active. The address

1

is asserted LOW, and

address advancement logic while being delivered to the
memory array. The Write signals (GW

inputs are ignored during this first cycle.

ADV

, BWE, and BW

[A:D]

) and

ADSP-triggered Write accesses require two clock cycles to
complete. If GW

is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corre­sponding address location in the memory array. If GW
then the Write operation is controlled by BWE
signals. The CY7C1339G provides Byte Write capability that

is HIGH,

and BW

[A:D]

is described in the Write Cycle Descriptions table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Write ( BW
bytes. Bytes not selected during a Byte Write operation will

) input, will selectively write to only the desired

[A:D]

remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.

Because the CY7C1339G is a common I/O device, the Output
Enable (OE

) must be deserted HIGH before presenting data
to the DQs inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE

.

Single Write Accesses Initiated by ADSC

ADSC Write accesses are initiated when the following condi­tions are satisfied: (1) ADSC
deserted HIGH, (3) CE
(4) the appropriate combination of the Write inputs (GW
and BW
desired byte(s). ADSC

) are asserted active to conduct a Write to the

[A:D]

is asserted LOW, (2) ADSP is

, CE2, CE3 are all asserted active, and

1

, BWE,

-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the memory array.
The ADV

input is ignored during this cycle. If a global Write is
conducted, the data presented to the DQs is written into the
corresponding address location in the memory core. If a Byte
Write is conducted, only the selected bytes are written. Bytes
not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.

Because the CY7C1339G is a common I/O device, the Output
Enable (OE

) must be deserted HIGH before presenting data

to the DQs inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE

.

Burst Sequences

The CY7C1339G provides a two-bit wraparound counter, fed
by A1, A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif­ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user se lectable
through the MODE input.

Asserting ADV

LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
remain inactive for the duration of t
returns LOW.

, CE2, CE3, ADSP, and ADSC must

1

after the ZZ input

ZZREC

Interleaved Burst Address Table
(MODE = Floating or V

First

Address

A1, A0

00 01 10 11
01 00 11 10
10 11 00 01

11 10 01 00

Second

Address

A1, A0

DD

)

Third

Address

A1, A0

Fourth

Address

A1, A0

Linear Burst Address Table (MODE = GND)

First

Address

A1, A0

00 01 10 11
01 10 11 00
10 11 00 01

11 00 01 10

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Document #: 38-05520 Rev. *F Page 5 of 18

Snooze mode standby current ZZ > VDD – 0.2V 40 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ active to snooze current This parameter is sampled 2t

CYC

CYC

ns
ns
ns

ZZ Inactive to exit snooze current This parameter is sampled 0 ns

[+] Feedback

CY7C1339G

Truth Table

[2, 3, 4, 5, 6, 7]

Operation Add. Used CE1CE2CE

ADSP ADSC ADV WRITE OE CLK DQ

ZZ

3

Deselect Cycle, Power-down None H X X L X L X X X L-H Tri-State
Deselect Cycle, Power-down None L L X L L X X X X L-H Tri-State
Deselect Cycle, Power-down None L X H L L X X X X L-H Tri-State
Deselect Cycle, Power-down None L L X L H L X X X L-H Tri-State
Deselect Cycle, Power-down None L X H L H L X X X L-H Tri-State
Snooze Mode, Power-down None X X X H X X X X X X Tri-State
READ Cycle, Begin Burst External L H L L L X X X L L-H Q
READ Cycle, Begin Burst External L H L L L X X X H L-H Tri-State
WRITE Cycle, Begin Burst External L H L L H L X L X L-H D
READ Cycle, Begin Burst External L H L L H L X H L L-H Q
READ Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
READ Cycle, Continue Burst Next X X X L H H L H L L-H Q
READ Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State
READ Cycle, Continue Burst Next H X X L X H L H L L-H Q
READ Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D
WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D
READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q
READ Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State
READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q
READ Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State
WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D
WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D

Notes:

2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

3. WRITE

4. The DQ pins are controlled by the current cycle and the

5. CE

6. The SRAM always initiates a read cycle when ADSP

7. OE

= L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW= L. WRITE = H when all Byte write enable signals

(BW

, BWB, BWC, BWD), BWE, GW = H.

A

, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.

1

after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is

inactive or when the device is deselected, and all data bits behave as output when OE

signal. OE is asynchronous and is not sampled with the clock.

OE

is asserted, regardless of the state of GW, BWE, or BW

is active (LOW).

. Writes may occur only on subsequent clocks

[A: D]

Document #: 38-05520 Rev. *F Page 6 of 18

[+] Feedback