Cypress CY7C1338G User Manual
CY7C1338G
A
s
4-Mbit (128K x 32) Flow-Through Sync SRAM
Features
• 128K x 32 common I/O
• 3.3V core power supply (V
• 2.5V or 3.3V I/O supply (V
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in lead-free 100-Pin TQFP package, lead-free
and non-lead-free 119-Ball BGA package
• “ZZ” Sleep Mode option
DD
DDQ
)
)
®
Functional Description
The CY7C1338G is a 128K x 32 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-trigg ered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
), depth-expansion Chip Enables (CE2 and CE3), Burst
1
Control inputs (ADSC
(BW
inputs include the Output Enable (OE
The CY7C1338G allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP
Address Strobe (ADSC
controlled by the Address Advancement (ADV
, and BWE), and Global Write (GW). Asynchronous
[A:D]
[1]
, ADSP, and ADV), Write Enables
) and the ZZ pin.
) or the cache Controller
) inputs. Address advancement is
) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
Address Strobe Controller (ADSC
) are active. Subsequent
) or
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1338G operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram
0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW
D
BW
BWE
BW
C
BW
B
A
GW
CE1
CE2
CE3
OE
ZZ
SLEEP
CONTROL
WRITE REGISTER
WRITE REGISTER
WRITE REGISTER
WRITE REGISTER
ADDRESS
REGISTER
BURST
COUNTER
AND LOGIC
CLR
D
BYTE
DQ
C
BYTE
DQ
B
BYTE
DQ
DQ
A
BYTE
ENABLE
REGISTER
A
[1:0]
Q1
Q0
DQ
D
BYTE
WRITE REGISTER
DQ
C
BYTE
WRITE REGISTER
DQ
B
BYTE
WRITE REGISTER
DQ
A
BYTE
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
INPUT
REGISTERS
DQ
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05521 Rev. *D Revised July 5, 2006
CY7C1338G
Selection Guide
133 MHz 100 MHz Unit
Maximum Access Time 6.5 8.0 ns
Maximum Operating Current 225 205 mA
Maximum Standby Current 40 40 mA
Pin Configurations
100-Pin TQFP Pinout
BYTE C
BYTE D
V
V
V
V
V
V
V
V
NC
DQ
DQ
DDQ
SSQ
DQ
DQ
DQ
DQ
SSQ
DDQ
DQ
DQ
V
NC
V
DQ
DQ
DDQ
SSQ
DQ
DQ
DQ
DQ
SSQ
DDQ
DQ
DQ
NC
NC
DD
SS
A
100
CE
CE
99989796959493929190898887868584838281
2BWDBWC
1
A
1
2
C
3
C
4
5
6
C
7
C
8
C
9
C
10
11
12
C
13
C
14
15
16
17
18
D
19
D
20
21
22
D
23
D
24
D
25
D
26
27
28
D
29
D
30
3
A
CE
BWBBW
VDDV
CY7C1338G
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
NC
B
B
B
B
B
B
B
B
A
A
A
A
A
A
A
A
BYTE B
BYTE A
31323334353637383940414243444546474849
AAAAA1A
MODE
0
NC/72M
NC/36M
SS
DD
V
V
NC/9M
NC/18M
AAAAA
50
A
A
Document #: 38-05521 Rev. *D Page 2 of 17
Pin Configurations (continued)
A
NC/288M
B
NC/144M
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DQ
V
DQ
DQ
V
DQ
DQ
V
DQ
DQ
V
DDQ
DDQ
DDQ
DDQ
NC
NC
DDQ
CY7C1338G
119-Ball BGA Pinout
2
AA AA
CE
2
C
C
C
C
D
D
D
D
NCDQ
DQ
DQ
DQ
DQ
V
DQ
DQ
DQ
DQ
NC
C
C
C
C
DD
D
D
D
D
A
345671
ADSP
A
AA
V
SS
V
SS
V
SS
BW
C
V
SS
NC V
V
SS
BW
D
V
SS
V
SS
V
SS
MODE
ADSC
V
DD
NC
CE
1
OE
ADV
GW
DD
CLK
NC
BWE
A1
A0
V
DD
A
V
V
V
BW
V
NC
V
BW
V
V
V
NC
SS
SS
SS
B
SS
SS
A
SS
SS
SS
AAA
NCNCNCNC
A
NC/9M
AA
NC
DQ
DQ
DQ
DQ
V
DD
DQ
DQ
DQ
DQ
NC
A
NC/36MNC/72M
NC
B
B
B
B
A
A
A
A
V
DDQ
NC/576M
NC/1G
DQ
B
DQ
B
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
NC
ZZ
V
DDQ
Pin Definitions
Name I/O Description
A0, A1, A Input-
Synchronous
BWA, BW
BWC, BW
B
D
Input-
Synchronous
GW Input-
Synchronous
BWE
Input-
Synchronous
CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
CE
CE
CE
OE
1
2
3
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
ADV Input-
Synchronous
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
of the CLK if ADSP
the 2-bit counter.
or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A
[1:0]
feed
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW
and BWE).
[A:D]
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
counter when ADV
is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only
CE
2
when a new external address is loaded.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE3 to select/deselect the device. CE2 is sampled only when a new external address is
1
loaded.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
and CE2 to select/deselect the device. CE3 is sampled only when a new external address is
CE
1
loaded.
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected
state.
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
Document #: 38-05521 Rev. *D Page 3 of 17
Pin Definitions (continued)
Name I/O Description
ADSP
ADSC
ZZ Input-
DQs I/O-
V
DD
V
SS
V
DDQ
V
SSQ
MODE Input-
NC No Connects. Not Internally connected to the die.
NC/9M,
NC/18M
NC/36M
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A
also loaded into the burst counter. When ADSP
Input-
Synchronous
nized. ASDP
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are captured in the address registers. A
into the burst counter. When ADSP
is ignored when CE1 is deasserted HIGH
and ADSC are both asserted, only ADSP is recognized.
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”
Asynchronous
condition with data integrity preserved. During normal operation, this pin has to be low or left floating.
ZZ pin has an internal pull-down.
Bidirectional Data I/O lines. As input s, they feed into an on-chip data register that is triggered by
Synchronous
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by the addresses presented during the previous clock rise of the read cycle. The direction of the
pins is controlled by OE
. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs
are placed in a tri-state condition.
Power
Power supply inputs to the core of the device.
Supply
Ground Ground for the core of the device.
I/O Power
Power supply for the I/O circuitry.
Supply
I/O Ground Ground for the I/O circuitry.
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
Static
floating selects interleaved burst sequence. This is a strap pin and should remain static during device
operation. Mode Pin has an internal pull-up.
– No Connects. Not internally connected to the die. NC/9M,NC/18M,NC/36M,NC/72M, NC/144M,
NC/288M, NC/576M and NC/1G are address expansion pins that are not internally connected to
the die.
CY7C1338G
are
DD
[1:0]
or left
and ADSC are both asserted, only ADSP is recog-
are also loaded
[1:0]
Functional Overview
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access d elay from
the clock rise (t
) is 6.5 ns (133-MHz device).
C0
The CY7C1338G supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE
asynchronous Output Enable (OE
, CE2, CE3) and an
1
) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE
is HIGH.
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP
(ADSC
). Address advancement through the burst sequence is
controlled by the ADV
) or the Controller Address Strobe
input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE
) and Byte Write Select (BW
) inputs. A Global Write
[A:D]
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
asserted active, and (2) ADSP
the access is initiated by ADSC
, CE2, and CE3 are all
1
or ADSC is asserted LOW (if
, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE
available at the data outputs a maximum to t
rise. ADSP
input is asserted LOW, the requested data will be
after clock
is ignored if CE1 is HIGH.
CDV
Document #: 38-05521 Rev. *D Page 4 of 17
1
CY7C1338G
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, and (2) ADSP
is asserted LOW. The addresses
, CE2, CE3 are all asserted
1
presented are loaded into the address register and the burst
inputs (GW
clock cycle. If the write inputs are asserted active (see Write
, BWE, and BW[
])are ignored during this first
A:D
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BW
BWC
controls DQC, and BWD controls DQD. All I/Os are
controls DQA and BWB controls DQB.
A
tri-stated during a byte write.Since this is a common I/O
device, the asynchronous OE input signal must be deasserted
and the I/Os must be tri-stated prior to the presentation of data
to DQs. As a safety precaution, the data lines are tri -stated
once a write cycle is detected, regardless of the state of OE
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, (2) ADSC
is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW
indicate a write access. ADSC
, CE2, and CE3 are all asserted
1
is ignored if ADSP is active
, BWE, and BW
[A:D]
LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ
written into the specified address location. Byte writes are
[A:D]
will be
allowed. During byte writes, BWA controls DQA, BWB controls
DQ
, BWC controls DQC, and BWD controls DQD. All I/Os are
B
tri-stated when a writ e is detected, even a byte write. Since this
is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless
of the state of OE
.
Burst Sequences
The CY7C1338G provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by
A[1:0], and can follow either a linear or interleaved burst order.
The burst order is determined by the state of the MODE input.
A LOW on MODE will select a linear burst sequence. A HIGH
on MODE will select an interleaved burst order. Leaving
MODE unconnected will cause the device to default to a interleaved burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
inactive for the duration of t
.
LOW.
s, ADSP, and ADSC must remain
after the ZZ input returns
ZZREC
Interleaved Burst Address Table
(MODE = Floating or V
)
First
Address
A1, A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Second
Address
A1, A0
DD
)
Third
Address
A1, A0
Linear Burst Address Table (MODE = GND)
First
Address
A1, A
0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
A1, A
0
Third
Address
A1, A
0
Fourth
Address
A1, A0
Fourth
Address
A1, A
0
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Document #: 38-05521 Rev. *D Page 5 of 17
Sleep mode standby current ZZ > VDD – 0.2V 40 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to sleep current This parameter is sampled 2t
CYC
CYC
ns
ns
ns
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
CY7C1338G
Truth Table
[2, 3, 4, 5, 6]
Address
Cycle Description
Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ
Deselected Cycle, Power-down None H X X L X L X X X L-H Tri-State
Deselected Cycle, Power-down None L L X L L X X X X L-H Tri-State
Deselected Cycle, Power-down None L X H L L X X X X L-H Tri-State
Deselected Cycle, Power-down None L L X L H L X X X L-H Tri-State
Deselected Cycle, Power-down None X X X L H L X X X L-H Tri-State
Sleep Mode, Power-down None X X X H X X X X X X Tri-State
Read Cycle, Begin Burst External L H L L L X X X L L-H Q
Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-State
Write Cycle, Begin Burst External L H L L H L X L X L-H D
Read Cycle, Begin Burst External L H L L H L X H L L-H Q
Read Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q
Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
Write Cycle, Continue Burst Next X X X L H H L L X L-H D
Write Cycle, Continue Burst Next H X X L X H L L X L-H D
Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q
Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State
Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q
Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State
Write Cycle, Suspend Burst Cur rent X X X L H H H L X L-H D
Write Cycle, Suspend Burst Cur rent H X X L X H H L X L-H D
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE
4. The DQ pins are controlled by the current cycle and the OE
5. The SRAM always initiates a read cycle when ADSP
6. OE
= L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW= L. WRITE = H when all Byte write enable signals
(BW
, BWB, BWC, BWD), BWE, GW = H.
A
after the ADSP
don't care for the remainder of the write cycle.
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE
or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
signal. OE is asynchronous and is not sampled with the clock.
is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks
is active (LOW).
Document #: 38-05521 Rev. *D Page 6 of 17
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