Cypress CY7C1333H User Manual

PRELIMINARY

s

C

C

2-Mbit (64K x 32) Flow-Through SRAM

Features

• Can support up to 133-MHz bus operations with zero
wait states.

— Data is transferred on every clock.

• Pin compatible and functionally equivalent to ZBT™
devices

• Internally self-timed output buffer control to eliminate
the need to use

• Registered inputs for flow-through operation

• Byte Write capability

• 64K x 32 common I/O architectu re

• Single 3.3V power supply

• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 8.0 ns (for 100-MHz device)

• Clock Enable (CEN

• Synchronous self-timed writes Offered in Lead-Free

• Asynchronous Output Enable

• Offered in Lead-Free JEDEC-standard 100 TQFP
package

• Burst Capability—linea r or interleaved burst order

OE

) pin to suspend operation

CY7C1333H

with NoBL™ Architecture

• Low standby power

Functional Description

The CY7C1333H is a 3.3V, 64K x 32 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1333H is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified b y
the Clock Enable (CEN
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).

Write operations are controlled by the two Byte Write Select
(BW
conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.

) and a Write Enable (WE) input. All writes are

[A:D]

[1]

) signal, which when deasserted

, CE2, CE3) and an

1

) provide for easy bank

Logic Block Diagram

A0, A1, A

MODE

ADV/LD

BW
BW
BW
BW

C

WE

CE1
CE2
CE3

ZZ

LK
EN

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

CE

A

B

C

D

OE

ADDRESS
REGISTER

ADV/LD

WRITE ADDRESS

REGISTER

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

READ LOGIC

SLEEP
Control

A1

D1

A0

D0

BURST

C

LOGIC

A1'

Q1

A0'

Q0

O
U
T
P

D

WRITE

DRIVERS

MEMORY

ARRAY

INPUT

REGISTER

S

E
N
S
E

A
M
P
S

E

U

A

T

T
A

B
U

S

F

T

F

E

E

E

R

R

S

I

E

N
G

DQ

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 001-00209 Rev. ** Revised April 11, 2005

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CY7C1333H

Selection Guide

PRELIMINARY

CY7C1333H-133 CY7C1333H-100 Unit

Maximum Access Time 6.5 8.0 ns
Maximum Operating Current 225 205 mA
Maximum CMOS Standby Current 40 40 mA

Shaded area contains advance information. Please contact your local Cypress sales representative for availability of this part.

Pin Configurations

100-lead TQFP

BYTE C

BYTE D

V

V

V

V

DQ
DQ

DDQ

V
DQ
DQ
DQ
DQ

V

DDQ

DQ
DQ

V
NC

V
DQ
DQ

DDQ

V
DQ
DQ
DQ
DQ

V

DDQ

DQ
DQ

NC

SS

SS

NC

DD

SS

SS

SS

NC

1CE2

A

A

CE

100

9998979695

1
2

C

3

C

4
5
6

C

7

C

8

C

9

C

10
11
12

C

13

C

14
15
16
17
18

D

19

D

20
21
22

D

23

D

24

D

25

D

26
27
28

D

29

D

30

C

BWDBW

BWBBWACE3VDDV

94939291908988878685848382

SS

CLKWECEN

OE

CY7C1333H

ADV/LD

NC(9M)

NC(18M)

A

A

81

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

NC
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
V
NC
V

ZZ
DQ

DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
NC

DDQ
SS

SS
DDQ

SS

DD

DDQ
SS

SS
DDQ

B
B

B
B

BYTE B

B
B

B
B

A
A

A

BYTE A

A
A
A

A
A

31323334353637383940414243

A

A

A

A

A1

A0

MODE

NC/144M

NC/288M

SS

DD

V

V

44454647484950

A

A

A

NC(72M)

NC(36M)

A

A

A

NC/4M

Document #: 001-00209 Rev. ** Page 2 of 12

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PRELIMINARY

CY7C1333H

Pin Definitions (100-pin TQFP Package)

Name I/O Description

A0, A1, A Input-

Synchronous

BW

WE

[A:D]

Input-

Synchronous

Input-

Synchronous

ADV/LD

Input-

Synchronous

CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK

CE

CE

CE

OE

1

2

3

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Asynchronous

CEN

Input-

Synchronous

ZZ Input-

Asynchronous

DQ

s

I/O-

Synchronous

Mode Input

Strap Pin

V
V

V

DD
DDQ

SS

Power Supply Power supply inputs to the core of the device.

I/O Power

Supply

Ground Ground for the device.

NC – No Connects. Not Internally connected to the die.

Address Inputs used to select one of the 64K address locations. Sampled at the rising edge
of the CLK. A

are fed to the two-bit burst counter.

[1:0]

Byte Write Input s , acti ve LO W. Qualified with WE to conduct Writes to the SRAM. Sampled on
the rising edge of CLK.

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a Write sequence.

Advance/Load Input . Used to advance the on-chip address counter or load a new address. When
HIGH (and CEN
address can be loaded into the device for an access. After being deselected, ADV/LD

is asserted LOW) the internal burst counter is advanced. When LOW, a new

should be

driven LOW in order to load a new address.

is only recognized if CEN

is active LOW.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE

, and CE3 to select/deselect the device.

2

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE

and CE3 to select/deselect the device.

1

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE

and CE2 to select/deselect the device.

1

Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block
inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins.
OE

is masked during the data portion of a Write sequence, during the first clock when emerging

from a deselected state, when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the

SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN
deselect the device, CEN

can be used to extend the previous cycle when required.

does not

ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin can be connected to V
floating.

SS

or left

Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by address during the clock rise of the Read cycle. The direction of the pins is controlled
by OE

and the internal control logic. When OE is asserted LOW, the pins can behave as outputs.
When HIGH, DQ
during the data portion of a Write sequence, during the first clock when emerging from a deselected
state, and when the device is deselected, regardless of the state of OE

are placed in a three-state condition. The outputs are automatically three-stated

s

.

Mode Input. Selects the burst order of the device.

When tied to Gnd selects linear burst sequence. When tied to V
burst sequence.

or left floating selects interleaved

DD

Power supply for the I/O circuitry.

4M, 9M,18M,36M, 72M, 144M, 256M, 576M and 1G are address expansion pins and are not
internally connected to the die.

Document #: 001-00209 Rev. ** Page 3 of 12

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PRELIMINARY

CY7C1333H

Functional Overview

The CY7C1333H is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN

). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
rise (t

Accesses can be initiated by asserting all three Chip Enables
(CE
Enable (CEN
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE
conduct Byte Write operations.

Write operations are qualified by the Write Enable (WE
writes are simplified with on-chip synchronous self-timed write
circuitry.

Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.

Single Read Accesses

A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
LOW. The address presented to the address inputs is latched
into the address register and presented to the memory arra y
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be three-stated
immediately.

Burst Read Accesses

The CY7C1333H has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new addre ss into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A
wrap around when incremented sufficiently. A HIGH input on
ADV/LD
the state of chip enable inputs or WE

) is 6.5 ns (133-MHz device).

CDV

, CE2, CE3) active at the rising edge of the clock. If Clock

1

) is active LOW and ADV/LD is asserted LOW,

). BW

can be used to

[A:D]

). All

, CE2, CE3) and an

1

) simplify depth expansion.

is asserted LOW, (2) CE1, CE2,

are ALL asserted active, (3) the Write Enable input

3

is deasserted HIGH, and 4) ADV/LD is asserted

is active LOW. After the first

and A1 in the burst sequence, and will

0

will increment the internal burst counter regardless of

. WE is latched at the

beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented to the address bus

are ALL asserted active, and (3) the write signal WE

3

is asserted LOW, (2) CE1, CE2,

is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically three-stated regardless of the state of the OE
input signal. This allows the external logic to present the data
on DQs.

On the next clock rise the data presented to DQs (or a subset
for Byte Write operations, see Truth Ta ble for details) inputs is
latched into the device and the write is complete. Additional
accesses (Read/Write/Deselect) can be initiated on this cycle.

The data written during the Write operation is controlled by
BW
capability that is described in the Truth Table. Asserting the

signals. The CY7C1333H provides Byte Write

[A:D]

Write Enable input (WE) with the selected Byte Write Select
input will selectively write to only the desired bytes. Bytes not
selected during a Byte Write operation will remain unaltered.
A synchronous self-timed Write mechanism has been
provided to simplify the Write operations. Byte Write capability
has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to
simple Byte Write operations.

Because the CY7C1333H is a common I/O device, data
should not be driven into the device while the outputs are
active. The Output Enable (OE

) can be deasserted HIGH
before presenting data to the DQ inputs. Doing so will
three-state the output drivers. As a safety precaution, DQs are
automatically three-stated during the data portion of a Write
cycle, regardless of the state of OE

.

Burst Write Accesses

The CY7C1333H has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD

must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD
rise, the Chip Enables (CE
ignored and the burst counter is incremented. The correct
BW
in order to write the correct bytes of data.

inputs must be driven in each cycle of the burst write,

[A:D]

is driven HIGH on the subsequent clock

, CE2, and CE3) and WE inputs are

1

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
for the duration of t

, CE2, and CE3, must remain inactive

1

after the ZZ input returns LOW.

ZZREC

Document #: 001-00209 Rev. ** Page 4 of 12

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