CY7C1330AV25
PRELIMINARY
CY7C1332AV25
18-Mbit (512K x 36/1Mbit x 18)
Pipelined Register-Register Late Write
Features
• Fast clock speed: 250, 200 MHz
• Fast access time: 2.0, 2.25 ns
• Synchronous Pipelined Operation with Self-timed Late
Write
• Internally synchronized registered outputs eliminate
the need to control OE
• 2.5V core supply voltage
• 1.4–1.9V V
— Wide range HSTL I/O Levels
• Single Differential HSTL clock Input K and K
•Single WE (READ/WRITE) control pin
• Individual byte write (BWS
LOW)
• Common I/O
• Asynchronous Output Enable Input
• Programmable Impedance Output Drivers
• JTAG boundary scan for BGA packaging version
• Available in a 119-ball BGA package (CY7C1330AV25
and CY7C1332AV25)
supply with V
DDQ
of 0.68–0.95V
REF
) control (may be tied
[a:d]
Configuration
Functional Description
The CY7C1330AV25 and CY7C1332AV25 are high performance, Synchronous Pipelined SRAMs designed with late
write operation. These SRAMs can achieve speeds up to 250
MHz. Each memory cell consists of six transistors.
Late write feature avoids an idle cycle required during the
turnaround of the bus from a read to a write.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (K). The synchronous
inputs include all addresses (A), all data inputs (DQ
Enable (CE
control (WE
the chip enable pin (CE
select/deselect the device when desired.
Power down feature is accomplished by pulling the
Synchronous signal ZZ HIGH.
Output Enable (OE
be used to disable the outputs at any given time.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
), Byte Write Selects (BWS
). Read or Write Operations can be initiated with
). This signal allows the user to
) is an asynchronous input signal. OE can
), and read-write
[a:d]
[a:d]
), Chip
CY7C1330AV25 – 512K x 36
CY7C1332AV25 – 1M x 18
Logic Block Diagram
K,K
Clock
Buffer
A
CE
WE
BWS
ZZ
OE
x
x
CONTROL
and WRITE
LOGIC
D
Data-In REG.
CE
Q
512Kx36
1Mx18
MEMORY
ARRAY
(2stage)
OUTOUT
REGISTERS
and LOGIC
512Kx36
1Mx18
A
X
X = 18:0
X = 19:0
DQ
x
DQ
X = a, b, c, d
X = a, b
X
BWS
X
X = a, b, c, d
X = a, b
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document No: 001-07844 Rev. *A Revised September 20, 2006
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CY7C1330AV25
119-Ball BGA (14
)
PRELIMINARY
Selection Guide
CY7C1330AV25-250
CY7C1332AV25-250
Maximum Access Time
2.0 2.25 ns
Maximum Operating Current 600 550 mA
Maximum CMOS Standby Current 280 260 mA
Pin Configurations
x 22 x 2.4 mm
CY7C1330AV25 (512K x 36)
2345671
V
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
V
V
V
DDQ
NC
NC
DQ
DQ
DDQ
DQ
DQ
DDQ
DQ
DQ
DDQ
DQ
DQ
NC
NC
DDQ
c
c
c
c
d
d
d
d
AA AANC V
AA
A
DQ
DQ
DQ
DQ
DQ
V
DD
DQ
DQ
DQd
DQ
DQ
A
NC
c
c
c
c
c
d
d
d
d
A
V
SS
V
SS
V
SS
BWS
V
SS
V
REF
V
SS
BWS
V
SS
V
SS
V
SS
M
A
1
TMS
NC A A NC
V
DD
ZQ DQ
CE
OE V
NC
c
NC
V
DD
K
d
K
WE V
A0
A1 V
V
DD
A
TCK
CY7C1330AV25-200
CY7C1332AV25- 200 Unit
AANC
V
SS
V
SS
SS
BWS
V
SS
V
REF
V
SS
BWS
SS
V
SS
SS
M
A
b
a
2
b
DQ
b
DQ
b
DQ
b
DQ
b
V
DD
DQ
a
DQ
a
DQ
a
DQ
a
DQ
a
A
NC
NCTDI TDO V
CY7C1332AV25
DDQ
DQ
b
DQ
b
V
DDQ
DQ
b
DQ
b
V
DDQ
DQ
a
DQ
a
V
DDQ
DQ
a
DQ
a
NC
ZZ
DDQ
CY7C1332AV25 (1M x 18)
2345671
V
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
DDQ
NC
NC
DQ
b
NC NC
V
DDQ
NC
DQ
b
V
DDQ
NC
DQ
b
V
DDQ
DQ
b
NC
NC
NC
V
DDQ
Document No: 001-07844 Rev. *A Page 2 of 19
AA AANC V
AA
A
NC NC
DQ
b
NC
DQ
b
NC
V
DD
DQ
b
NC
DQb
NC
DQ
b
A
A
A
V
SS
V
SS
V
SS
BWS
V
SS
V
REF
V
SS
NC
V
SS
V
SS
V
SS
M
A
1
TMS
NC A A NC
V
DD
ZQ DQ
CE
OE V
NC
b
NC
V
DD
K
K
WE V
A0
A1 V
V
DD
NC A
AANC
V
SS
V
SS
SS
NC
V
SS
V
REF
V
SS
BWS
a
SS
V
SS
SS
M
2
A
TCK
a
DQ
a
NC
DQ
a
V
DD
NC
DQ
a
NC
DQ
a
NC
NCTDI TDO V
V
V
V
DDQ
DQ
DDQ
DQ
NC
DDQ
DQ
NC
DDQ
NC
DQ
NCA
ZZ
DDQ
a
a
a
a
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CY7C1330AV25
PRELIMINARY
Pin Definitions
Name I/O Type Description
A Input-
Synchronous
BWS
BWS
BWS
BWS
a
b
c
d
Input-
Synchronous
WE Input-
Synchronous
K,K
Input-
Differential Clock
CE Input-
Synchronous
OE Input-
Asynchronous
DQ
DQ
DQ
DQ
M
a
b
c
d
1, M2
Read Protocol Mode
I/O-
Synchronous
Pins
ZZ Input-
Asynchronous
ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to
V
V
V
V
DD
DDQ
REF
SS
Power Supply Power supply inputs to the core of the device. For this device, the VDD is 2.5V .
I/O Power Supply Power supply for the I/O circuitry. For this device, the V
Input-
Reference Voltage
Ground Ground for the d evice. Should be connected to ground of the system.
TDO JTAG serial output
Synchronous
TDI JTAG serial input
Synchronous
TMS Test Mode Select
Synchronous
TCK JTAG serial clock Serial clock to the JTAG circuit.
NC – No connects.
Address Inputs used to select one of the address locations. Sampled at the rising
edge of the K.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWS
BWS
controls DQc, BWSd controls DQd.
c
controls DQa, BWSb controls DQb,
a
Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to initiate a write sequence and high to initiate a read sequence.
Clock Inputs. Used to capture all synchronous inputs to the device.
Chip Enable Input, active LOW. Sampled on the rising edge of CLK. Used to
select/deselect the device.
Output Enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input
data pins. OE
is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state and when the device has been
deselected.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A
direction of the pins is controlled by OE
during the previous clock rise of the read cycle. The
[x:0]
and the internal control logic. When OE is
asserted LOW, the pins can behave as outputs. When HIGH, DQ
a tri-state condition. The outputs are automatically tri-stated during the data portion of
a write sequence, during the first clock when emerging from a deselected state, and
when the device is deselected, regardless of the state of OE
Mode control pins, used to set the proper read protocol. For specified device
operation, M
These mode pins must be set at power-up and cannot be changed during device
must be connected to VSS, and M2 must be connected to VDD or V
1
operation.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved.
the system data bus impedance. Q
RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to V
cannot be connected directly to GND or left unconnected.
, which enables the minimum impedance mode. This pin
DDQ
output impedance are set to 0.2 x RQ, where
[x:0]
Reference Volt age Input. S t atic input used to set the reference level for HSTL inputs
and Outputs as well as AC measurement points.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.
This pin controls the Test Access Port state machine. Sampled on the rising edge
of TCK.
CY7C1332AV25
–DQd are placed in
a
. DQ a,b,c,d are 9 bits wide
DDQ
is 1.5V.
DDQ
.
Document No: 001-07844 Rev. *A Page 3 of 19
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PRELIMINARY
Introduction
Functional Overview
The CY7C1330AV25 and CY7C1332AV25 are synchronouspipelined Late Write SRAMs running at speeds up to 250 MHz.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t
(250-MHz device).
Accesses can be initiated by asserting Chip Enable (CE
the rising edge of the clock. The address presented to the
device will be latched on this edge of the clock. The access
can either be a read or write operation, depending on the
status of the Write Enable (WE
conduct individual byte write operations.
). BWS
[d:a]
Write operations are qualified by the Write Enable (WE
writes are simplified with on-chip synchronous self-timed late
write circuitry.
All operations (Reads, Writes, and Deselects) are pipelined.
Pipelined Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) Chip Enable (CE) is asserted active
and (2) the Write Enable input signal (WE)
is asserted HIGH.
The address presented to the address inputs is latched in to
the Address Register and presented to the memory core and
control logic. The control logic determines that a read access
is in progress and allows the requested data to propagate to
the input of the output register. At the rising edge of the next
clock the requested data is allowed to propagate through the
output register and onto the data bus within 2.0 ns (250-MHz
device) provided OE
is active LOW. After the first clock of the
read access the output buffers are controlled by OE
internal control logic. OE
must be driven LOW in order for the
device to drive out the requested data. During the second
clock, a subsequent operation (Read/Write/Deselect) can be
initiated. Deselecting the device is also pipelined. Therefore,
when the SRAM is deselected at clock rise by one of the chip
enable signals, its output will tri-state following the next clock
rise.
Bypass Read Operation
Bypass read operation occurs when the last write operation is
followed by a read operation where write and read addresses
are identical. The data outputs are provided from the data in
registers rather than the memory array. This operation occurs
on a byte to byte basis. If only one byte is written during a write
operation and a read operation is performed on the same
address; then a partial bypass read operation is performed
since the new byte data will be from the datain registers while
the remaining bytes are from the memory array.
Late Write Accesses
The Late Write feature allows for the write data to be presented
one cycle later after the access is started. This feature eliminates one bus-turnaround cycle which is necessary when
going from a read to a write in an ordinary pipelined
Synchronous Burst SRAM.
Write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
write signal WE
is asserted LOW. The address presented to
is asserted active and (2) the
) is 2.0 ns
CO
) on
can be used to
). All
and the
CY7C1330AV25
CY7C1332AV25
A
is loaded into the Address Register. The write signals are
x
latched into the Control Logic block.
The data lines are automatically tri-stated regardless of the
state of the OE
allows the external logic to present the data on DQ
(DQ
In addition, the address for the subsequent access
for CY7C1332AV25 and DQ
[a:b]
(Read/Write/Deselect) is latched into the Address Register
(provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ
for byte write operations, see Write Cycle Description table for
details) inputs is latched into the device and the write is
complete.
The data written during the Write operation is controlled by
BWS (BWS
CY7C1332AV25) signals. The CY7C1330AV25 and
CY7C1332AV25 provide byte write capability that is described
in the Write Cycle Description table. Asserting the Write
Enable input (WE
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
Synchronous self-timed write mechanism has been provided
to simplify the write operations. Byte write capability has been
included in order to greatly simplify Read/Modify/Write
sequences, which can be reduced to simple byte write operations.
Because the CY7C1330AV25/CY7C1332AV25 is a common
I/O device, data should not be driven into the device while the
outputs are active. The Output Enable (OE
HIGH before presenting data to the DQ
tri-state the output drivers. As a safety precaution, DQ
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Power-up/Power-down Supply Voltage Sequencing
The power-up and power-down supply voltage application
recommendations are as follows:
Power-up: V
Power-down: VIN, V
V
can be applied/removed simultaneously with VDD as
DDQ
long as V
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and V
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±10% is between 175Ω and 350Ω
V
=1.5V. The output impedance is adjusted every 1024
DDQ
cycles to adjust for drifts in supply voltage and temperature.The output buffers can also be programmed in a
minimum impedance configuration by connecting ZQ to V
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
input signal when a write is detected. This
for CY7C1330AV25).
[a:d]
for CY7C1330AV25 and BWS
[a:d]
) with the selected Byte Write Select (BWS)
) can be deasserted
inputs. Doing so will
, VDD, V
SS
does not exceed VDD by more than 0.5V.
DDQ
REF
, V
DDQ
, V
SS
, VIN.
REF
, VDD, VSS.
DDQ
to allow the SRAM to adjust its
and DQP
(or a subset
for
[a:b]
, with
DD
is
.
Document No: 001-07844 Rev. *A Page 4 of 19
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PRELIMINARY
CY7C1330AV25
CY7C1332AV25
guaranteed. The device must be deselected prior to e ntering
the “sleep” mode. CE
t
after the ZZ input returns LOW.
ZZREC
Cycle Description Truth Table
must remain inactive for the duration of
[1, 2, 3, 4, 5]
Operation Address Used CE WE BWSxCLK ZZ Comments
Deselected External 1 X X L-H 0 I/Os tri-state following next recognized clock.
Begin Read External 0 1 X L-H 0 Address latched. Data driven out on the next rising edge of the clock.
Begin Write External 0 0 Valid L-H 0 Address latched, data presented to the SRAM on the next rising
edge of the clock.
Sleep Mode - X X X X 1 P ower down mode.
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
I
DDZZ
t
ZZS
t
ZZREC
Write Cycle Descriptions
Function (CY7C1330AV25) WE BW
Read 1 X X X X
Write Byte 0 – DQ
Write Byte 1 – DQ
Write Bytes 1, 0 0 1 1 0 0
Write Byte 2 – DQ
Write Bytes 2, 0 0 1 0 1 0
Write Bytes 2, 1 0 1 0 0 1
Write Bytes 2, 1, 0 0 1 0 0 0
Write Byte 3 – DQ
Write Bytes 3, 0 0 0 1 1 0
Write Bytes 3, 1 0 0 1 0 1
Write Bytes 3, 1, 0 0 0 1 0 0
Write Bytes 3, 2 0 0 0 1 1
Write Bytes 3, 2, 0 0 0 0 1 0
Write Bytes 3, 2, 1 0 0 0 0 1
Write All Bytes 0 0 0 0 0
Abort Write All Bytes 0 1 1 1 1
Write Cycle Descriptions
Snooze mode standby current ZZ > V
Device operation to ZZ ZZ > V
ZZ recovery time ZZ < V
[1, 2]
a
b
c
d
[1, 2]
01110
01101
01011
00111
IH
IH
BW
2t
CYC
c
IL
d
128 mA
2t
CYC
BW
b
BW
ns
ns
a
Function (CY7C1332AV25) WE BW
b
BW
a
Read 1 X X
Write Byte 0 – DQ
Write Byte 1 – DQ
a
b
010
001
Write All Bytes 0 0 0
Abort Write All Bytes 0 1 1
Notes:
1. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW. BWS
selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE
3. The DQ pins are controlled by the current cycle and the OE
4. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE
assumed LOW.
5. OE
and BWSx. See Write Cycle Description table for details.
= 0 signifies at least one Byte Write Select is active, BWSx = Valid signifies that the desired byte write
x
signal.
.
Document No: 001-07844 Rev. *A Page 5 of 19
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PRELIMINARY
CY7C1330AV25
CY7C1332AV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This port operates in accordance with IEEE Standard 1149.1-1900 but does not have the
set of functions required for full 1149.1 compliance. The TAP
operates using JEDEC standard 1.8V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V
) to prevent clocking of the device. TDI and TMS are inter-
SS
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the T AP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V
) when the BYPASS instruction is executed.
SS
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
Document No: 001-07844 Rev. *A Page 6 of 19
[+] Feedback
PRELIMINARY
CY7C1330AV25
CY7C1332AV25
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR sta te. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the T AP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (t
captured correctly if there is no way in a design to stop (o r
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
and tCH). The SRAM clock input might not be
CS
Document No: 001-07844 Rev. *A Page 7 of 19
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PRELIMINARY
CY7C1330AV25
CY7C1332AV25
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
1
IDLE
[6]
1
0
1
SELECT
DR-SCAN
1
CAPTURE-DR
SHIFT-DR
EXIT1-DR
1
SELECT
IR-SCAN
0
0
1
CAPTURE-IR
0
0
SHIFT-IR
1
0
1
1
EXIT1-IR
0
0
PAUSE-DR
1
0
EXIT2-DR
1
UPDATE-DR
1
Note:
6. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
0
PAUSE-IR
0
1
0
EXIT2-IR
1
UPDATE-IR
0
1
0
Document No: 001-07844 Rev. *A Page 8 of 19
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TAP Controller Block Diagram
TDI
Selection
Circuitry
PRELIMINARY
Bypass Register
Instruction Register
CY7C1330AV25
CY7C1332AV25
0
012
Selection
Circuitry
TDO
29
3031
012..
Identification Register
.
.106
012..
Boundary Scan Register
TCK
TMS
TAP Electrical Characteristics Over the Operating Range
Parameter Description T est Conditions Min. Max. Unit
V
V
V
V
V
V
I
OH1
OH2
OL1
OL2
IH
IL
X
Output HIGH Voltage I
Output HIGH Voltage I
Output LOW Voltage IOL = 2.0 mA 0.7 V
Output LOW Voltage IOL = 100 µA0.2V
Input HIGH Voltage 1.7 V
Input LOW Voltage –0.3 0.7 V
Input and Output Load Current GND ≤ VI ≤ V
TAP AC Switching Characteristics Over the Operating Range
Parameter Description Min. Max. Unit
t
TCYC
t
TF
t
TH
t
TL
Set-up Times
t
TMSS
t
TDIS
t
CS
Hold Times
t
TMSH
t
TDIH
Notes:
7. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
8. Input waveform should have a slew rate of >
9. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
10.t
and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
11.Test conditions are specified using the load in TAP AC test conditions. t
TCK Clock Cycle Time 50 ns
TCK Clock Frequency 20 MHz
TCK Clock HIGH 20 ns
TCK Clock LOW 20 ns
TMS Set-up to TCK Clock Rise 5 ns
TDI Set-up to TCK Clock Rise 5 ns
Capture Set-up to TCK Rise 5 ns
TMS Hold after TCK Clock Rise 5 ns
TDI Hold after Clock Rise 5 ns
1 V/ns.
TAP Controller
[7, 8, 9]
= −2.0 mA 1.7 V
OH
= −100 µA2.1 V
OH
+ 0.3 V
DD
–5 5 µA
R/tF
DD
[10, 1 1]
= 1 ns.
Document No: 001-07844 Rev. *A Page 9 of 19
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PRELIMINARY
CY7C1330AV25
CY7C1332AV25
TAP AC Switching Characteristics Over the Operating Range (continued)
[10, 11]
Parameter Description Min. Max. Unit
t
CH
Capture Hold after Clock Rise 5 ns
Output Times
t
TDOV
t
TDOX
TAP Timing and Test Conditions
TDO
TCK Clock LOW to TDO Valid 10 ns
TCK Clock LOW to TDO Invalid 0 ns
[11]
ALL INPUT PULSES
2.5V
1.25V
Z
= 50Ω
0
(a)
1.25V
GND
50Ω
C
L
= 20 pF
0V
TH
t
TL
t
Test Clock
TCK
t
TMSS
t
TMSH
t
TCYC
Test Mode Select
TMS
t
TDIS
t
TDIH
Test Data-In
TDI
Test Data-Out
TDO
t
TDOV
t
TDOX
Identification Register Definitions
Value
Instruction Field
Revision Number (31:29) 000 000 Version number.
Cypress Device ID (28:12) 01011110101100101 01011110101010101 Defines the type of SRAM.
Cypress JEDEC ID (11:1) 000 00110100 00000110100 Allows unique identification of SRAM vendor.
ID Register Presence (0) 1 1 Indicates the presence of an ID register.
DescriptionCY7C1330AV25 CY7C1332AV25
Document No: 001-07844 Rev. *A Page 10 of 19
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CY7C1330AV25
PRELIMINARY
Scan Register Sizes
Register Name Bit Size—CY7C1330AV25 Bit Size—CY7C1332AV25
Instruction 3 3
Bypass 1 1
ID 32 32
Boundary Scan 70 51
Instruction Codes
Instruction Code Description
EXTEST 000 Captures the Input/Output ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect
SRAM operation.
Boundary Scan Order (1 Mbit x 18)
Bit # Bump ID Bit # Bump ID Bi t # Bump ID
15R 187E 351H
26T 196D 363G
34P 206A 374D
46R 216C 384E
55T 225C 394G
67T 235A 404H
77P 246B 414M
86N 255B 422K
96L 263B 431L
10 7K 27 2B 44 2M
11 5L 28 3A 45 1N
12 4L 29 3C 46 2P
13 4K 30 2C 47 3T
14 4F 31 2A 48 2R
15 6H 32 1D 49 4N
16 7G 33 2E 50 2T
17 6F 34 2G 51 3R
CY7C1332AV25
Document No: 001-07844 Rev. *A Page 11 of 19
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CY7C1330AV25
PRELIMINARY
Boundary Scan Order (512K x 36)
Bit # Bump ID Bit # Bump ID Bit # Bump ID
15R 256F 492H
24P 267E 501H
34T 276E 513G
46R 287D 524D
55T 296D 534E
67T 306A 544G
76P 316C 554H
87P 325C 564M
96N 335A 57 3L
10 7N 34 6B 58 1K
11 6M 35 5B 59 2K
12 6L 36 3B 60 1L
13 7L 37 2B 61 2L
14 6K 38 3A 62 2M
15 7K 39 3C 63 1N
16 5L 40 2C 64 2N
17 4L 41 2A 65 1P
18 4K 42 2D 66 2P
19 4F 43 1D 67 3T
20 5G 44 2E 68 2R
21 7H 45 1E 69 4N
22 6H 46 2F 70 3R
23 7G 47 2G
24 6G 48 1G
CY7C1332AV25
Document No: 001-07844 Rev. *A Page 12 of 19
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CY7C1330AV25
PRELIMINARY
[7]
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied........................................... –55°C to +125°°C
Supply Voltage on V
Supply Voltage on V
DC Voltage Applied to Outputs
in High-Z State
[7]
Relative to GND........–0.5V to +2.9V
DD
Relative to GND......–0.5V to +V
DDQ
.................................–0.5V to V
DDQ
DD
+ 0.5V
DC Input Voltage
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage...........................................> 1500V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Range
Com’l 0°C to +70°C 2.37V to 2.63V 1.4V to 1.9V
Electrical Characteristics Over the Operating Range
DC Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
V
DD
V
DDQ
V
OH1
V
OL1
V
OH2
V
OL2
V
OH3
V
OL3
V
IH
V
IL
I
X
I
OZ
V
REF
V
–CLK Clock Input Reference
IN
–CLK Clock Input Differential
V
DIF
–CLK Clock Common Mode
V
CM
I
DD
I
SB1
Power Supply Voltage 2.37 2.63 V
I/O Supply Voltage 1.4 1.9 V
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage IOH = –0.1 mA, Minimum Impedance Mode
Output LOW Voltage IOL = 0.1 mA, Minimum Impedance Mode
Output HIGH Voltage IOH = –6.0 mA, Minimum Impedance Mode
Output LOW Voltage IOL = 6.0 mA, Minimum Impedance Mode
Input HIGH Voltage V
Input LOW Voltage
Input Leakage Current GND ≤ VI ≤ V
Output Leakage Current GND ≤ VI ≤ V
Input Reference Voltage Typical value = 0.75V 0.68 0.95 V
Voltage
Voltage
Voltage
VDD Operating Supply V
Automatic CE
Power-Down
Current—TTL Inputs
Over the Operating Range
[12]
Programmable Impedance Mode
[13]
Programmable Impedance Mode
[7]
Typical Value =0.75V 0.55 0.95 V
= Max., I
DD
f = f
MAX
= 1/t
Max. VDD, Device Deselected,
V
> VIH or VIN < V
IN
f = f
MAX
= 1/t
[14]
[14]
DDQ
Output Disabled –1 1 mA
DDQ,
= 0 mA,
OUT
CYC
IL
CYC
................................–0.5V to VDD + 0.5V
Ambient
Temperature V
[15]
V
[15]
[15]
V
[15]
250 MHz 600 mA
200 MHz 550 mA
250 MHz 280 mA
200 MHz 260 mA
CY7C1332AV25
DD
V
/2 V
DDQ
V
SS
– 0.2 V
DDQ
V
SS
– 0.4 V
DDQ
V
SS
+ 0.1 V
REF
–0.3 V
V
DDQ
REF
–1 1 mA
–0.3 V
0.1 V
DDQ
DDQ
V
DD
/2 V
DDQ
DDQ
0.2 V
DDQ
0.4 V
+ 0.3 V
– 0.1 V
+ 0.3 V
+ 0.3 V
DDQ
V
V
V
AC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions Min. Max. Unit
V
IH
V
IL
Notes:
= (V
12.I
OH
= (V
13.I
OL
14.Programmable Impedance Output Buffer Mode. The ZQ pin is connected to V
15.Minimum Impedance Output Buffer Mode: The ZQ pin is connected directly to V
16.T
Power-up
Input HIGH Voltage V
REF
Input LOW Voltage – V
/2)/(RQ/5)+15% for 175Ω < RQ < 350Ω.
DDQ
/2)/(RQ/5)+15% for 175Ω < RQ < 350Ω.
DDQ
: Assumes a linear ramp from 0V to V
(min.) within 200 ms. During this time VIH < VDD and V
DD
through RQ.
SS
or VDD.
SS
DDQ
< VDD.
+ 0.2 – V
– 0.2 V
REF
Document No: 001-07844 Rev. *A Page 13 of 19
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PRELIMINARY
CY7C1330AV25
CY7C1332AV25
Capacitance
[17]
Parameter Description T est Conditions Max. Unit
C
Input Capacitance TA = 25°C, f = 1 MHz,
IN
C
CLK
C
I/O
Thermal Resistance
Clock Input Capacitance 6 pF
Input/Output Capacitance 7 pF
[17]
V
V
= 2.5V
DD
DDQ
= 1.5V
5pF
Parameter Description Test Conditions BGA Typ. Unit
Θ
JA
Θ
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Still Air , soldered on a 4.25 x 1.125 inch, 4-layer printed
circuit board
19.7 °C/W
6.0 °C/W
AC Test Loads and Waveforms
V
= 0.75V
REF
(a)
0.75V
Z
0
RQ =
250
= 50Ω
Ω
V
REF
= 50Ω
R
L
= 0.75V
V
REF
OUTPUT
Device
Under
Test
ZQ
0.75V
RQ =
250
(b)
R = 50Ω
5pF
Ω
0.25V
ALL INPUT PULSES
1.25V
0.75V
Slew Rate = 2 V/ns
[18]
V
REF
OUTPUT
Device
Under
Test
ZQ
Notes:
17.Tested initially and after any design or process change that may affect these parameters.
18.Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75V, V
pulse levels of 0.25V to 1.25V, and output loading of the specified I
and load capacitance shown in (a) of AC Test Loads.
OL/IOH
= 0.75V, RQ = 250Ω, V
REF
= 1.5V, input
DDQ
Document No: 001-07844 Rev. *A Page 14 of 19
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PRELIMINARY
CY7C1330AV25
CY7C1332AV25
Switching Characteristics
[18, 19, 20, 21]
Parameter Description
t
Power
VCC (typical) to the First Access Read or Write
Clock
t
CYC
F
t
CH
t
CL
MAX
Clock Cycle Time 4.0 5.0 ns
Maximum Operating Frequency 250 200 MHz
Clock HIGH 1.5 1.5 ns
Clock LOW 1.5 1.5 ns
Output Times
t
CO
t
EOV
t
DOH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
Data Output Valid After CLK Rise 2.0 2.25 ns
OE LOW to Output Valid
Data Output Hold After CLK Rise 0.5 0.5 ns
Clock to High-Z
Clock to Low-Z
[17, 18, 19, 20, 21]
[17, 18, 19, 20, 21]
OE HIGH to Output High-Z
OE LOW to Output Low-Z
Set-Up Times
t
AS
t
DS
t
WES
t
CES
Address Set-Up Before CLK Rise 0.3 0.3 ns
Data Input Set-Up Before CLK Rise 0.3 0.3 ns
WE, BWSx Set-Up Before CLK Rise 0.3 0.3 ns
Chip Select Set-Up 0.3 0.3 ns
Hold Times
t
AH
t
DH
t
WEH
t
CEH
Address Hold After CLK Rise 0.6 0.6 ns
Data Input Hold After CLK Rise 0.6 0.6 ns
WE, BWx Hold After CLK Rise 0.6 0.6 ns
Chip Select Hold After CLK Rise 0.6 0.6 ns
[17, 19, 21]
[18, 19, 21]
[18, 19, 21]
[22]
250 200
UnitMin. Max. Min. Max.
11ms
2.0 2.25 ns
2.0 2.25 ns
0.5 0.5 ns
2.0 2.25 ns
0.5 0.5 ns
Notes:
19.t
, t
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
CHZ
CLZ
20.At any given voltage and temperature, t
data bus. These specifications do not imply a bus contenti on con dition, but r efl ec t parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
21.This parameter is sampled and not 100% tested.
22.This part has a voltage regulator that steps down t he volt age internally; t
or write operation can be initiated.
is less than t
EOHZ
EOLZ
and t
is less than t
CHZ
is the time power needs to be supplied above VDD minimum initially before a read
Power
to eliminate bus contention between SRAMs when sharing the same
CLZ
Document No: 001-07844 Rev. *A Page 15 of 19
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PRELIMINARY
Switching Waveforms
READ/WRITE/DESELECT Sequence (OE Controlled)
CY7C1330AV25
CY7C1332AV25
[23, 24, 25, 26]
K
ADDRESS
WE
BWS
x
OE/
Data
In/Out
READ
t
t
AH
AS
RA1
t
t
WES
WEH
Device
originally
deselected
t
CLZ
DESELECT
t
CO
t
WES
t
DOH
WA2
Q1
Out
WRITE
t
CH
t
WEH
t
EOHZ
t
CHZ
READ
t
CL
RA3
t
t
DS
DH
D2
In
READ
t
EOLZ
t
EOV
t
CYC
WA5
Q3
Out
WRITE
t
DOH
RA6
D5
In
READ
DESELECT
WA7
Q6
Out
WRITE
t
EOHZ
WA8
t
DS
WRITE
D7
In
DESELECT
D8
In
t
DH
= DON’T CARE
Notes:
23.The combination of WE
24.All chip enables need to be active in order to select the device. Any chip enable can deselect the device.
25.RAx stands for Read Address X, WAx Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X.
held LOW.
26.CE
and BWSx (x = a, b, c, d for x36 and x = a, b for x18) define a write cycle (see Write Cycle Description table).
= UNDEFINED
Document No: 001-07844 Rev. *A Page 16 of 19
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Switching Waveforms (continued)
PRELIMINARY
CY7C1330AV25
CY7C1332AV25
READ/WRITE/DESELECT Sequence (CE
READ
DESELECT
WRITE
CLK
t
t
CES
t
CEH
CH
CE
t
t
AH
AS
ADDRESS
RA1
WA2
WE
t
t
WES
WEH
Controlled)
READ
t
CL
RA3
Deselect
t
CYC
WA5
WRITE
RA6
READ
DESELECT
WA7
WRITE
WRITE
DESELECT
WA8
BWS
Data
In/Out
x
t
CLZ
Device
originally
deselected
t
t
WES
WEH
t
t
DS
t
DOH
Q1
Out
t
t
CO
CHZ
DH
D2
In
= DON’T CARE
t
DOH
Q3
Out
= UNDEFINED
D5
In
Q6
Out
D7
In
D8
In
Document No: 001-07844 Rev. *A Page 17 of 19
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Ordering Information
CY7C1330AV25
CY7C1332AV25
PRELIMINARY
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz) Ordering Code
250 CY7C1330AV25-250BGC
Package
Diagram Package Type
Operating
Range
51-85115 119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 mm) Commercial
CY7C1332AV25-250BGC
CY7C1330AV25-250BGXC
51-85115 119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1332AV25-250BGXC
200 CY7C1330AV25-200BGC
51-85115 119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1332AV25-200BGC
CY7C1330AV25-200BGXC
51-85115 119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1332AV25-200BGXC
Package Diagram
119-ball PBGA (14 x 22 x 2.4 mm) (51-85115)
51-85115-*B
All product and company names mentioned in this document are trademarks of their respective holders.
Document No: 001-07844 Rev. *A Page 18 of 19
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change wi t hou t notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not auth orize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypre ss
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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PRELIMINARY
Document History Page
Document Title: CY7C1330AV25/CY7C1332AV25 18-Mbit (512K x 36/1Mbit x 18)
Pipelined Register-Register Late Write SRAM
Document Number: 001-07844
REV. ECN No. Issue Date
** 469811 See ECN NXR New data sheet
*A 503690 See ECN VKN Minor change: Moved data sheet to web
Orig. of
Change Description of Change
CY7C1330AV25
CY7C1332AV25
Document No: 001-07844 Rev. *A Page 19 of 19
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