Cypress CY7C1330AV25, CY7C1332AV25 User Manual

CY7C1330AV25

PRELIMINARY

CY7C1332AV25

18-Mbit (512K x 36/1Mbit x 18)

Pipelined Register-Register Late Write

Features

• Fast clock speed: 250, 200 MHz

• Fast access time: 2.0, 2.25 ns

• Synchronous Pipelined Operation with Self-timed Late
Write

• Internally synchronized registered outputs eliminate
the need to control OE

• 2.5V core supply voltage

• 1.4–1.9V V
— Wide range HSTL I/O Levels

• Single Differential HSTL clock Input K and K

•Single WE (READ/WRITE) control pin

• Individual byte write (BWS
LOW)

• Common I/O

• Asynchronous Output Enable Input

• Programmable Impedance Output Drivers

• JTAG boundary scan for BGA packaging version

• Available in a 119-ball BGA package (CY7C1330AV25
and CY7C1332AV25)

supply with V

DDQ

of 0.68–0.95V

REF

) control (may be tied

[a:d]

Configuration

Functional Description

The CY7C1330AV25 and CY7C1332AV25 are high perfor­mance, Synchronous Pipelined SRAMs designed with late
write operation. These SRAMs can achieve speeds up to 250
MHz. Each memory cell consists of six transistors.

Late write feature avoids an idle cycle required during the
turnaround of the bus from a read to a write.

All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (K). The synchronous
inputs include all addresses (A), all data inputs (DQ
Enable (CE
control (WE
the chip enable pin (CE
select/deselect the device when desired.

Power down feature is accomplished by pulling the
Synchronous signal ZZ HIGH.

Output Enable (OE
be used to disable the outputs at any given time.

Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.

), Byte Write Selects (BWS
). Read or Write Operations can be initiated with

). This signal allows the user to

) is an asynchronous input signal. OE can

), and read-write

[a:d]

[a:d]

), Chip

CY7C1330AV25 – 512K x 36
CY7C1332AV25 – 1M x 18

Logic Block Diagram

K,K

Clock
Buffer

A

CE

WE

BWS

ZZ

OE

x

x

CONTROL

and WRITE

LOGIC

D

Data-In REG.

CE

Q

512Kx36
1Mx18

MEMORY

ARRAY

(2stage)

OUTOUT

REGISTERS

and LOGIC

512Kx36

1Mx18

A

X

X = 18:0

X = 19:0

DQ

x

DQ

X = a, b, c, d

X = a, b

X

BWS

X

X = a, b, c, d

X = a, b

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document No: 001-07844 Rev. *A Revised September 20, 2006

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CY7C1330AV25

119-Ball BGA (14

)

PRELIMINARY

Selection Guide

CY7C1330AV25-250
CY7C1332AV25-250

Maximum Access Time

2.0 2.25 ns
Maximum Operating Current 600 550 mA
Maximum CMOS Standby Current 280 260 mA

Pin Configurations

x 22 x 2.4 mm

CY7C1330AV25 (512K x 36)

2345671

V

A
B

C
D

E
F
G
H

J
K
L

M

N
P

R
T
U

V

V

V

V

DDQ

NC
NC

DQ
DQ

DDQ

DQ
DQ

DDQ

DQ
DQ

DDQ

DQ
DQ

NC
NC

DDQ

c
c

c
c

d
d

d
d

AA AANC V
AA

A

DQ
DQ
DQ
DQ
DQ

V

DD

DQ

DQ

DQd
DQ
DQ

A

NC

c
c
c
c
c

d

d

d
d

A

V

SS

V

SS

V

SS

BWS

V

SS

V

REF

V

SS

BWS

V

SS

V

SS

V

SS

M

A

1

TMS

NC A A NC

V

DD

ZQ DQ
CE
OE V
NC

c

NC

V

DD

K

d

K
WE V
A0
A1 V

V

DD

A

TCK

CY7C1330AV25-200
CY7C1332AV25- 200 Unit

AANC

V

SS

V

SS
SS

BWS

V

SS

V

REF

V

SS

BWS

SS

V

SS
SS

M

A

b

a

2

b

DQ

b

DQ

b

DQ

b

DQ

b

V

DD

DQ

a

DQ

a

DQ

a

DQ

a

DQ

a

A

NC
NCTDI TDO V

CY7C1332AV25

DDQ

DQ

b

DQ

b

V

DDQ

DQ

b

DQ

b

V

DDQ

DQ

a

DQ

a

V

DDQ

DQ

a

DQ

a

NC

ZZ

DDQ

CY7C1332AV25 (1M x 18)

2345671

V

A
B

C
D

E
F

G

H

J
K
L

M

N
P

R
T
U

DDQ

NC
NC

DQ

b

NC NC

V

DDQ

NC

DQ

b

V

DDQ

NC

DQ

b

V

DDQ

DQ

b

NC
NC

NC

V

DDQ

Document No: 001-07844 Rev. *A Page 2 of 19

AA AANC V
AA

A

NC NC

DQ

b

NC

DQ

b

NC

V

DD

DQ

b

NC
DQb
NC

DQ

b

A
A

A

V

SS

V

SS

V

SS

BWS

V

SS

V

REF

V

SS

NC

V

SS

V

SS

V

SS

M

A

1

TMS

NC A A NC

V

DD

ZQ DQ
CE
OE V
NC

b

NC

V

DD

K

K
WE V
A0
A1 V

V

DD

NC A

AANC

V

SS

V

SS
SS

NC

V

SS

V

REF

V

SS

BWS

a

SS

V

SS
SS

M

2

A

TCK

a

DQ

a

NC

DQ

a

V

DD

NC

DQ

a

NC

DQ

a

NC

NCTDI TDO V

V

V

V

DDQ

DQ

DDQ

DQ

NC

DDQ

DQ

NC

DDQ

NC

DQ

NCA

ZZ

DDQ

a

a

a

a

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CY7C1330AV25

PRELIMINARY

Pin Definitions

Name I/O Type Description

A Input-

Synchronous

BWS
BWS
BWS
BWS

a
b
c
d

Input-

Synchronous

WE Input-

Synchronous

K,K

Input-

Differential Clock

CE Input-

Synchronous

OE Input-

Asynchronous

DQ
DQ
DQ
DQ

M

a
b
c
d

1, M2

Read Protocol Mode

I/O-

Synchronous

Pins

ZZ Input-

Asynchronous

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to

V
V
V

V

DD
DDQ
REF

SS

Power Supply Power supply inputs to the core of the device. For this device, the VDD is 2.5V .

I/O Power Supply Power supply for the I/O circuitry. For this device, the V

Input-

Reference Voltage

Ground Ground for the d evice. Should be connected to ground of the system.

TDO JTAG serial output

Synchronous

TDI JTAG serial input

Synchronous

TMS Test Mode Select

Synchronous
TCK JTAG serial clock Serial clock to the JTAG circuit.
NC – No connects.

Address Inputs used to select one of the address locations. Sampled at the rising
edge of the K.

Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWS
BWS

controls DQc, BWSd controls DQd.

c

controls DQa, BWSb controls DQb,

a

Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to initiate a write sequence and high to initiate a read sequence.

Clock Inputs. Used to capture all synchronous inputs to the device.

Chip Enable Input, active LOW. Sampled on the rising edge of CLK. Used to

select/deselect the device.
Output Enable, active LOW. Combined with the synchronous logic block inside the

device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input
data pins. OE

is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state and when the device has been
deselected.

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A
direction of the pins is controlled by OE

during the previous clock rise of the read cycle. The

[x:0]

and the internal control logic. When OE is
asserted LOW, the pins can behave as outputs. When HIGH, DQ
a tri-state condition. The outputs are automatically tri-stated during the data portion of
a write sequence, during the first clock when emerging from a deselected state, and
when the device is deselected, regardless of the state of OE

Mode control pins, used to set the proper read protocol. For specified device
operation, M
These mode pins must be set at power-up and cannot be changed during device

must be connected to VSS, and M2 must be connected to VDD or V

1

operation.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”

condition with data integrity preserved.

the system data bus impedance. Q
RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to V
cannot be connected directly to GND or left unconnected.

, which enables the minimum impedance mode. This pin

DDQ

output impedance are set to 0.2 x RQ, where

[x:0]

Reference Volt age Input. S t atic input used to set the reference level for HSTL inputs
and Outputs as well as AC measurement points.

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.

This pin controls the Test Access Port state machine. Sampled on the rising edge

of TCK.

CY7C1332AV25

–DQd are placed in

a

. DQ a,b,c,d are 9 bits wide

DDQ

is 1.5V.

DDQ

.

Document No: 001-07844 Rev. *A Page 3 of 19

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PRELIMINARY

Introduction

Functional Overview

The CY7C1330AV25 and CY7C1332AV25 are synchronous­pipelined Late Write SRAMs running at speeds up to 250 MHz.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t
(250-MHz device).

Accesses can be initiated by asserting Chip Enable (CE
the rising edge of the clock. The address presented to the
device will be latched on this edge of the clock. The access
can either be a read or write operation, depending on the
status of the Write Enable (WE
conduct individual byte write operations.

). BWS

[d:a]

Write operations are qualified by the Write Enable (WE
writes are simplified with on-chip synchronous self-timed late
write circuitry.

All operations (Reads, Writes, and Deselects) are pipelined.

Pipelined Read Accesses

A read access is initiated when the following conditions are
satisfied at clock rise: (1) Chip Enable (CE) is asserted active
and (2) the Write Enable input signal (WE)

is asserted HIGH.
The address presented to the address inputs is latched in to
the Address Register and presented to the memory core and
control logic. The control logic determines that a read access
is in progress and allows the requested data to propagate to
the input of the output register. At the rising edge of the next
clock the requested data is allowed to propagate through the
output register and onto the data bus within 2.0 ns (250-MHz
device) provided OE

is active LOW. After the first clock of the
read access the output buffers are controlled by OE
internal control logic. OE

must be driven LOW in order for the
device to drive out the requested data. During the second
clock, a subsequent operation (Read/Write/Deselect) can be
initiated. Deselecting the device is also pipelined. Therefore,
when the SRAM is deselected at clock rise by one of the chip
enable signals, its output will tri-state following the next clock
rise.

Bypass Read Operation

Bypass read operation occurs when the last write operation is
followed by a read operation where write and read addresses
are identical. The data outputs are provided from the data in
registers rather than the memory array. This operation occurs
on a byte to byte basis. If only one byte is written during a write
operation and a read operation is performed on the same
address; then a partial bypass read operation is performed
since the new byte data will be from the datain registers while
the remaining bytes are from the memory array.

Late Write Accesses

The Late Write feature allows for the write data to be presented
one cycle later after the access is started. This feature elimi­nates one bus-turnaround cycle which is necessary when
going from a read to a write in an ordinary pipelined
Synchronous Burst SRAM.

Write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
write signal WE

is asserted LOW. The address presented to

is asserted active and (2) the

) is 2.0 ns

CO

) on

can be used to

). All

and the

CY7C1330AV25
CY7C1332AV25

A

is loaded into the Address Register. The write signals are

x

latched into the Control Logic block.
The data lines are automatically tri-stated regardless of the

state of the OE
allows the external logic to present the data on DQ
(DQ
In addition, the address for the subsequent access

for CY7C1332AV25 and DQ

[a:b]

(Read/Write/Deselect) is latched into the Address Register
(provided the appropriate control signals are asserted).

On the next clock rise the data presented to DQ
for byte write operations, see Write Cycle Description table for
details) inputs is latched into the device and the write is
complete.

The data written during the Write operation is controlled by
BWS (BWS
CY7C1332AV25) signals. The CY7C1330AV25 and
CY7C1332AV25 provide byte write capability that is described
in the Write Cycle Description table. Asserting the Write
Enable input (WE
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
Synchronous self-timed write mechanism has been provided
to simplify the write operations. Byte write capability has been
included in order to greatly simplify Read/Modify/Write
sequences, which can be reduced to simple byte write opera­tions.

Because the CY7C1330AV25/CY7C1332AV25 is a common
I/O device, data should not be driven into the device while the
outputs are active. The Output Enable (OE
HIGH before presenting data to the DQ
tri-state the output drivers. As a safety precaution, DQ
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.

Power-up/Power-down Supply Voltage Sequencing

The power-up and power-down supply voltage application
recommendations are as follows:

Power-up: V
Power-down: VIN, V
V

can be applied/removed simultaneously with VDD as

DDQ

long as V

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and V
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±10% is between 175Ω and 350Ω
V

=1.5V. The output impedance is adjusted every 1024

DDQ

cycles to adjust for drifts in supply voltage and temper­ature.The output buffers can also be programmed in a
minimum impedance configuration by connecting ZQ to V

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation

input signal when a write is detected. This

for CY7C1330AV25).

[a:d]

for CY7C1330AV25 and BWS

[a:d]

) with the selected Byte Write Select (BWS)

) can be deasserted

inputs. Doing so will

, VDD, V

SS

does not exceed VDD by more than 0.5V.

DDQ

REF

, V

DDQ

, V

SS

, VIN.

REF

, VDD, VSS.

DDQ

to allow the SRAM to adjust its

and DQP

(or a subset

for

[a:b]

, with

DD

is

.

Document No: 001-07844 Rev. *A Page 4 of 19

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PRELIMINARY

CY7C1330AV25
CY7C1332AV25

guaranteed. The device must be deselected prior to e ntering
the “sleep” mode. CE
t

after the ZZ input returns LOW.

ZZREC

Cycle Description Truth Table

must remain inactive for the duration of

[1, 2, 3, 4, 5]

Operation Address Used CE WE BWSxCLK ZZ Comments

Deselected External 1 X X L-H 0 I/Os tri-state following next recognized clock.
Begin Read External 0 1 X L-H 0 Address latched. Data driven out on the next rising edge of the clock.
Begin Write External 0 0 Valid L-H 0 Address latched, data presented to the SRAM on the next rising

edge of the clock.

Sleep Mode - X X X X 1 P ower down mode.

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

I

DDZZ

t

ZZS

t

ZZREC

Write Cycle Descriptions

Function (CY7C1330AV25) WE BW

Read 1 X X X X
Write Byte 0 – DQ
Write Byte 1 – DQ
Write Bytes 1, 0 0 1 1 0 0
Write Byte 2 – DQ
Write Bytes 2, 0 0 1 0 1 0
Write Bytes 2, 1 0 1 0 0 1
Write Bytes 2, 1, 0 0 1 0 0 0
Write Byte 3 – DQ
Write Bytes 3, 0 0 0 1 1 0
Write Bytes 3, 1 0 0 1 0 1
Write Bytes 3, 1, 0 0 0 1 0 0
Write Bytes 3, 2 0 0 0 1 1
Write Bytes 3, 2, 0 0 0 0 1 0
Write Bytes 3, 2, 1 0 0 0 0 1
Write All Bytes 0 0 0 0 0
Abort Write All Bytes 0 1 1 1 1

Write Cycle Descriptions

Snooze mode standby current ZZ > V
Device operation to ZZ ZZ > V
ZZ recovery time ZZ < V

[1, 2]

a
b

c

d

[1, 2]

01110
01101

01011

00111

IH
IH

BW

2t

CYC

c

IL

d

128 mA

2t

CYC

BW

b

BW

ns
ns

a

Function (CY7C1332AV25) WE BW

b

BW

a

Read 1 X X
Write Byte 0 – DQ
Write Byte 1 – DQ

a
b

010

001
Write All Bytes 0 0 0
Abort Write All Bytes 0 1 1

Notes:

1. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW. BWS
selects are asserted, see Write Cycle Description table for details.

2. Write is defined by WE

3. The DQ pins are controlled by the current cycle and the OE

4. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE

assumed LOW.

5. OE

and BWSx. See Write Cycle Description table for details.

= 0 signifies at least one Byte Write Select is active, BWSx = Valid signifies that the desired byte write

x

signal.

.

Document No: 001-07844 Rev. *A Page 5 of 19

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PRELIMINARY

CY7C1330AV25
CY7C1332AV25

IEEE 1149.1 Serial Boundary Scan (JTAG)

These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This port operates in accor­dance with IEEE Standard 1149.1-1900 but does not have the
set of functions required for full 1149.1 compliance. The TAP
operates using JEDEC standard 1.8V I/O logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V

) to prevent clocking of the device. TDI and TMS are inter-

SS

nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.

Test Access Port—Test Clock

The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.

Test Mode Select

The TMS input is used to give commands to the T AP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.

Test Data-Out (TDO)

The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.

TAP Registers

Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.

When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V

) when the BYPASS instruction is executed.

SS

Boundary Scan Register

The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.

The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc­tions can be used to capture the contents of the Input and
Output ring.

The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.

TAP Instruction Set

Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc­tions are described in detail below.

Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.

Document No: 001-07844 Rev. *A Page 6 of 19

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