A
A
B
CY7C1327F
4-Mb (256K x 18) Pipelined Sync SRAM
Features
• Registered inputs and outputs for pipelined operation
• 256K ×18 common I/O architecture
• 3.3V core power supply
• 3.3V / 2.5V I/O operation
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.6 ns (for 225-MHz device)
— 2.8 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
— 4.5 ns (for 100-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP and 119 Ball
BGA packages.
• “ZZ” Sleep Mode Option
Logic Block Diagram
Functional Description
[1]
The CY7C1327F SRAM integrates 262,144 x 18 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(
), depth-expansion Chip Enables (CE2 and
CE
1
Control inputs (
(
BW
inputs include the Output Enable (
[A:B]
, and
BWE
,
ADSC
), and Global Write (GW). Asynchronous
ADSP
,
and
OE
), Write Enables
ADV
) and the ZZ pin.
CE
), Burst
3
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (
Address Strobe Controller (
) are active. Subsequent
ADSC
ADSP
) or
burst addresses can be internally generated as controlled by
the Advance pin (
ADV
).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two bytes wide as
controlled by the byte write control inputs.
causes all bytes to be written.
LOW
when active
GW
The CY7C1327F operates from a +3.3V core power supply
while all outputs also operate with a +3.3V or a +2.5V supply.
All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW
B
BW
A
BWE
GW
CE
1
CE2
CE3
OE
ZZ
1
Note:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com
ADDRESS
REGISTER
DQB,DQP
B
WRITE REGISTER
DQA,DQP
A
WRITE REGISTER
ENABLE
REGISTER
SLEEP
CONTROL
2
Q1
BURST
COUNTER AND
LOGIC
CLR
Q0
PIPELINED
ENABLE
A[1:0]
DQB,DQP
B
WRITE DRIVER
DQA,DQP
A
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
INPUT
REGISTERS
DQs
DQP
DQP
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05216 Rev. *B Revised December 12, 2003
CY7C1327F
Selection Guide
250 MHz 225 MHz 200 MHz 166 MHz 133 MHz 100 MHz Unit
Maximum Access Time 2.6 2.6 2.8 3.5 4.0 4.5 ns
Maximum Operating Current 325 290 265 240 225 205 mA
Maximum CMOS Standby
Current
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Pin Configurations
40 40 40 40 40 40 mA
BYTE B
V
DDQ
V
DQ
DQ
V
V
DDQ
DQ
DQ
V
V
DQ
DQ
V
DDQ
V
DQ
DQ
DQP
V
V
DDQ
NC
NC
NC
SS
NC
NC
SS
NC
DD
NC
SS
SS
NC
SS
NC
NC
NC
AACE1CE2NCNCBWBBWACE3VDDVSSCLKGWBWEOEADSC
100999897969594939291908988878685848382
1
2
3
4
5
6
7
B
B
8
9
10
11
B
B
B
B
12
13
14
15
16
17
18
19
20
100-pin TQFP
CY7C1327F
21
B
B
B
22
23
24
25
26
27
28
29
30
ADSP
ADVAA
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
81
A
NC
NC
V
DDQ
V
SS
NC
DQP
DQ
DQ
V
SS
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SS
DQ
DQ
NC
NC
V
SS
V
DDQ
NC
NC
NC
A
A
A
A
A
BYTE A
A
A
A
A
31323334353637383940414243444546474849
A
A
1A0
A
A
A
NC
NC
SS
V
V
DD
NC
NC
A
AAA
50
A
A
A
MODE
Document #: 38-05216 Rev. *B Page 2 of 17
Pin Configurations
119-ball BGA
CY7C1327F
2
V
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DQ
V
DQ
V
DQ
V
DDQ
NC
NC
B
NC
DDQ
NC
B
DDQ
NC
B
DDQ
B
NC
NC
NC
DDQ
AA AAADSP V
CE
2
NCDQ
DQ
B
NC
DQ
B
NC
V
DD
DQ
B
NC
DQ
B
NC
DQP
B
A
345671
V
V
V
V
V
NC
V
BW
V
V
V
NC
A
SS
SS
SS
ss
SS
SS
A
SS
SS
SS
A
AA
V
SS
V
SS
V
SS
BW
B
V
SS
NC V
V
SS
V
ss
V
SS
V
SS
V
SS
MODE
ADSC
V
DD
NC
CE
1
OE
ADV
GW
DD
CLK
NC
BWE
A1
A0
V
DD
ANCA
NCNCNCNC
A
CE
AA
DQP
NC
DQ
NC
DQ
V
DD
NC
DQ
NC
DQ
NC
A
AA
NC
DDQ
3
NC
NC
NC
A
DQ
A
V
DQ
V
DQ
V
DQ
DDQ
A
NC
DDQ
A
NC
DDQ
NC
A
A
A
A
A
NC
ZZ
V
DDQ
Document #: 38-05216 Rev. *B Page 3 of 17
Pin Definitions
Name TQFP BGA I/O Description
A
, A1, A 37,36,
0
32,33,34,
35,44,45,
46,47,48,
49,50,80,
81,82,99,
P4,N4,A2,
C2,R2,T2,
A3,B3,C3,
T3,A5,B5,
C5,T5,A6,
C6,R6,T6
Input-
Synchronous
100
BWA,BW
GW
BWE
93,94 L5,G3 Input-
B
88 H4 Input-
87 M4 Input-
Synchronous
Synchronous
Synchronous
CLK 89 K4 Input-
Clock
CE
1
CE
2
CE
3
OE
ADV
ADSP
98 E4 Input-
Synchronous
97 B2 Input-
Synchronous
92 B6 Input-
Synchronous
86 F4 Input-
Asynchronous
83 G4 Input-
Synchronous
84 A4 Input-
Synchronous
ZZ 64 T7 Input-
Asynchronous
ADSC
DQ
A,
DQ
B
DQP
DQP
A,
B
85 B4 Input-
58,59,62,
63,68,69,
72,73
8,9,12,13,
18,19,22,
23
74,24
F6,H6,L6,
N6,E7,G7,
K7,P7
D1,H1,L1,
N1,E2,G2,
K2,M2,
D6,P2
Synchronous
I/O-
Synchronous
Address Inputs used to select one of the 256K address locations. Sampled
at the rising edge of the CLK if ADSP
CE2, and CE3 are sampled active. A1, A0 feed the 2-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct
byte writes to the SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the
rising edge of CLK, a global write is conducted (ALL bytes are written,
regardless of the values on BW
[A:B]
Byte Write Enable Input, active LOW. Sampled on the rising edge of
CLK. This signal must be asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also
used to increment the burst counter when ADV
a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK.
Used in conjunction with
is ignored if CE
is HIGH.
1
CE
and
2
CE
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK.
Used in conjunction with
CE
and
1
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK.
Used in conjunction with CE
and CE2 to select/deselect the device.
1
connected for BGA. Where referenced, CE3 is assumed active throughout
this document for BGA.
Output Enable, asynchronous input, active LOW. Controls the
direction of the I/O pins. When LOW, the I/O pins behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and act as input data pins.
OE
is masked during the first clock of a read cycle when emerging from a
deselected state.
Advance Input signal, sampled on the rising edge of CLK, active
LOW. When asserted, it automatically increments the address in a burst
cycle.
Address Strobe from Processor, sampled on the rising edge of CLK,
active LOW. When asserted LOW, A is captured in the address registers.
A1, A0 are also loaded into the burst counter. When
both asserted, only
is recognized.
ADSP
deasserted HIGH.
ZZ “sleep” Input, active HIGH. This input, when High places the device
in a non-time-critical “sleep” condition with data integrity preserved. For
normal operation, this pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
Address Strobe from Controller, sampled on the rising edge of CLK,
active LOW. When asserted LOW, A is captured in the address registers.
A1, A0 are also loaded into the burst counter. When
both asserted, only
ADSP
is recognized.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data
register that is triggered by the rising edge of CLK. As outputs, they deliver
the data contained in the memory location specified by “A” during the
previous clock rise of the read cycle. The direction of the pins is controlled
by
. When OE is asserted LOW, the pins behave as outputs. When
OE
HIGH, DQs and DQP
are placed in a three-state condition.
[A:B]
CY7C1327F
or
ADSC
is active LOW, and CE1,
and BWE).
is asserted LOW, during
to select/deselect the device.
3
to select/deselect the device.
CE
3
and
ADSP
is ignored when
ASDP
and
ADSP
ADSP
ADSC
CE
ADSC
Not
are
is
1
are
Document #: 38-05216 Rev. *B Page 4 of 17
Pin Definitions (continued)
Name TQFP BGA I/O Description
V
DD
V
SS
V
DDQ
MODE 31 R3 Input-
NC 1,2,3,6,7,
15,41,65,91J2,C4,J4,
R4,J6
5,10,17,
21,26,40,
55,60,67,
71,76,90
D3,E3,F3,
H3,K3,L3,
M3,N3,P3,
D5,E5,F5,
G5,H5,K5,
M5,N5,P5
4,11,20,
27,54,61,
70,77
A1,F1,J1,
M1,U1,A7,
F7,J7,M7,
U7
B1,C1,E1,
14,16,25,
28,29,30,
38,39,42,
43,51,52,
53,56,57,
66,75,78,
79,95,96
G1,K1,P1,
R1,T1,D2,
F2,H2,L2,
N2,U2,J3,
U3,D4,L4,
T4,U4,J5,
U5,E6,G6,
K6,M6,P6,
U6,B7,C7,
D7,H7,L7,
N7,R5,R7
Power Supply Power supply inputs to the core of the device.
Ground Ground for the device.
I/O Ground Ground for the I/O circuitry.
Selects Burst Order. When tied to GND selects linear burst sequence.
Static
When tied to VDD or left floating selects interleaved burst sequence. This
is a strap pin and should remain static during device operation. Mode Pin
has an internal pull-up.
No Connects. Not internally connected to the die
CY7C1327F
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1327F supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
Enable (GW
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE
asynchronous Output Enable (OE
selection and output three-state control. ADSP
CE
is HIGH.
1
) or the Controller Address Strobe (ADSC).
) inputs. A Global Write
) overrides all Byte Write inputs and writes data to
[A:B]
, CE2, CE3) and an
1
) provide for easy bank
is ignored if
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
, CE2, CE3 are all asserted active, and (3) the Write
CE
1
signals (GW
CE
is HIGH. The address presented to the address inputs (A)
1
is stored into the address advancement logic and the Address
, BWE) are all deserted HIGH. ADSP is ignored if
Register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within tco if OE
is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always three-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE
signal. Consecutive
single Read cycles are supported. Once the SRAM is
deselected at clock rise by the chip select and either ADSP
signals, its output will three-state immediately.
ADSC
or
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP
(2) CE
presented to A is loaded into the address register and the
, CE2, CE3 are all asserted active. The address
1
is asserted LOW, and
address advancement logic while being delivered to the
memory array. The Write signals (GW
ADV
inputs are ignored during this first cycle.
ADSP
-triggered Write accesses require two clock cycles to
complete. If GW
is asserted LOW on the second clock rise, the
, BWE, and BW
[A:B]
) and
Document #: 38-05216 Rev. *B Page 5 of 17
CY7C1327F
data presented to the DQ inputs is written into the corresponding address location in the memory array. If GW
then the Write operation is controlled by BWE
signals. The CY7C1327F provides Byte Write capability that is
is HIGH,
and BW
[A:B]
described in the Write Cycle Descriptions table. Asserting the
Byte Write Enable input (BWE) with the selected Byte Write
(BW
Bytes not selected during a Byte Write operation will remain
) input, will selectively write to only the desired bytes.
[A:B]
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
Because the CY7C1327F is a common I/O device, the Output
Enable (OE
) must be deserted HIGH before presenting data
to the DQ inputs. Doing so will three-state the output drivers.
As a safety precaution, DQs are automatically three-stated
whenever a Write cycle is detected, regardless of the state of
OE
.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC
deserted HIGH, (3) CE
(4) the appropriate combination of the Write inputs (GW
and BW
desired byte(s). ADSC
) are asserted active to conduct a Write to the
[A:B]
is asserted LOW, (2) ADSP is
, CE2, CE3 are all asserted active, and
1
, BWE,
-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the memory array.
The ADV
input is ignored during this cycle. If a global Write is
conducted, the data presented to DQ is written into the corresponding address location in the memory core. If a Byte Write
is conducted, only the selected bytes are written. Bytes not
selected during a Byte Write operation will remain unaltered.
A synchronous self-timed Write mechanism has been
provided to simplify the Write operations.
Because the CY7C1327F is a common I/O device, the Output
Enable (OE
) must be deserted HIGH before presenting data
to the DQ inputs. Doing so will three-state the output drivers.
As a safety precaution, DQs are automatically three-stated
whenever a Write cycle is detected, regardless of the state of
OE
.
Burst Sequences
The CY7C1327F provides a two-bit wraparound counter, fed
by A1, A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV
LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
t
he “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of t
returns LOW.
after the ZZ input
ZZREC
Interleaved Burst Address Table (MODE =
Floating or V
First
Address
A1, A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
)
DD
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Document #: 38-05216 Rev. *B Page 6 of 17
Snooze mode standby current ZZ > VDD – 0.2V 40 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to snooze current This parameter is sampled 2t
CYC
CYC
ns
ns
ns
ZZ Inactive to exit snooze current This parameter is sampled 0 ns
CY7C1327F
Truth Table
Next Cycle Add. Used ZZ
[ 2, 3, 4, 5, 6]
CE
CE
1
CE
2
ADSP ADSC ADV OE
3
DQ
WRITE
Unselected None L H X X X L X X three-state X
Unselected None L L X H L X X X three-state X
Unselected None L L L X L X X X three-state X
Unselected None L L X H H L X X three-state X
Unselected None L L L X H L X X three-state X
Begin Read External L L H L L X X X three-state X
Begin Read External L L H L H L X X three-state Read
Continue Read Next L X X X H H L H three-state Read
Continue Read Next L X X X H H L L DQ Read
Continue Read Next L H X X X H L H three-state Read
Continue Read Next L H X X X H L L DQ Read
Suspend Read Current L X X X H H H H three-state Read
Suspend Read Current L X X X H H H L DQ Read
Suspend Read Current L H X X X H H H three-state Read
Suspend Read Current L H X X X H H L DQ Read
Begin Write Current L X X X H H H X three-state Write
Begin Write Current L H X X X H H X three-state Write
Begin Write External L L H L H H X X three-state Write
Continue Write Next L X X X H H H X three-state Write
Continue Write Next L H X X X H H X three-state Write
Suspend Write Current L X X X H H H X three-state Write
Suspend Write Current L H X X X H H X three-state Write
ZZ “Sleep” None H X X X X X X X three-state X
Truth Table for Read/Write
Function
[2]
GW BWE
BW
B
BW
A
Read H H X X
Read H L H H
Write Byte A – (DQ
Write Byte B – (DQ
and DQPA)HLHL
A
and DQPB)HLLH
B
Write Bytes B, A H L L L
Write All Bytes H L L L
Write All Bytes L X X X
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE
4. The DQ pins are controlled by the current cycle and the
5. The SRAM always initiates a read cycle when ADSP
6.
= L when any one or more Byte Write enable signals (BWA, BWB) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BWA, BWB),
BWE
, GW = H.
after the
a don't care for the remainder of the write cycle.
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE
OE
is
inactive or when the device is deselected, and all data bits behave as output when
or with the assertion of
ADSP
. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
ADSC
signal. OE is asynchronous and is not sampled with the clock.
OE
is asserted, regardless of the state of GW, BWE, or BW
is active (LOW)
OE
.
. Writes may occur only on subsequent clocks
[A: B]
Document #: 38-05216 Rev. *B Page 7 of 17
CY7C1327F
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
Relative to GND........ –0.5V to +4.6V
DD
DC Voltage Applied to Outputs
in three-state ....................................... –0.5V to V
DC Input Voltage....................................–0.5V to V
DDQ
DD
+ 0.5V
+ 0.5V
Electrical Characteristics Over the Operating Range
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Commercial 0°C to +70°C 3.3V –5%/+10% 2.5V –5%
Industrial –40°C to +85°C
[7, 8]
Ambient
Temperat ure V
DD
V
DDQ
to V
Parameter Description Test Conditions Min. Max. Unit
V
V
V
V
V
V
I
I
I
DD
DDQ
OH
OL
IH
IL
X
OZ
DD
Power Supply Voltage 3.135 3.6 V
I/O Supply Voltage 2.375 V
Output HIGH Voltage V
Output LOW Voltage V
Input HIGH Voltage
Input LOW Voltage
[7]
[7]
Input Load Current
except ZZ and MODE
Input Current of MODE Input = V
Input Current of ZZ Input = V
Output Leakage Current GND ≤ VI ≤ V
VDD Operating Supply
Current
= 3.3V, VDD = Min., I
DDQ
V
= 2.5V, VDD = Min., I
DDQ
= 3.3V, VDD = Min., I
DDQ
V
= 2.5V, VDD = Min., I
DDQ
V
= 3.3V 2.0 VDD + 0.3V V
DDQ
V
= 2.5V 1.7 VDD + 0.3V V
DDQ
V
= 3.3V –0.3 0.8 V
DDQ
V
= 2.5V –0.3 0.7 V
DDQ
GND ≤ VI ≤ V
Input = V
Input = V
V
= Max.,
DD
= 0 mA,
I
OUT
f = f
MAX
1/t
CYC
=
SS
DD
SS
DD
DDQ
Output Disabled –5 5 µA
DDQ,
= –4.0 mA 2.4 V
OH
= –2.0 mA 2.0 V
OH
= 8.0 mA 0.4 V
OL
= 2.0 mA 0.4 V
OL
–5 5 µA
–30 µA
–5 µA
4-ns cycle,250MHz 325 mA
4.4-ns cycle,225MHz 290 mA
5-ns cycle,200MHz 265 mA
DD
5 µA
30 µA
6-ns cycle,166MHz 240 mA
7.5-ns cycle,133MHz 225 mA
10-ns cycle,100MHz 205 mA
I
SB1
Automatic CE
Power-down
Current—TTL Inputs
V
= Max, Device
DD
Deselected, V
V
≤ V
IN
IL
f = f
MAX
= 1/t
≥ VIH or
IN
CYC
4-ns cycle,250MHz 120 mA
4.4-ns cycle,225MHz 115 mA
5-ns cycle,200MHz 110 mA
6-ns cycle,166MHz 100 mA
7.5-ns cycle,133MHz 90 mA
10-ns cycle,100MHz 80 mA
I
SB2
Shaded areas contain advance information.
Notes:
7. Overshoot: V
8. T
Power-up
Automatic CE
Power-down
Current—CMOS Inputs
(AC) < VDD +1.5V (Pulse width less than t
IH
: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and V
V
= Max, Device
DD
Deselected, V
> V
V
IN
– 0.3V, f = 0
DDQ
/2), undershoot: VIL(AC) > -2V (Pulse width less than t
CYC
≤ 0.3V or
IN
All speeds 40 mA
DDQ
< VDD.
CYC
/2).
DD
V
Document #: 38-05216 Rev. *B Page 8 of 17
CY7C1327F
Electrical Characteristics Over the Operating Range (continued)
[7, 8]
Parameter Description Test Conditions Min. Max. Unit
I
SB3
Automatic CE
Power-down
Current—CMOS Inputs
V
= Max, Device
DD
Deselected, or V
or V
f = f
IN
MAX
> V
DDQ
= 1/t
– 0.3V
CYC
≤ 0.3V
IN
4-ns cycle,250MHz 105 mA
4.4-ns cycle,225MHz 100 mA
5-ns cycle,200MHz 95 mA
6-ns cycle,166MHz 85 mA
7.5-ns cycle,133MHz 75 mA
10-ns cycle,100MHz 65 mA
I
SB4
Automatic CE
Power-down
Current—TTL Inputs
Thermal Resistance
[9]
Parameter Description Test Conditions
Θ
Θ
Capacitance
Thermal Resistance
JA
(Junction to Ambient)
Thermal Resistance
JC
(Junction to Case)
[9]
Parameter Description Test Conditions
C
Input Capacitance TA = 25°C, f = 1 MHz,
IN
C
CLK
C
I/O
Clock Input Capacitance 5 5 pF
Input/Output Capacitance 5 7 pF
V
= Max, Device
DD
Deselected, V
V
≤ VIL, f = 0
IN
All speeds 45 mA
≥ VIH or
IN
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA / JESD51.
V
= 3.3V.
DD
V
= 3.3V
DDQ
TQFP
Package
BGA
Package Unit
41.83 47.63 °C/W
9.99 11.71 °C/W
TQFP
Package
BGA
Package Unit
55pF
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
Z
= 50Ω
0
R
L
3.3V
OUTPUT
= 50Ω
5pF
VL= 1.5V
INCLUDING
(a)
JIG AND
SCOPE
2.5V I/O Test Load
OUTPUT
= 50Ω
Z
0
= 1.25V
V
L
R
L
(a)
Notes:
9. Tested initially and after any design or process change that may affect these parameters
2.5V
OUTPUT
= 50Ω
5pF
INCLUDING
JIG AND
SCOPE
R = 317Ω
R = 351Ω
(b)
R = 1667Ω
R =1538Ω
(b)
GND
V
DD
GND
V
DD
≤ 1ns
≤ 1ns
ALL INPUT PULSES
10%
10%
90%
ALL INPUT PULSES
90%
90%
10%
≤ 1ns
(c)
90%
10%
≤ 1ns
(c)
Document #: 38-05216 Rev. *B Page 9 of 17
CY7C1327F
Switching Characteristics Over the Operating Range
[14, 15]
250 MHz 225 MHz 200 MHz 166 MHz 133 MHz 100 MHz
Parameter Description
t
POWER
VDD(Typical) to the first
[10]
Min. Max Min. Max Min. Max Min. Max Min. Max Min. Max
1 1 1 111ms
Clock
t
CYC
t
CH
t
CL
Clock Cycle Time 4.0 4.4 5.0 6.0 7.5 10 ns
Clock HIGH 1.7 2.0 2.0 2.5 3.0 3.5 ns
Clock LOW 1.7 2.0 2.0 2.5 3.0 3.5 ns
Output Times
t
CO
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Data Output Valid After CLK
Rise
Data Output Hold After CLK
Rise
Clock to Low-Z
Clock to High-Z
[11, 12, 13]
[11, 12, 13]
OE LOW to Output Valid
LOW to Output Low-Z
OE
12, 13]
OE HIGH to Output High-Z
12, 13]
[11,
[11,
2.6 2.6 2.8 3.5 4.0 4.5 ns
1.0 1.0 1.0 2.0 2.0 2.0 ns
0 0 0 000ns
2.6 2.6 2.8 3.5 4.0 4.5 ns
2.6 2.6 2.8 3.5 4.5 4.5 ns
0 0 0 000ns
2.6 2.6 2.8 3.5 4.0 4.5 ns
Set-up Times
t
AS
t
ADS
Address Set-up Before CLK
Rise
,
ADSC
ADSP
Set-up Before
0.8 1.2 1.2 1.5 1.5 1.5 ns
0.8 1.2 1.2 1.5 1.5 1.5 ns
CLK Rise
t
ADVS
t
WES
t
DS
t
CES
ADV Set-up Before CLK Rise
GW, BWE, BW
Before CLK Rise
[A:B]
Set-up
Data Input Set-up Before CLK
Rise
Chip Enable Set-Up Before
CLK Rise
0.8 1.2 1.2 1.5 1.5 1.5 ns
0.8 1.2 1.2 1.5 1.5 1.5 ns
0.8 1.2 1.2 1.5 1.5 1.5 ns
0.8 1.2 1.2 1.5 1.5 1.5 ns
Hold Times
t
AH
t
ADH
Address Hold After CLK Rise 0.4 0.5 0.5 0.5 0.5 0.5 ns
ADSP
,
ADSC
Hold After CLK
0.4 0.5 0.5 0.5 0.5 0.5 ns
Rise
t
ADVH
t
WEH
t
DH
t
CEH
Shaded areas contain advance information.
Notes:
10. This part has a voltage regulator internally; t
can be initiated.
, t
11. t
CHZ
CLZ,tOELZ
12. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
13. This parameter is sampled and not 100% tested.
14. Timing references level is 1.5V when V
15. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Hold After CLK Rise
ADV
,
GW
BWE, BW
CLK Rise
[A:B]
Hold After
Data Input Hold After CLK
Rise
Chip Enable Hold After CLK
Rise
POWER
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
OEHZ
is less than t
OEHZ
= 3.3V and is 1.25V when V
DDQ
0.4 0.5 0.5 0.5 0.5 0.5 ns
0.4 0.5 0.5 0.5 0.5 0.5 ns
0.4 0.5 0.5 0.5 0.5 0.5 ns
0.4 0.5 0.5 0.5 0.5 0.5 ns
is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation
and t
OELZ
is less than t
CHZ
= 2.5V on all data sheets.
DDQ
to eliminate bus contention between SRAMs when sharing the same
CLZ
Unit
Document #: 38-05216 Rev. *B Page 10 of 17
D
Switching Waveforms
Read Cycle Timing
[16]
t
CY7C1327F
CYC
CLK
ADSP
ADSC
ADDRESS
GW, BWE,
[A:B]
BW
CE
ADV
OE
ata Out (Q)
t
ADS
t
t
CL
CH
t
ADH
t
t
ADH
ADS
t
t
AH
AS
A1
t
WES
t
t
CEH
CES
A2 A3
t
WEH
t
t
ADVH
ADVS
Burst continued with
new base address
Deselect
cycle
ADV
suspends
burst.
t
OEV
t
OELZ
High-Z
t
CLZ
t
OEHZ
Q(A1)
t
CO
Single READ BURST READ
t
CO
t
DOH
Q(A2) Q(A2 + 1) Q(A2 + 2)
t
CHZ
Q(A2) Q(A2 + 1)Q(A2 + 3)
Burst wraps around
to its initial state
Notes:
16. On this diagram, when CE
17.
Full width write can be initiated by either GW
is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
DON’T CARE
LOW; or by GW HIGH, BWE LOW and BW
UNDEFINED
LOW.
[A:B]
Document #: 38-05216 Rev. *B Page 11 of 17
Switching Waveforms (continued)
D
Write Cycle Timing
[16, 17]
t
CYC
CY7C1327F
CLK
ADSP
ADSC
ADDRESS
BWE,
BW[A :B]
GW
ADV
t
t
CL
CH
t
t
ADH
ADS
t
t
ADH
ADS
t
t
AH
AS
A1
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t
t
CEH
CES
CE
A2 A3
t
t
WEH
WES
ADV suspends burst
ADSC extends burst
t
ADS
t
ADH
t
WES
t
ADVS
t
WEH
t
ADVH
OE
Data In (D)
ata Out (Q)
t
t
DH
DS
High-Z
BURST READ BURST WRITE
t
OEHZ
D(A1)
Single WRITE
D(A2) D(A2 + 1) D(A2 + 1)
DON’T CARE
UNDEFINED
D(A2 + 2)
D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)
Extended BURST WRITE
Document #: 38-05216 Rev. *B Page 12 of 17
Switching Waveforms (continued)
D
Read/Write Cycle Timing[16, 18, 19]
t
CYC
CY7C1327F
CLK
ADSP
ADSC
ADDRESS
BWE,
BW
[A:B]
CE
ADV
OE
Data In (D)
t
t
CL
CH
t
t
ADH
ADS
t
t
AH
AS
High-Z
t
CES
A2
t
CEH
t
CO
t
CLZ
t
OEHZ
t
WES
t
DS
D(A3)
A3
t
A1
A4 A5 A6
t
WEH
DH
t
OELZ
D(A5) D(A6)
ata Out (Q)
High-Z
Q(A2)Q(A1)
Single WRITE
DON’T CARE UNDEFINED
Q(A4) Q(A4+1) Q(A4+2)
BURST READBack-to-Back READs
Q(A4+3)
Back-to-Back
WRITEs
Notes:
18.
The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by
19.
is HIGH.
GW
ADSP
or ADSC
.
Document #: 38-05216 Rev. *B Page 13 of 17
Switching Waveforms (continued)
A
ZZ Mode Timing
[20, 21]
CLK
CY7C1327F
t
ZZ
t
ZZREC
ZZ
I
SUPPLY
LL INPUTS
(except ZZ)
Outputs (Q)
t
ZZI
I
DDZZ
High-Z
t
RZZI
DESELECT or READ Only
DON’T CARE
Ordering Information
Speed
(MHz) Ordering Code
250
CY7C1327F-250AC A101 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial
CY7C1327F-250BGC BG119 119-Ball BGA (14 x 22 x 2.4mm)
CY7C1327F-250AI A101 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Industrial
CY7C1327F-250BGI BG119 119-Ball BGA (14 x 22 x 2.4mm)
225
CY7C1327F-225AC A101 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial
CY7C1327F-225BGC BG119 119-Ball BGA (14 x 22 x 2.4mm)
CY7C1327F-225AI A101 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Industrial
CY7C1327F-225BGI BG119 119-Ball BGA (14 x 22 x 2.4mm)
200
CY7C1327F-200AC A101 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial
CY7C1327F-200BGC BG119 119-Ball BGA (14 x 22 x 2.4mm)
CY7C1327F-200AI A101 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Industrial
CY7C1327F-200BGI BG119 119-Ball BGA (14 x 22 x 2.4mm)
166 CY7C1327F-166AC A101 100-Lead Thin Quad Flat Pact (14 x 20 x 1.4mm) Commercial
CY7C1327F-166BGC BG119 119-Ball BGA (14 x 22 x 2.4mm)
CY7C1327F-166AI A101 100-Lead Thin Quad Flat Pact (14 x 20 x 1.4mm) Industrial
CY7C1327F-166BGI BG119 119-Ball BGA (14 x 22 x 2.4mm)
133 CY7C1327F-133AC A101 100-Lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Commercial
CY7C1327F-133BGC BG119 119-Ball BGA(14 x 22 x 2.4mm)
CY7C1327F-133AI A101 100-Lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Industrial
CY7C1327F-133BGI BG119 119-Ball BGA(14 x 22 x 2.4mm)
Notes:
20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
21. DQs are in high-Z when exiting ZZ sleep mode.
Package
Name Package Type
Operating
Range
Document #: 38-05216 Rev. *B Page 14 of 17
Ordering Information (continued)
Speed
(MHz) Ordering Code
100
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
CY7C1327F-100AC A101 100-Lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Commercial
CY7C1327F-100BGC BG119 119-Ball BGA(14 x 22 x 2.4mm)
CY7C1327F-100AI A101 100-Lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Industrial
CY7C1327F-100BGI BG119 119-Ball BGA(14 x 22 x 2.4mm)
Package Diagrams
100-pin Thin Plastic Quad Flat Pack (14 x 20 x 1.4mm) A101
Package
Name Package Type
CY7C1327F
Operating
Range
51-85050*A
Document #: 38-05216 Rev. *B Page 15 of 17
Package Diagrams (continued)
CY7C1327F
119-lead BGA (14 x 22 x 2.4 mm) BG119
51-85115-*A
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark
of IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders.
Document #: 38-05216 Rev. *B Page 16 of 17
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other righ ts. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1327F
Document History Page
Document Title: CY7C1327F 4-Mb (256K x 18) Pipelined Sync SRAM
Document Number: 38-05216
REV. ECN NO. Issue Date
** 119823 01/06/03 HGK New Data Sheet
*A 123849 01/18/03 AJH Added power up requirements to AC test loads and waveforms information
*B 200660 See ECN SWI Final Data Sheet
Orig. of
Change Description of Change
Document #: 38-05216 Rev. *B Page 17 of 17
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