CYPRESS CY7C1327F User Manual

A B

CY7C1327F

4-Mb (256K x 18) Pipelined Sync SRAM

Features

• Registered inputs and outputs for pipelined operation

• 256K ×18 common I/O architecture

• 3.3V core power supply

• 3.3V / 2.5V I/O operation

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 2.6 ns (for 225-MHz device)

— 2.8 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

— 4.5 ns (for 100-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel



Pentium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Offered in JEDEC-standard 100-pin TQFP and 119 Ball BGA packages.

• “ZZ” Sleep Mode Option

Logic Block Diagram

Functional Description

[1]

The CY7C1327F SRAM integrates 262,144 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (

), depth-expansion Chip Enables (CE2 and

Control inputs ( (

inputs include the Output Enable (

[A:B]

, and

BWE

ADSC

), and Global Write (GW). Asynchronous

ADSP

and

), Write Enables

ADV

) and the ZZ pin.

), Burst

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ( Address Strobe Controller (

) are active. Subsequent

ADSC

ADSP

) or

burst addresses can be internally generated as controlled by the Advance pin (

ADV

Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two bytes wide as controlled by the byte write control inputs.

causes all bytes to be written.

LOW

when active

The CY7C1327F operates from a +3.3V core power supply while all outputs also operate with a +3.3V or a +2.5V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

0, A1, A

MODE

ADV

CLK

ADSC

ADSP

BWE

CE2 CE3

Note:

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com

ADDRESS REGISTER

DQB,DQP

WRITE REGISTER

DQA,DQP

WRITE REGISTER

ENABLE

SLEEP

CONTROL

BURST

COUNTER AND

LOGIC

CLR

PIPELINED

ENABLE

A[1:0]

DQB,DQP

WRITE DRIVER

DQA,DQP

WRITE DRIVER

MEMORY

ARRAY

SENSE AMPS

OUTPUT

REGISTERS

OUTPUT BUFFERS

INPUT

REGISTERS

DQs DQP DQP

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-05216 Rev. *B Revised December 12, 2003

CY7C1327F

Selection Guide

250 MHz 225 MHz 200 MHz 166 MHz 133 MHz 100 MHz Unit

Maximum Access Time 2.6 2.6 2.8 3.5 4.0 4.5 ns

Maximum Operating Current 325 290 265 240 225 205 mA

Maximum CMOS Standby Current

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

Pin Configurations

40 40 40 40 40 40 mA

BYTE B

DDQ

DQ DQ

DDQ

DQ DQ

DDQ

DQ DQ

DQP

DDQ

NC NC NC

NC NC

NC NC NC

AACE1CE2NCNCBWBBWACE3VDDVSSCLKGWBWEOEADSC

100999897969594939291908988878685848382 1 2 3 4 5 6 7

8 9 10 11

12 13 14 15

16 17 18 19 20

100-pin TQFP

CY7C1327F

22 23 24 25 26 27 28 29 30

ADSP

ADVAA

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

A NC NC V

DDQ

NC DQP DQ DQ V

DDQ

DQ DQ V

NC V

ZZ DQ DQ V

DDQ

DQ DQ NC NC V

DDQ

NC NC NC

BYTE A

31323334353637383940414243444546474849

1A0

AAA

MODE

Document #: 38-05216 Rev. *B Page 2 of 17

Pin Configurations

119-ball BGA

CY7C1327F

DDQ

AA AAADSP V

NCDQ

DQP

345671

V V

NC V

MODE

ADSC

ADV

CLK

BWE

ANCA

NCNCNCNC

DQP

DDQ

Document #: 38-05216 Rev. *B Page 3 of 17

Pin Definitions

Name TQFP BGA I/O Description

, A1, A 37,36,

32,33,34, 35,44,45, 46,47,48, 49,50,80, 81,82,99,

P4,N4,A2, C2,R2,T2, A3,B3,C3,

T3,A5,B5,

C5,T5,A6,

C6,R6,T6

Input-

Synchronous

100

BWA,BW

BWE

93,94 L5,G3 Input-

88 H4 Input-

87 M4 Input-

Synchronous

CLK 89 K4 Input-

Clock

ADV

ADSP

98 E4 Input-

Synchronous

97 B2 Input-

Synchronous

92 B6 Input-

Synchronous

86 F4 Input-

Asynchronous

83 G4 Input-

Synchronous

84 A4 Input-

Synchronous

ZZ 64 T7 Input-

Asynchronous

ADSC

DQP DQP

A, B

85 B4 Input-

58,59,62, 63,68,69,

72,73

8,9,12,13,

18,19,22,

74,24

F6,H6,L6,

N6,E7,G7,

K7,P7 D1,H1,L1, N1,E2,G2,

K2,M2,

D6,P2

Synchronous

I/O-

Synchronous

Address Inputs used to select one of the 256K address locations. Sampled at the rising edge of the CLK if ADSP CE2, and CE3 are sampled active. A1, A0 feed the 2-bit counter.

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK.

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW

[A:B]

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write.

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV a burst operation.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with is ignored if CE

is HIGH.

and

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

and

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE2 to select/deselect the device.

connected for BGA. Where referenced, CE3 is assumed active throughout this document for BGA.

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE

is masked during the first clock of a read cycle when emerging from a

deselected state.

Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it automatically increments the address in a burst

cycle.

Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, A is captured in the address registers.

A1, A0 are also loaded into the burst counter. When both asserted, only

is recognized.

ADSP

deasserted HIGH.

ZZ “sleep” Input, active HIGH. This input, when High places the device in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.

Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, A is captured in the address registers.

A1, A0 are also loaded into the burst counter. When both asserted, only

ADSP

is recognized.

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by “A” during the previous clock rise of the read cycle. The direction of the pins is controlled by

. When OE is asserted LOW, the pins behave as outputs. When

HIGH, DQs and DQP

are placed in a three-state condition.

[A:B]

CY7C1327F

ADSC

is active LOW, and CE1,

and BWE).

is asserted LOW, during

to select/deselect the device.

and

ADSP

is ignored when

ASDP

and

ADSP

ADSC

Not

are

Document #: 38-05216 Rev. *B Page 4 of 17

Pin Definitions (continued)

Name TQFP BGA I/O Description

DDQ

MODE 31 R3 Input-

NC 1,2,3,6,7,

15,41,65,91J2,C4,J4,

R4,J6

5,10,17, 21,26,40, 55,60,67,

71,76,90

D3,E3,F3,

H3,K3,L3, M3,N3,P3, D5,E5,F5, G5,H5,K5,

M5,N5,P5

4,11,20,

27,54,61,

70,77

A1,F1,J1, M1,U1,A7,

F7,J7,M7,

B1,C1,E1,

14,16,25, 28,29,30, 38,39,42, 43,51,52, 53,56,57, 66,75,78,

79,95,96

G1,K1,P1, R1,T1,D2,

F2,H2,L2,

N2,U2,J3, U3,D4,L4,

T4,U4,J5, U5,E6,G6, K6,M6,P6, U6,B7,C7, D7,H7,L7,

N7,R5,R7

Power Supply Power supply inputs to the core of the device.

Ground Ground for the device.

I/O Ground Ground for the I/O circuitry.

Selects Burst Order. When tied to GND selects linear burst sequence.

Static

When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up.

No Connects. Not internally connected to the die

CY7C1327F

Functional Overview

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock.

The CY7C1327F supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.

Byte Write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW Enable (GW all four bytes. All writes are simplified with on-chip synchronous self-timed Write circuitry.

Three synchronous Chip Selects (CE asynchronous Output Enable (OE selection and output three-state control. ADSP CE

is HIGH.

) or the Controller Address Strobe (ADSC).

) inputs. A Global Write

) overrides all Byte Write inputs and writes data to

[A:B]

, CE2, CE3) and an

) provide for easy bank

is ignored if

Single Read Accesses

This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)

, CE2, CE3 are all asserted active, and (3) the Write

signals (GW CE

is HIGH. The address presented to the address inputs (A)

is stored into the address advancement logic and the Address

, BWE) are all deserted HIGH. ADSP is ignored if

Register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tco if OE

is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE

signal. Consecutive single Read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP

signals, its output will three-state immediately.

ADSC

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP (2) CE presented to A is loaded into the address register and the

, CE2, CE3 are all asserted active. The address

is asserted LOW, and

address advancement logic while being delivered to the memory array. The Write signals (GW ADV

inputs are ignored during this first cycle.

ADSP

-triggered Write accesses require two clock cycles to

complete. If GW

is asserted LOW on the second clock rise, the

, BWE, and BW

[A:B]

) and

Document #: 38-05216 Rev. *B Page 5 of 17

CY7C1327F

data presented to the DQ inputs is written into the corresponding address location in the memory array. If GW then the Write operation is controlled by BWE signals. The CY7C1327F provides Byte Write capability that is

is HIGH,

and BW

[A:B]

described in the Write Cycle Descriptions table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BW Bytes not selected during a Byte Write operation will remain

) input, will selectively write to only the desired bytes.

[A:B]

unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations.

Because the CY7C1327F is a common I/O device, the Output Enable (OE

) must be deserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. As a safety precaution, DQs are automatically three-stated whenever a Write cycle is detected, regardless of the state of OE

Single Write Accesses Initiated by ADSC

ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC deserted HIGH, (3) CE (4) the appropriate combination of the Write inputs (GW and BW desired byte(s). ADSC

) are asserted active to conduct a Write to the

[A:B]

is asserted LOW, (2) ADSP is

, CE2, CE3 are all asserted active, and

, BWE,

-triggered Write accesses require a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The ADV

input is ignored during this cycle. If a global Write is conducted, the data presented to DQ is written into the corresponding address location in the memory core. If a Byte Write is conducted, only the selected bytes are written. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations.

Because the CY7C1327F is a common I/O device, the Output Enable (OE

Burst Sequences

The CY7C1327F provides a two-bit wraparound counter, fed by A1, A0, that implements either an interleaved or linear burst

sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input.

Asserting ADV

LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering t

he “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of t returns LOW.

after the ZZ input

ZZREC

Interleaved Burst Address Table (MODE = Floating or V

First

Address

A1, A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

)

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

Linear Burst Address Table (MODE = GND)

First

Address

A1, A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

DDZZ

ZZS

ZZREC

ZZI

RZZI

Document #: 38-05216 Rev. *B Page 6 of 17

Snooze mode standby current ZZ > VDD – 0.2V 40 mA

Device operation to ZZ ZZ > VDD – 0.2V 2t

ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ active to snooze current This parameter is sampled 2t

CYC

ZZ Inactive to exit snooze current This parameter is sampled 0 ns

+ 11 hidden pages

CYPRESS CY7C1327F User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual