Cypress CY7C1324H User Manual

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CY7C1324H

2-Mbit (128K x 18) Flow-Through Sync SRAM

Features

• 128K x 18 common I/O

• 3.3V core power supply

• 3.3V/2.5V I/O supply

• Fast clock-to-output times
— 6.5 ns (133-MHz version)

• Provide high-performance 2-1-1-1 access rate

• User-selectable burst counter supporting Intel
Pentium

®

interleaved or linear burst sequences

®

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• Offered in JEDEC-standard lead-free 100-pin TQFP
package

• “ZZ” Sleep Mode option

Functional Description

[1]

The CY7C1324H is a 128K x 18 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the

Logic Block Diagram

first address in a burst and increments the address automati­cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-trigg ered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE

), depth-expansion Chip Enables (CE2 and CE3), Burst

1

Control inputs (ADSC
(BW

[A:B]

nputs include the Output Enable

i

,

and

BWE

, ADSP,

ADV), Write Enables

and

), and Global Write (GW). Asynchronous

(OE)

and the ZZ pin

. The
CY7C1324H allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP
Address Strobe (ADSC

) inputs. Address advancement is

controlled by the Address Advancement (ADV

) or the cache Controller

) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
Address Strobe Controller (ADSC

) are active. Subsequent

) or

burst addresses can be internally generated as controlled by
the Advance pin (ADV

).

The CY7C1324H operates from a +3.3V core power supply
while all outputs may operate with either a +3.3V or +2.5 V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.

0,A1,A

MODE

ADV

CLK

ADSC
ADSP

B

BW

BW

A

BWE

GW

CE

1

CE

2

CE

3

OE

ZZ

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

ADDRESS
REGISTER

DQB,DQP

B

WRITE REGISTER

A

,DQP

A

DQ

WRITE REGISTER

ENABLE

REGISTER

SLEEP

CONTROL

Q1

BURST

COUNTER AND

LOGIC

CLR

Q0

A[1:0]

DQB,DQP

B

WRITE DRIVER

A

,DQP

A

DQ

WRITE DRIVER

MEMORY

ARRAY

SENSE
AMPS

OUTPUT
BUFFERS

DQs
DQP
DQP

INPUT

REGISTERS

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-00208 Rev. *B Revised April 26, 2006

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CY7C1324H

Selection Guide

133 MHz Unit

Maximum Access Time 6.5 ns
Maximum Operating Current 225 mA
Maximum Standby Current

Pin Configurations

100-pin TQFP Pinout

40 mA

BYTE B

V

DDQ

V

DQ
DQ

V

V

DDQ

DQ
DQ

V
NC

V
DQ
DQ

V

DDQ

V
DQ
DQ

DQP

V

V

DDQ

NC
NC
NC

SS

NC
NC

SS

NC

DD

SS

SS

NC

SS

NC
NC
NC

A

100

CE

CE

NC

NC

99989796959493929190898887868584838281

2

1

A

1
2
3
4
5
6
7
8

B

9

B

10
11
12

B

13

B

14
15
16
17
18

B

19

B

20
21
22

B

23

B

24

B

25
26
27
28
29
30

3

BBWA

CE

BW

VDDV

CY7C1324H

SS

CLK

GW

BWE

OE

ADSC

ADSP

ADV

A

A

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

A
NC

NC
V

DDQ

V

SS

NC
DQP
DQ
DQ
V

SS

V

DDQ

DQ
DQ
V

SS

NC
V

DD

ZZ
DQ

DQ
V

DDQ

V

SS

DQ
DQ
NC
NC
V

SS

V

DDQ

NC
NC
NC

B
A
A

A
A

BYTE A

A
A

A
A

31323334353637383940414243444546474849

AAAAA1A

MODE

0

NC/72M

NC/36M

SS

DD

V

V

NC/18M

NC/9M

AAAAA

50

A

NC/4M

Document #: 001-00208 Rev. *B Page 2 of 15

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CY7C1324H

Pin Definitions

Name I/O Description

A0, A1, A Input-

Synchronous

BWA,BW

B

Input-

Synchronous

GW Input-

Synchronous

BWE Input-

Synchronous

CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the

CE

CE

CE

1

2

3

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

OE Input-

Asynchronous

ADV Input-

Synchronous

ADSP Input-

Synchronous

ADSC Input-

Synchronous

ZZ Input-

Asynchronous

DQs
DQP

V

DD

V

SS

V

DDQ

A,

DQP

B

I/O-

Synchronous

Power

Supply

Ground Ground for the device.

I/O Power

Supply

MODE Input-

Static

NC No Connects. Not Internally connected to the die. 4M, 9M, 18M, 72M, 144M, 288M, 576M, and

Address Inputs used to select one of the 128K address locations. Sampled at the rising
edge of the CLK if ADSP
A

feed the 2-bit counter.

[1:0]

or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active.

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the
SRAM. Sampled on the rising edge of CLK.

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
global Write is conducted (ALL bytes are written, regardless of the values on BW

and BWE).

[A:B]

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a Byte Write.

burst counter when ADV

is asserted LOW, during a burst operation.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE

and CE3 to select/deselect the device. ADSP is ignored

2

if CE1 is HIGH

CE1

.

is sampled

only when a new external address is loaded.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in co njunction

with CE

and CE3 to select/deselect the device. CE

1

is sampled only when a new external

2

address is loaded.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE
address is loaded.

and CE2 to select/deselect the device. CE3 is sampled only when a new external

1

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a Read cycle when emerging
from a deselected state.

Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.

Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers.
A

are also loaded into the burst counter. When ADSP and ADSC are both asserted,

[1:0]

only ADSP

is recognized. ASDP is ignored when

CE1 is deasserted HIGH

Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers.
A

are also loaded into the burst counter. When ADSP and ADSC are both asserted,

[1:0]

only ADSP

is recognized.

ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.

Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the Read cycle. The
direction of the pins is controlled by OE
When HIGH, DQs and DQP

[A:B]

. When OE is asserted LOW, the pins behave as outputs.

are placed in a tri-state condition.

Power supply inputs to the core of the device.

Power supply for the I/O circuitry.

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or

left floating selects interleaved burst sequence. This is a strap pin and should remain static
during device operation. Mode Pin has an internal pull-up.

1G are address expansion pins and are not internally connected to the die.

Document #: 001-00208 Rev. *B Page 3 of 15

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CY7C1324H

Functional Overview

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access d elay from
the clock rise (t

The CY7C1324H supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP

). Address advancement through the burst sequence is

(ADSC
controlled by the ADV
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.

Byte write operations are qualified with the Byte Write Enable
(BWE

) and Byte Write Select (BW
Enable (GW
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.

Three synchronous Chip Selects (CE
asynchronous Output Enable (OE
selection and output tri-state control. ADSP is ignored if CE
is HIGH.

Single Read Accesses

A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
asserted active, and (2) ADSP
the access is initiated by ADSC
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to t
rise. ADSP

is ignored if CE1 is HIGH.

Single Write Accesses Initiated by ADSP

This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, and (2) ADSP
presented are loaded into the address register and the burst
inputs (GW

, BWE, and BW
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
Write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte Writes are allowed.
During Byte Writes, BWA
DQB. All I/Os are tri-stated during a Byte Write. Since this is a
common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless
of the state of OE

Single Write Accesses Initiated by ADSC

This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE

) is 6.5 ns (133-MHz device).

CDV

) or the Controller Address Strobe

input. A two-bit on-chip wraparound

) inputs. A Global Write

) overrides all byte write inputs and writes data to

[A:B]

, CE2, CE3) and an

1

) provide for easy bank

, CE2, and CE3 are all

1

or ADSC is asserted LOW (if

, the write inputs must be

after clock

CDV

, CE2, CE3 are all asserted

1

is asserted LOW. The addresses

) are ignored during this first

[A:B]

controls DQA and BWB controls

.

, CE2, and CE3 are all asserted

1

active, (2) ADSC
HIGH, and (4) the write input signals (GW
indicate a write access. ADSC

is asserted LOW, (3) ADSP is deasserted

, BWE, and BW[A:B])

is ignored if ADSP is active

LOW.
The addresses presented are loaded into the address register

and the burst counter/control logic and delivered to the
memory core. The information presented to DQ[A:D] will be
written into the specified address location. Byte Writes are
allowed. During Byte Writes, BWA

controls DQA and BWB
controls DQB. All I/Os are tri-stated when a Write is detected,
even a Byte Write. Since this is a common I/O device, the
asynchronous OE input signal must be deasserted and the
I/Os must be tri-stated prior to the presentation of data to DQs.
As a safety precaution, the data lines are tri-stated once a
Write cycle is detected, regardless of the state of OE

Burst Sequences

The CY7C1324H provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by
A

, and can follow either a linear or interleaved burst order.

[1:0]

The burst order is determined by the state of the MODE input.
A LOW on MODE will select a linear burst sequence. A HIGH
on MODE will select an interleaved burst order. Leaving
MODE unconnected will cause the device to default to an
interleaved burst sequence.

1

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP
inactive for the duration of t
LOW.

, and ADSC must remain

after the ZZ input returns

ZZREC

Interleaved Burst Address Table
(MODE = Floating or V

First

Address

A1, A0

00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

Linear Burst Address Table (MODE = GND)

First

Address

A1, A

0

00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10

Second

Address

A1, A0

Second

Address

A1, A

0

DD

)

Third

Address

A1, A0

Third

Address

A1, A

0

.

Fourth

Address

A1, A0

Fourth

Address

A1, A

0

Document #: 001-00208 Rev. *B Page 4 of 15

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CY7C1324H

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Truth Table

Cycle Description

Deselected Cycle,
Power-down

Deselected Cycle,
Power-down

Deselected Cycle,
Power-down

Deselected Cycle,
Power-down

Deselected Cycle,
Power-down

Sleep Mode, Power-down None X X X H X X X X X X Tri-State
Read Cycle, Begin Burst External L H L L L X X X L L-H Q
Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-State
Write Cycle, Begin Burst External L H L L H L X L X L-H D
Read Cycle, Begin Burst External L H L L H L X H L L-H Q
Read Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next X X X L H H L H H L-H Tri-S tate
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q
Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
Write Cycle, Continue Burst Next X X X L H H L L X L-H D
Write Cycle, Continue Burst Next H X X L X H L L X L-H D
Read Cycle, Suspend Burst Curre nt X X X L H H H H L L-H Q
Read Cycle, Suspend Burst Curre nt X X X L H H H H H L-H Tri-State
Read Cycle, Suspend Burst Curre nt H X X L X H H H L L-H Q
Read Cycle, Suspend Burst Curre nt H X X L X H H H H L-H Tri-State
Write Cycle, Suspend Burst Current X X X L H H H L X L-H D
Write Cycle, Suspend Burst Current H X X L X H H L X L-H D

Notes:

2. X = “Don't Care.” H = Logic HIGH, L =Logic LOW.

3. WRITE

4. The SRAM always initiates a Read cycle when ADSP

5. OE

= L when any one or more Byte Write Enable signals (BWA, BWB) and BWE = L or GW= L. WRITE = H when all Byte Write Enable signals (BWA, BWB),

BWE

, GW = H.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

after the ADSP
don't care for the remainder of the Write cycle

is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle all data bits are Tri-State when OE

is inactive or when the device is deselected, and all data bits behave as output when OE

Sleep mode standby current ZZ > VDD – 0.2V 40 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ Active to sleep current This parameter is sampled 2t

CYC

CYC

ns
ns
ns

ZZ Inactive to exit sleep current This parameter is sampled 0 ns

[2, 3, 4, 5]

ADDRESS

Used CE1CE2CE3ZZ ADSP ADSC ADV WE OE CLK DQ

None H X X L X L X X X L-H Tri-State

None L L X L L X X X X L-H Tri-State

None L X H L L X X X X L-H Tri-State

None L L X L H L X X X L-H Tri-State

None X X X L H L X X X L-H Tri-State

or with the assertion of ADSC. As a result, OE must be driven HI GH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a

is asserted, regardless of the state of GW , BWE, or BW

is active (LOW)

. Writes may occur only on subsequent clocks

[A: B]

Document #: 001-00208 Rev. *B Page 5 of 15

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