Cypress CY7C1917CV18, CY7C1319CV18, CY7C1317CV18, CY7C1321CV18 User Manual

18-Mbit DDR-II SRAM 4-Word

Burst Architecture

CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18

Features

Functional Description

■ 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

■ 300 MHz clock for high bandwidth

■ 4-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) at 300 MHz

■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Synchronous internally self-timed writes

■ DDR-II operates with 1.5 cycle read latency when the DLL is

enabled

■ Operates similar to a DDR-I device with 1 cycle read latency in

DLL off mode

■ 1.8V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4V–V

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

)

The CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and CY7C1321CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a two-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K driven on the rising edges of C and C edge of K and K is associated with four 8-bit words in the case of CY7C1317CV18 and four 9-bit words in the case of CY7C1917CV18 that burst sequentially into or out of the device. The burst counter always starts with a ‘00’ internally in the case of CY7C1317CV18 and CY7C1917CV18. For CY7C1319CV18 and CY7C1321CV18, the burst counter takes in the least two significant bits of the external address and bursts four 18-bit words in the case of CY7C1319CV18, and four 36-bit words in the case of CY7C1321CV18, sequentially into or out of the device.

Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs, D) are tightly matched to the two output echo clocks CQ/CQ separately from each individual DDR SRAM in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by the K or K registers controlled by the C or C domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

if C/C are not provided. Each address location

, eliminating the need to capture data

input clocks. All data outputs pass through output

if provided, or on the rising

(or K or K in a single clock

. Read data is

Configurations

CY7C1317CV18 – 2M x 8 CY7C1917CV18 – 2M x 9 CY7C1319CV18 – 1M x 18 CY7C1321CV18 – 512K x 36

Selection Guide

Description 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 300 278 250 200 167 MHz Maximum Operating Current x8 770 720 670 580 515 mA

x9 770 720 670 580 515 x18 810 760 700 600 540 x36 890 830 765 655 600

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-07161 Rev. *D Revised June 18, 2008

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CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18

Logic Block Diagram (CY7C1317CV18)

Write

Reg

CLK

(18:0)

Gen.

Control

Logic

Address

Read Add. Decode

Read Data Reg.

R/W

[7:0]

Output

Logic

Reg.

NWS

[1:0]

REF

Write Add. Decode

Control

CQ CQ

R/W

DOFF

512K x 8 Array

Write

Reg

Write

Reg

Write

Reg

512K x 8 Array

Write

Reg

CLK

(18:0)

Gen.

Control

Logic

Address Register

Read Add. Decode

Read Data Reg.

R/W

Output

Logic

Reg.

BWS

[0]

REF

Write Add. Decode

Control

R/W

DOFF

512K x 9 Array

Write

Reg

Write

Reg

Write

Reg

512K x 9 Array

[8:0]

CQ CQ

Logic Block Diagram (CY7C1917CV18)

Document Number: 001-07161 Rev. *D Page 2 of 31

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Logic Block Diagram (CY7C1319CV18)

Write

Reg

CLK

(19:0)

Gen.

Control

Logic

Address

Read Add. Decode

Read Data Reg.

R/W

Output

Logic

Reg.

BWS

[1:0]

REF

Write Add. Decode

Control

R/W

DOFF

256K x 18 Array

Write

Reg

Write

Reg

Write

Reg

256K x 18 Array

Burst Logic

(1:0)

(19:2)

[17:0]

CQ CQ

Write

Reg

CLK

(18:0)

Gen.

Control

Logic

Address Register

Read Add. Decode

Read Data Reg.

R/W

Output

Logic

Reg.

144

BWS

[3:0]

REF

Write Add. Decode

Control

R/W

DOFF

128K x 36 Array

Write

Reg

Write

Reg

Write

Reg

128K x 36 Array

Burst Logic

(1:0)

(18:2)

[35:0]

CQ CQ

Logic Block Diagram (CY7C1321CV18)

Document Number: 001-07161 Rev. *D Page 3 of 31

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Pin Configuration

Note

1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.

The pin configuration for CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and CY7C1321CV18 follow.

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1317CV18 (2M x 8)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/72M A R/W NWS

B NC NC NC A NC/288M K NWS C NC NC NC V D NC NC NC V E NC NC DQ4 V F NC NC NC V G NC NC DQ5 V H DOFF V

REF

DDQ

J NC NC NC V K NC NC NC V

L NC DQ6 NC V M NC NC NC V N NC NC NC V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

ANCAVSSNC NC NC

AAAVSSNC NC NC

P NC NC DQ7 A A C A A NC NC NC

R TDO TCK A A A C AAATMSTDI

K NC/144M LD A NC/36M CQ

ANCNCDQ3

DDQ

[1]

NC NC NC NC NC DQ2 NC NC NC NC NC NC

DDQ

REF

NC DQ1 NC NC NC NC NC NC DQ0 NC NC NC

CY7C1917CV18 (2M x 9)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/72M A R/W NC K NC/144M LD A NC/36M CQ B NC NC NC A NC/288M K BWS C NC NC NC V D NC NC NC V

E NC NC DQ4 V

F NC NC NC V G NC NC DQ5 V H DOFF V

REF

DDQ

J NC NC NC V K NC NC NC V

L NC DQ6 NC V M NC NC NC V N NC NC NC V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

ANCAVSSNC NC NC

AAAVSSNC NC NC

ANCNCDQ3

V V V V V V V

DDQ DDQ DDQ DDQ DDQ DDQ DDQ

NC NC NC NC NC DQ2 NC NC NC NC NC NC

DDQ

REF

NC DQ1 NC NC NC NC NC NC DQ0 NC NC NC

P NC NC DQ7 A A C A A NC NC DQ8

R TDO TCK A A A C AAATMSTDI

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CY7C1317CV18, CY7C1917CV18 CY7C1319CV18, CY7C1321CV18

Pin Configuration (continued)

The pin configuration for CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and CY7C1321CV18 follow.

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1319CV18 (1M x 18)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/72M A R/W BWS

B NC DQ9 NC A NC/288M K BWS C NC NC NC V D NC NC DQ10 V

E NC NC DQ11 V

F NC DQ12 NC V G NC NC DQ13 V H DOFF V

REF

DDQ

J NC NC NC V K NC NC DQ14 V

L NC DQ15 NC V M NC NC NC V N NC NC DQ16 V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

AA0A1VSSNC DQ7 NC

AAAVSSNC NC NC

P NC NC DQ17 A A C A A NC NC DQ0

R TDO TCK A A A C AAATMSTDI

K NC/144M LD A NC/36M CQ

ANCNCDQ8

DDQ

[1]

NC NC NC NC NC DQ6 NC NC DQ5 NC NC NC

DDQ

REF

NC DQ4 NC NC NC DQ3 NC NC DQ2 NC DQ1 NC

CY7C1321CV18 (512K x 36)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/144M NC/36M R/W BWS B NC DQ27 DQ18 A BWS C NC NC DQ28 V D NC DQ29 DQ19 V

E NC NC DQ20 V

F NC DQ30 DQ21 V G NC DQ31 DQ22 V H DOFF V

REF

DDQ

J NC NC DQ32 V K NC NC DQ23 V

L NC DQ33 DQ24 V M NC NC DQ34 V N NC DQ35 DQ25 V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

AA0A1VSSNC DQ17 DQ7

AAAVSSNC NC DQ10

2 3

K BWS

LD A NC/72M CQ

KBWS0ANCNCDQ8

V V V V V V V

DDQ DDQ DDQ DDQ DDQ DDQ DDQ

NC NC DQ16 NC DQ15 DQ6 NC NC DQ5 NC NC DQ14

DDQ

REF

ZQ NC DQ13 DQ4 NC DQ12 DQ3 NC NC DQ2 NC DQ11 DQ1

P NC NC DQ26 A A C A A NC DQ9 DQ0

R TDO TCK A A A C AAATMSTDI

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Pin Definitions

Pin Name IO Pin Description

[x:0]

LD Input-

NWS0, NWS

BWS BWS BWS BWS

A, A0, A1 Input-

R/W

C Input Clock Positive Input Clock for Output Data. C is used in conjunction with C

K Input Clock Positive Input Clock In put. The rising edge of K is used to capture synchronous inputs to the device

2 3

Input OutputSynchronous

Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write operations. These pins drive out the requested data during a read operation. Valid data is driven out on the rising edge of both the C and C When read access is deselected, Q CY7C1317CV18 − DQ CY7C1917CV18 − DQ CY7C1319CV18 − DQ CY7C1321CV18 − DQ

[7:0] [8:0] [17:0] [35:0]

clocks during read operations or K and K when in single clock mode.

are automatically tri-stated.

[x:0]

Synchronous Load. This input is brought LOW when a bus cycle sequence is defined. This definition

Synchronous

includes address and read/write direction. All transactions operate on a burst of 4 data (two clock periods of bus activity).

Input-

Synchronous

Nibble Write Select 0, 1 − Active LOW (CY7C1317CV18 only). Sampled on the rising edge of the K and K

clocks during write operations. Used to select which nibble is written into the device during the current portion of the write operations. Nibbles not written remain unaltered. NWS0 controls D

and NWS1 controls D

[3:0]

[7:4]

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select ignores the corresponding nibble of data and it is not written into the device.

Input-

Synchronous

Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks during write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered. CY7C1917CV18 − BWS CY7C1319CV18 − BWS0 controls D CY7C1321CV18 − BWS0 controls D D

[35:27]

controls D

[8:0]

and BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

[17:9].

, BWS2 controls D

[17:9]

and BWS3 controls

[26:18]

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select ignores the corresponding byte of data and it is not written into the device.

Address Inputs. These address inputs are multiplexed for both read and write operations. Internally, the

Synchronous

device is organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1317CV18 and 2M x 9 (4 arrays each of 512K x 9) for CY7C1917CV18, 1M x 18 (4 arrays each of 256K x 18) for CY7C1319CV18, and 512K x 36 (4 arrays each of 128K x 36) for CY7C1321CV18.

CY7C1317CV18 – Because the least two significant bits of the address internally are “00”, only 19 external address inputs are needed to access the entire memory array.

CY7C1917CV18 – Because the least two significant bits of the address internally are “00”, only 19 external address inputs are needed to access the entire memory array.

CY7C1319CV18 – A0 and A1 are the inputs to the burst counter. These are incremented internally in a linear fashion. 20 address inputs are needed to access the entire memory array.

CY7C1321CV18 – A0 and A1 are the inputs to the burst counter. These are incremented internally in a linear fashion. 19 address inputs are needed to access the entire memory array.

Input-

Synchronous

Synchronous Read/Write Input. When LD is LOW, this input designates the access type (read when R/W

is HIGH, write when R/W is LOW) for the loaded address. R/W must meet the setup and hold times

around the edge of K.

to clock out the read data from

the device. C and C

can be used together to deskew the flight times of various devices on the board back

to the controller. See Application Example on page 10 for more information.

Input Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from

the device. C and C

can be used together to deskew the flight times of various devices on the board back

to the controller. See Application Example on page 10 for more information.

and to drive out data through Q edge of K.

when in single clock mode. All accesses are initiated on the rising

[x:0]

Input Clock Negative Input Clock Input. K is used to capture synchronous data being presented to the device and

to drive out data through Q

when in single clock mode.

[x:0]

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Pin Definitions (continued)

Pin Name IO Pin Description

CQ Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock

for output data (C) of the DDR-II. In single clock mode, CQ is generated with respect to K. The timing for the echo clocks is shown in Switching Characteristics on page 24.

ZQ Input Output Impedance Matching Inpu t. This input is used to tune the device outputs to the system data bus

DOFF

TDO Output TDO for JTAG. TCK Input TCK Pin for JTAG. TDI Input TDI Pin for JTAG. TMS Input TMS Pin for JTAG. NC N/A Not Connected to the Die. Can be tied to any voltage level. NC/36M N/A Not Connected to the Die. Can be tied to any voltage level. NC/72M N/A Not Connected to the Die. Can be tied to any voltage level. NC/144M N/A Not Connected to the Die. Can be tied to any voltage level. NC/288M N/A Not Connected to the Die. Can be tied to any voltage level. V

REF

DDQ

Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock

Input DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing

Input-

Reference

Power Supply Power Supply Inputs to the Core of the Device.

Ground Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

for output data (C the echo clocks is shown in Switching Characteristics on page 24.

impedance. CQ, CQ, and Q between ZQ and ground. Alternatively, this pin can be connected directly to V minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

in the DLL turned off operation is different from that listed in this data sheet. For normal operation, this pin can be connected to a pull up through a 10 Kohm or less pull up resistor. The device behaves in DDR-I mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with DDR-I timing.

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC measurement points.

) of the DDR-II. In single clock mode, CQ is generated with respect to K. The timing for

output impedance are set to 0.2 x RQ, where RQ is a resistor connected

[x:0]

, which enables the

DDQ

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Functional Overview

The CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and CY7C1321CV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of one and half cycles when DOFF When DOFF

pin is set LOW or connected to VSS the device

behaves in DDR-I mode with a read latency of one clock cycle. Accesses are initiated on the rising edge of the positive input

clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K referenced to the rising edge of the output clocks (C/C when in single clock mode).

All synchronous data inputs (D controlled by the rising edge of the input clocks (K and K synchronous data outputs (Q controlled by the rising edge of the output clocks (C/C

) pass through input registers

[x:0]

) pass through output registers

[x:0]

when in single-clock mode). All synchronous control (R/W, LD, BWS

input registers controlled by the rising edge of the input clock (K). CY7C1319CV18 is described in the following sections. The

same basic descriptions apply to CY7C1317CV18, CY7C1917CV18, and CY7C1321CV18.

Read Operations

The CY7C1319CV18 is organized internally as four arrays of 256K x 18. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting R/W

HIGH and LD LOW at the rising edge of the positive input clock (K). The address presented to address inputs is stored in the read address register and the least two significant bits of the address are presented to the burst counter. The burst counter increments the address in a linear fashion. Following the next K clock rise, the corresponding 18-bit word of data from this address location is driven onto Q timing reference. On the subsequent rising edge of C the next 18-bit data word from the address location generated by the burst counter is driven onto Q all four 18-bit data words have been driven out onto Q requested data is valid 0.45 ns from the rising edge of the output clock (C or C

, or K and K when in single clock mode, for 200 MHz and 250 MHz device). To maintain the internal logic, each read access must be allowed to complete. Each Read access consists of four 18-bit data words and takes two clock cycles to complete. Therefore, Read accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device ignores the second read request. Read accesses can be initiated on every other K clock rise. Doing so pipelines the data flow such that data is transferred out of the device on every rising edge of the output clocks (C/C mode).

The CY7C1319CV18 first completes the pending read transactions, when read access is deselected. Synchronous internal circuitry automatically tri-states the output following the next rising edge of the positive output clock (C). This enables a seamless transition between devices without the insertion of wait states in a depth expanded memory.

[17:0]

. This process continues until

[17:0]

or K/K when in single-clock

pin is tied HIGH.

) and all output timing is

, or K/K

). All

, or K/K

) inputs pass through

[0:X]

, using C as the output

The

[17:0].

Write Operations

Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock (K). The address presented to address inputs is stored in the write address register and the least two significant bits of the address are presented to the burst counter. The burst counter increments the address in a linear fashion. On the following K clock rise the data presented to D write data register, provided BWS On the subsequent rising edge of the negative input clock (K information presented to D register, provided BWS process continues for one more cycle until four 18-bit words (a

is latched and stored into the 18-bit

[17:0]

are both asserted active. This

[1:0]

are both asserted active.

[1:0]

is also stored into the write data

) the

total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, Write accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device ignores the second write request. Write accesses can be initiated on every other rising edge of the positive input clock (K). Doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K

When Write access is deselected, the device ignores all inputs after the pending write operations are completed.

Byte Write Operations

Byte write operations are supported by the CY7C1 319CV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS

, which are sampled with each set of 18-bit data words.

BWS

Asserting the appropriate Byte Write Select input during the data

and

portion of a write latches the data being presented and writes it into the device. Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read/modify/write operations to a byte write operation.

Single Clock Mode

The CY7C1319CV18 can be used with a single clock that controls both the input and output registers. In this mode the device recognizes only a single pair of input clocks (K and K

) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K in this mode. T o use this mode of operation, tie C and C

and C/C clocks. All timing parameters remain the same

HIGH at power on. This function is a strap option and not alterable during device operation.

DDR Operation

The CY7C1319CV18 enables high-performance operation through high clock frequencies (achieved through pipelining) and double data rate mode of operation. The CY7C1319CV18 requires a single No Operation (NOP) cycle when transitioning from a read to a write cycle. At higher frequencies, some applications may require a second NOP cycle to avoid contention.

If a read occurs after a write cycle, address and data for the write are stored in registers. The write information must be stored because the SRAM cannot perform the last word write to the array without conflicting with the read. The data stays in this register until the next write cycle occurs. On the first write cycle

Document Number: 001-07161 Rev. *D Page 8 of 31

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after the read(s), the stored data from the earlier write is written into the SRAM array. This is called a posted write.

If a read is performed on the same address on which a write is performed in the previous cycle, the SRAM reads out the most current data. The SRAM does this by bypassing the memory array and reading the data from the regi ste r s.

Depth Expansion

Depth expansion requires replicating the LD control signal for each bank. All other control signals can be commo n between banks as appropriate.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω output impedance is adjusted every 1024 cycles at power up to account for drifts in supply voltage and temperature.

to enable the SRAM to adjust its output

, with V

=1.5V. The

DDQ

Echo Clocks

Echo clocks are provided on the DDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the DDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C nized to the output clock of the DDR-II. In the single clock mode, CQ is generated with respect to K and CQ respect to K

Characteristics on page 24.

. These are free running clocks and are synchro-

is generated with

. The timing for the echo clocks is shown in Switching

DLL

These chips use a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the DLL is locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary to reset the DLL to lock to the desired frequency. The DLL automatically locks 1024 clock cycles after a stable clock is presented. The DLL may be disabled by applying ground to the DOFF is turned off, the device behaves in DDR-I mode (with one cycle latency and a longer access time). For information refer to the application note DLL Considerations in QDRII™/DDRII.

pin. When the DLL

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Application Example

Vterm = 0.75V

R = 50ohms

R = 250ohms

LD# C C#R/W#

DQ A

LD# C C#R/W#

DQ A

SRAM#1

SRAM#2

R = 250ohms

BUS

MASTER

(CPU

ASIC)

Addresses

Cycle Start#

R/W# Return CLK Source CLK

Return CLK#

Source CLK# Echo Clock1/Echo Clock#1 Echo Clock2/Echo Clock#2

CQ/CQ#

Notes

2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑

represents rising edge.

3. Device powers up deselected with the outputs in a tri-state condition.

4. On CY7C1319CV18 and CY7C1321CV18, “A1” represents address loca tion latched b y the devices when tran saction was init iated and “A 2”, “A3”, “A4” r epresent s the addresses sequence in the burst. On CY7C1317CV18 and CY7C1917CV18, “A1” represents A + ‘00’ and “A2” represents A + ‘01’, “A3” represents A + ‘10’ and “A4” represents A + ‘11’.

5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.

6. Data inputs are registered at K and K

rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7. It is recommended that K = K

and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging

symmetrically.

Figure 1 shows two DDR-II used in an application.

Figure 1. Application Example

Truth Table

[2, 3, 4, 5, 6, 7]

The truth table for the CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and CY7C1321CV18 follows .

Operation K LD R/W DQ DQ DQ DQ

Write Cycle:

L-H L L D(A1) at K(t + 1)↑ D(A2) at K

(t + 1)↑ D(A3) at K(t + 2)↑ D(A4) at K(t + 2)↑ Load address; wait one cycle; input write data on four consecutive K and K

rising edges.

Read Cycle:

L-H L H Q(A1) at C(t + 1)↑ Q(A2) at C(t + 2)↑ Q(A3) at C(t + 2)↑ Q(A4) at C(t + 3)↑ Load address; wait one and a half cycle; read data on four consecutive C

and C

rising edges. NOP: No Operation L-H H X High-Z High-Z High-Z High-Z Standby: Clock Stopped Stopped X X Previous State Previous State Previous State Previous State

Document Number: 001-07161 Rev. *D Page 10 of 31

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Cypress CY7C1917CV18, CY7C1319CV18, CY7C1317CV18, CY7C1321CV18 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Functional Description

Configurations

Selection Guide

Logic Block Diagram (CY7C1317CV18)

Logic Block Diagram (CY7C1917CV18)

Logic Block Diagram (CY7C1319CV18)

Logic Block Diagram (CY7C1321CV18)

Pin Configuration

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

Pin Definitions

Functional Overview

Read Operations

Write Operations

Byte Write Operations

Single Clock Mode

DDR Operation

Depth Expansion

Programmable Impedance

Echo Clocks

Application Example

Truth Table