Cypress CY7C1320CV18-250BZXC, 001-07160, CY7C1318CV18-200BZI, CY7C1320CV18-200BZC, CY7C1320CV18-167BZC User Manual

18-Mbit DDR II SRAM 2-Word

Burst Architecture

CY7C1318CV18
CY7C1320CV18

Features

Functional Description

■ 18-Mbit Density (1M x 18, 512K x 36)

■ 267 MHz Clock for high Bandwidth

■ 2-word Burst for reducing Address Bus Frequency

■ Double Data Rate (DDR) Interfaces

(data transferred at 534 MHz) at 267 MHz

■ Two Input Clocks (K and K) for precise DDR Timing
❐ SRAM uses rising edges only

■ Two Input Clocks for Output Data (C and C) to minimize Clock

Skew and Flight Time mismatches

■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed

Systems

■ Synchronous internally Self-timed Writes

■ DDR II operates with 1.5 Cycle Read Latency when the DLL is

enabled

■ Operates similar to a DDR I Device with one Cycle Read

Latency in DLL Off Mode

■ 1.8V Core Power Supply with HSTL Inputs and Outputs

■ Variable drive HSTL Output Buffers

■ Expanded HSTL Output Voltage (1.4V–V

■ Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free Packages

■ JTAG 1149.1 compatible Test Access Port

■ Delay Lock Loop (DLL) for accurate Data Placement

DD

)

The CY7C1318CV18, and CY7C1320CV18 are 1.8V
Synchronous Pipelined SRAMs equipped with DDR II archi­tecture. The DDR II consists of an SRAM core with advanced
synchronous peripheral circuitry and a one-bit burst counter.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K
of C and C
not provided. For CY7C1318CV18 and CY7C1320CV18, the
burst counter takes in the least significant bit of the external
address and bursts two 18-bit words (in the case of
CY7C1318CV18) of two 36-bit words (in the case of
CY7C1320CV18) sequentially into or out of the device.

Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the two
output echo clocks CQ/CQ
separately from each individual DDR SRAM in the system
design. Output data clocks (C/C
clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by
the K or K
registers controlled by the C or C
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.

if provided, or on the rising edge of K and K if C/C are

input clocks. All data outputs pass through output

. Read data is driven on the rising edges

, eliminating the need to capture data

) enable maximum system

(or K or K in a single clock

Configurations

CY7C1318CV18 – 1M x 18

CY7C1320CV18 – 512K x 36

Selection Guide

Description 267 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 267 250 200 167 MHz

Maximum Operating Current x18 805 730 600 510 mA

x36 855 775 635 540

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-07160 Rev. *F Revised August 24, 2009

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CY7C1318CV18
CY7C1320CV18

Logic Block Diagram (CY7C1318CV18)

Write
Reg

Write
Reg

CLK

A

(19:0)

Gen.

K

K

Control

Logic

Address

Register

Read Add. Decode

Read Data Reg.

R/W

Output

Logic

Reg.

Reg.

Reg.

18

36

18

BWS

[1:0]

V

REF

Write Add. Decode

18

20

C

C

18

LD

Control

Burst

Logic

A0

A

(19:1)

R/W

DOFF

512K x 18 Array

512K x 18 Array

19

18

DQ

[17:0]

18

CQ

CQ

Write
Reg

Write
Reg

CLK

A

(18:0)

Gen.

K

K

Control

Logic

Address

Register

Read Add. Decode

Read Data Reg.

R/W

Output

Logic

Reg.

Reg.

Reg.

36

72

36

BWS

[3:0]

V

REF

Write Add. Decode

36

19

C

C

36

LD

Control

Burst
Logic

A0

A

(18:1)

R/W

DOFF

256K x 36 Array

256K x 36 Array

18

36

DQ

[35:0]

36

CQ

CQ

Logic Block Diagram (CY7C1320CV18)

Document Number: 001-07160 Rev. *F Page 2 of 26

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CY7C1318CV18
CY7C1320CV18

Pin Configuration

Note

1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.

The pin configuration for CY7C1318CV18 and CY7C1320CV18 follow.

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1318CV18 (1M x 18)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/72M A R/W BWS

B NC DQ9 NC A NC/288M K BWS

C NC NC NC V

D NC NC DQ10 V

E NC NC DQ11 V

F NC DQ12 NC V

G NC NC DQ13 V

H DOFF V

REF

V

DDQ

J NC NC NC V

K NC NC DQ14 V

L NC DQ15 NC V

M NC NC NC V

N NC NC DQ16 V

V

SS

SS

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

SS

SS

P NC NC DQ17 A A C A A NC NC DQ0

R TDO TCK A A A C AAATMSTDI

1

AA0AVSSNC DQ7 NC

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

AAAVSSNC NC NC

[1]

K NC/144M LD A NC/36M CQ

0

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

ANCNCDQ8

V

V

V

V

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

V

SS

SS

NC NC NC

NC NC DQ6

NC NC DQ5

NC NC NC

V

DDQ

V

REF

NC DQ4 NC

NC NC DQ3

NC NC DQ2

NC DQ1 NC

ZQ

CY7C1320CV18 (512K x 36)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/144M NC/36M R/W BWS

B NC DQ27 DQ18 A BWS

C NC NC DQ28 V

D NC DQ29 DQ19 V

E NC NC DQ20 V

F NC DQ30 DQ21 V

G NC DQ31 DQ22 V

H DOFF V

REF

V

DDQ

V

J NC NC DQ32 V

K NC NC DQ23 V

L NC DQ33 DQ24 V

M NC NC DQ34 V

N NC DQ35 DQ25 V

SS

SS

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

SS

SS

AA0AVSSNC DQ17 DQ7

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

AAAVSSNC NC DQ10

2

3

K BWS

LD A NC/72M CQ

1

KBWS0ANCNCDQ8

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

V

V

V

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

V

SS

SS

NC NC DQ16

NC DQ15 DQ6

NC NC DQ5

NC NC DQ14

V

DDQ

V

REF

ZQ

NC DQ13 DQ4

NC DQ12 DQ3

NC NC DQ2

NC DQ11 DQ1

P NC NC DQ26 A A C A A NC DQ9 DQ0

R TDO TCK A A A C AAATMSTDI

Document Number: 001-07160 Rev. *F Page 3 of 26

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CY7C1318CV18
CY7C1320CV18

Pin Definitions

Pin Name I/O Pin Description

DQ

[x:0]

LD Input-

BWS
BWS
BWS
BWS

A, A0 Input-

R/W

C Input Clock Positive Input Clock for Output Data. C is used in conjunction with C

C

K Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device

K

CQ Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock

CQ

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

Input Output­Synchronous

Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write
operations. These pins drive out the requested data during a read operation. Valid data is driven out on
the rising edge of both the C and C
When read access is deselected, Q
CY7C1318CV18 − DQ
CY7C1320CV18 − DQ

[17:0]
[35:0]

clocks during read operations or K and K when in single clock mode.

are automatically tristated.

[x:0]

Synchronous Load. This input is brought LOW when a bus cycle sequence is defined. This definition

,

0

,

1

,

2
3

Synchronous

Input-

Synchronous

includes address and read/write direction. All transactions operate on a burst of 2 data.
Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks during

write operations. Used to select which byte is written into the device during the current portion of the Write
operations. Bytes not written remain unaltered.
CY7C1318CV18 − BWS
CY7C1320CV18 − BWS0 controls D

.

D

[35:27]

controls D

0

and BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

[17:9].

, BWS2 controls D

[17:9]

and BWS3 controls

[26:18]

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.

Address Inputs. These address inputs are multiplexed for both read and write operations. Internally, the

Synchronous

device is organized as 1M x 18 (2 arrays each of 512K x 18) for CY7C1318CV18, and 512K x 36 (2 arrays
each of 256K x 36) for CY7C1320CV18.

CY7C1318CV18 – A0 is the input to the burst counter. These are incremented internally in a linear fashion.
20 address inputs are needed to access the entire memory array.

CY7C1320CV18 – A0 is the input to the burst counter. These are incremented internally in a linear fashion.
19 address inputs are needed to access the entire memory array. All the address inputs are ignored when
the appropriate port is deselected.

Input-

Synchronous

Synchronous Read/Write Input. When LD is LOW, this input designates the access type (read when

is HIGH, write when R/W is LOW) for the loaded address. R/W must meet the setup and hold times

R/W
around the edge of K.

to clock out the read data from

the device. C and C

can be used together to deskew the flight times of various devices on the board back

to the controller. See Application Example on page 7 for more information.

Input Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from

the device. C and C

can be used together to deskew the flight times of various devices on the board back

to the controller. See Application Example on page 7 for more information.

and to drive out data through Q
edge of K.

when in single clock mode. All accesses are initiated on the rising

[x:0]

Input Clock Negative Input Clock Input. K is used to capture synchronous data being presented to the device and

to drive out data through Q

when in single clock mode.

[x:0]

for output data (C) of the DDR II. In single clock mode, CQ is generated with respect to K. The timing for
the echo clocks is shown in Switching Characteristics on page 20.

Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock

for output data (C

) of the DDR II. In single clock mode, CQ is generated with respect to K. The timing for

the echo clocks is shown in Switching Characteristics on page 20.

impedance. CQ, CQ
between ZQ and ground. Alternatively, this pin can be connected directly to V
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

, and Q

output impedance are set to 0.2 x RQ, where RQ is a resistor connected

[x:0]

, which enables the

DDQ

Document Number: 001-07160 Rev. *F Page 4 of 26

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CY7C1318CV18
CY7C1320CV18

Pin Definitions (continued)

Pin Name I/O Pin Description

DOFF

TDO Output TDO for JTAG.

TCK Input TCK Pin for JTAG.

TDI Input TDI Pin for JTAG.

TMS Input TMS Pin for JTAG.

NC N/A Not Connected to the Die. Can be tied to any voltage level.

NC/36M N/A Not Connected to the Die. Can be tied to any voltage level.

NC/72M N/A Not Connected to the Die. Can be tied to any voltage level.

NC/144M N/A Not Connected to the Die. Can be tied to any voltage level.

NC/288M N/A Not Connected to the Die. Can be tied to any voltage level.

V

REF

V

DD

V

SS

V

DDQ

Input DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing

in the DLL turned off operation is different from that listed in this data sheet. For normal operation, this
pin can be connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in DDR I
mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167
MHz with DDR I timing.

Input-

Reference

Power Supply Power Supply Inputs to the Core of the Device.

Ground Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.

Document Number: 001-07160 Rev. *F Page 5 of 26

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CY7C1318CV18
CY7C1320CV18

Functional Overview

The CY7C1318CV18, and CY7C1320CV18 are synchronous
pipelined Burst SRAMs equipped with a DDR interface, which
operates with a read latency of one and half cycles when DOFF
pin is tied HIGH. When DOFF pin is set LOW or connected to
V

the device behaves in DDR I mode with a read latency of

SS

one clock cycle.

Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K
referenced to the rising edge of the output clocks (C/C
when in single clock mode).

All synchronous data inputs (D
controlled by the rising edge of the input clocks (K and K
synchronous data outputs (Q
controlled by the rising edge of the output clocks (C/C

[x:0]

[x:0]

when in single-clock mode).

All synchronous control (R/W, LD, BWS
input registers controlled by the rising edge of the input clock (K).

CY7C1318CV18 is described in the following sections. The
same basic descriptions apply to CY7C1320CV18.

Read Operations

The CY7C1318CV18 is organized internally as two arrays of
512K x 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
R/W

HIGH and LD LOW at the rising edge of the positive input
clock (K). The address presented to address inputs is stored in
the read address register and the least significant bit of the
address is presented to the burst counter. The burst counter
increments the address in a linear fashion. Following the next K
clock rise, the corresponding 18-bit word of data from this
address location is driven onto Q
timing reference. On the subsequent rising edge of C the next
18-bit data word from the address location generated by the
burst counter is driven onto Q

0.45 ns from the rising edge of the output clock (C or C
K

when in single clock mode, 200 MHz and 250 MHz device). To

[17:0]

maintain the internal logic, each read access must be allowed to
complete. Read accesses can be initiated on every rising edge
of the positive input clock (K).

The CY7C1318CV18 first completes the pending read transac­tions, when read access is deselected. Synchronous internal
circuitry automatically tristates the output following the next rising
edge of the positive output clock (C). This enables a seamless
transition between devices without the insertion of wait states in
a depth expanded memory.

Write Operations

Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the write
address register and the least significant bit of the address is
presented to the burst counter. The burst counter increments the
address in a linear fashion. On the following K clock rise the data
presented to D
data register, provided BWS

is latched and stored into the 18-bit write

[17:0]

are both asserted active. On the

[1:0]

) and all output timing is

, or K/K

) pass through input registers

). All

) pass through output registers

, or K/K

) inputs pass through

[0:X]

, using C as the output

[17:0]

. The requested data is valid

, or K and

subsequent rising edge of the negative input clock (K
mation presented to D
register, provided BWS
of data are then written into the memory array at the specified

is also stored into the write data

[17:0]

are both asserted active. The 36 bits

[1:0]

) the infor-

location. Write accesses can be initiated on every rising edge of
the positive input clock (K). This pipelines the data flow such that
18 bits of data can be transferred into the device on every rising
edge of the input clocks (K and K

).

When Write access is deselected, the device ignores all inputs
after the pending write operations are completed.

Byte Write Operations

Byte write operations are supported by the CY7C1318CV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS

, which are sampled with each set of 18-bit data words.

1

Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify read/modify/write operations to a byte write operation.

Single Clock Mode

The CY7C1318CV18 can be used with a single clock that
controls both the input and output registers. In this mode the
device recognizes only a single pair of input clocks (K and K) that
control both the input and output registers. This operation is
identical to the operation if the device had zero skew between
the K/K

and C/C clocks. All timing parameters remain the same

in this mode. To use this mode of operation, tie C and C

HIGH at
power on. This function is a strap option and not alterable during
device operation.

DDR Operation

The CY7C1318CV18 enables high-performance operation
through high clock frequencies (achieved through pipelining) and
double data rate mode of operation. The CY7C1318CV18
requires a single No Operation (NOP) cycle when transitioning
from a read to a write cycle. At higher frequencies, some appli­cations may require a second NOP cycle to avoid contention.

If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information must be stored
because the SRAM cannot perform the last word write to the
array without conflicting with the read. The data stays in this
register until the next write cycle occurs. On the first write cycle
after the read(s), the stored data from the earlier write is written
into the SRAM array. This is called a posted write.

If a read is performed on the same address on which a write is
performed in the previous cycle, the SRAM reads out the most
current data. The SRAM does this by bypassing the memory
array and reading the data from the registers.

Depth Expansion

Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.

Document Number: 001-07160 Rev. *F Page 6 of 26

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CY7C1318CV18
CY7C1320CV18

Programmable Impedance

Vterm = 0.75V

Vterm = 0.75V

R = 50ohms

R = 250ohms

LD# C C#R/W#

DQ
A

K

LD# C C#R/W#

DQ
A

K

SRAM#1

SRAM#2

R = 250ohms

BUS

MASTER

(CPU

or

ASIC)

DQ

Addresses

Cycle Start#

R/W#
Return CLK
Source CLK

Return CLK#

Source CLK#
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2

ZQ

CQ/CQ#

K#

ZQ

CQ/CQ#

K#

An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω
output impedance is adjusted every 1024 cycles at power up to
account for drifts in supply voltage and temperature.

to enable the SRAM to adjust its output

SS

, with V

=1.5V. The

DDQ

Echo Clocks

Echo clocks are provided on the DDR II to simplify data capture
on high speed systems. Two echo clocks are generated by the
DDR II. CQ is referenced with respect to C and CQ is referenced
with respect to C

. These are free running clocks and are synchro­nized to the output clock of the DDR II. In the single clock mode,
CQ is generated with respect to K and CQ is generated with
respect to K

. The timing for the echo clocks is shown in Switching

Characteristics on page 20.

Application Example

Figure 1 shows two DDR II used in an application.

Figure 1. Application Example

DLL

These chips use a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. During power up, when the DOFF is tied HIGH, the
DLL is locked after 1024 cycles of stable clock. The DLL can also
be reset by slowing or stopping the input clocks K and K
minimum of 30 ns. However, it is not necessary to reset the DLL
to lock it to the desired frequency. The DLL automatically locks
1024 clock cycles after a stable clock is presented. The DLL may
be disabled by applying ground to the DOFF pin. When the DLL
is turned off, the device behaves in DDR I mode (with one cycle
latency and a longer access time). For information refer to the
application note DLL Considerations in QDRII™/DDRII.

for a

Document Number: 001-07160 Rev. *F Page 7 of 26

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CY7C1318CV18
CY7C1320CV18

Truth Table

Notes

2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑

represents rising edge.

3. Device powers up deselected with the outputs in a tristate condition.

4. On CY7C1318CV18 and CY7C1320CV18, “A1” represents address location latched by the devices when transaction was initiated and “A2” represents the addresses
sequence in the burst.

5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.

6. Data inputs are registered at K and K

rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7. It is recommended that K = K

and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging

symmetrically.

8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. BWS

0

, BWS1, BWS2, and BWS3 can be altered on different portions

of a write cycle, as long as the setup and hold requirements are achieved.

The truth table for the CY7C1318CV18, and CY7C1320CV18 follows.

Operation K LD R/W DQ DQ

Write Cycle:

L-H L L D(A1) at K(t + 1) ↑ D(A2) at K

Load address; wait one cycle;
input write data on consecutive K and K

Read Cycle:

rising edges.

L-H L H Q(A1) at C(t + 1)↑ Q(A2) at C(t + 2) ↑

Load address; wait one and a half cycle;
read data on consecutive C

and C rising edges.

NOP: No Operation L-H H X High-Z High-Z

Standby: Clock Stopped Stopped X X Previous State Previous State

[2, 3, 4, 5, 6, 7]

(t + 1) ↑

Burst Address Table

(CY7C1318CV18, CY7C1320CV18)

First Address (External) Second Address (Internal)

X..X0 X..X1

X..X1 X..X0

Write Cycle Descriptions

The write cycle description table for CY7C1318CV18 follows.

BWS0BWS1K

K

L L L–H – During the data portion of a write sequence :

Both bytes (D

) are written into the device.

[17:0]

L L – L-H During the data portion of a write sequence :

Both bytes (D

) are written into the device.

[17:0]

L H L–H – During the data portion of a write sequence :

Only the lower byte (D

[8:0]

L H – L–H During the data portion of a write sequence :

Only the lower byte (D

[8:0]

H L L–H – During the data portion of a write sequence :

Only the upper byte (D

[17:9]

H L – L–H During the data portion of a write sequence :

Only the upper byte (D

[17:9]

H H L–H – No data is written into the devices during this portion of a write operation.

H H – L–H No data is written into the devices during this portion of a write operation.

[2, 8]

Comments

) is written into the device, D

) is written into the device, D

) is written into the device, D

) is written into the device, D

remains unaltered.

[17:9]

remains unaltered.

[17:9]

remains unaltered.

[8:0]

remains unaltered.

[8:0]

Document Number: 001-07160 Rev. *F Page 8 of 26

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