Cypress CY7C1320CV18-250BZXC, 001-07160, CY7C1318CV18-200BZI, CY7C1320CV18-200BZC, CY7C1320CV18-167BZC User Manual

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18-Mbit DDR II SRAM 2-Word

Burst Architecture

CY7C1318CV18 CY7C1320CV18

Features

Functional Description

■ 18-Mbit Density (1M x 18, 512K x 36)

■ 267 MHz Clock for high Bandwidth

■ 2-word Burst for reducing Address Bus Frequency

■ Double Data Rate (DDR) Interfaces

(data transferred at 534 MHz) at 267 MHz

■ Two Input Clocks (K and K) for precise DDR Timing ❐ SRAM uses rising edges only

■ Two Input Clocks for Output Data (C and C) to minimize Clock

Skew and Flight Time mismatches

■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed

Systems

■ Synchronous internally Self-timed Writes

■ DDR II operates with 1.5 Cycle Read Latency when the DLL is

enabled

■ Operates similar to a DDR I Device with one Cycle Read

Latency in DLL Off Mode

■ 1.8V Core Power Supply with HSTL Inputs and Outputs

■ Variable drive HSTL Output Buffers

■ Expanded HSTL Output Voltage (1.4V–V

■ Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free Packages

■ JTAG 1149.1 compatible Test Access Port

■ Delay Lock Loop (DLL) for accurate Data Placement

)

The CY7C1318CV18, and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K of C and C not provided. For CY7C1318CV18 and CY7C1320CV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words (in the case of CY7C1318CV18) of two 36-bit words (in the case of CY7C1320CV18) sequentially into or out of the device.

Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs, D) are tightly matched to the two output echo clocks CQ/CQ separately from each individual DDR SRAM in the system design. Output data clocks (C/C clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by the K or K registers controlled by the C or C domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

if provided, or on the rising edge of K and K if C/C are

input clocks. All data outputs pass through output

. Read data is driven on the rising edges

, eliminating the need to capture data

) enable maximum system

(or K or K in a single clock

Configurations

CY7C1318CV18 – 1M x 18

CY7C1320CV18 – 512K x 36

Selection Guide

Description 267 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 267 250 200 167 MHz

Maximum Operating Current x18 805 730 600 510 mA

x36 855 775 635 540

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-07160 Rev. *F Revised August 24, 2009

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CY7C1318CV18 CY7C1320CV18

Logic Block Diagram (CY7C1318CV18)

Write Reg

CLK

(19:0)

Gen.

Control

Logic

Address

Read Add. Decode

Read Data Reg.

R/W

Output

Logic

Reg.

BWS

[1:0]

REF

Write Add. Decode

Control

Burst

Logic

(19:1)

R/W

DOFF

512K x 18 Array

[17:0]

Write Reg

CLK

(18:0)

Gen.

Control

Logic

Address

Read Add. Decode

Read Data Reg.

R/W

Output

Logic

Reg.

BWS

[3:0]

REF

Write Add. Decode

Control

Burst Logic

(18:1)

R/W

DOFF

256K x 36 Array

[35:0]

Logic Block Diagram (CY7C1320CV18)

Document Number: 001-07160 Rev. *F Page 2 of 26

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CY7C1318CV18 CY7C1320CV18

Pin Configuration

Note

1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.

The pin configuration for CY7C1318CV18 and CY7C1320CV18 follow.

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1318CV18 (1M x 18)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/72M A R/W BWS

B NC DQ9 NC A NC/288M K BWS

C NC NC NC V

D NC NC DQ10 V

E NC NC DQ11 V

F NC DQ12 NC V

G NC NC DQ13 V

H DOFF V

REF

DDQ

J NC NC NC V

K NC NC DQ14 V

L NC DQ15 NC V

M NC NC NC V

N NC NC DQ16 V

DDQ

P NC NC DQ17 A A C A A NC NC DQ0

R TDO TCK A A A C AAATMSTDI

AA0AVSSNC DQ7 NC

AAAVSSNC NC NC

[1]

K NC/144M LD A NC/36M CQ

ANCNCDQ8

DDQ

NC NC NC

NC NC DQ6

NC NC DQ5

NC NC NC

DDQ

REF

NC DQ4 NC

NC NC DQ3

NC NC DQ2

NC DQ1 NC

CY7C1320CV18 (512K x 36)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/144M NC/36M R/W BWS

B NC DQ27 DQ18 A BWS

C NC NC DQ28 V

D NC DQ29 DQ19 V

E NC NC DQ20 V

F NC DQ30 DQ21 V

G NC DQ31 DQ22 V

H DOFF V

REF

DDQ

J NC NC DQ32 V

K NC NC DQ23 V

L NC DQ33 DQ24 V

M NC NC DQ34 V

N NC DQ35 DQ25 V

DDQ

AA0AVSSNC DQ17 DQ7

AAAVSSNC NC DQ10

K BWS

LD A NC/72M CQ

KBWS0ANCNCDQ8

DDQ

NC NC DQ16

NC DQ15 DQ6

NC NC DQ5

NC NC DQ14

DDQ

REF

NC DQ13 DQ4

NC DQ12 DQ3

NC NC DQ2

NC DQ11 DQ1

P NC NC DQ26 A A C A A NC DQ9 DQ0

R TDO TCK A A A C AAATMSTDI

Document Number: 001-07160 Rev. *F Page 3 of 26

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CY7C1318CV18 CY7C1320CV18

Pin Definitions

Pin Name I/O Pin Description

[x:0]

LD Input-

BWS BWS BWS BWS

A, A0 Input-

R/W

C Input Clock Positive Input Clock for Output Data. C is used in conjunction with C

K Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device

CQ Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

Input OutputSynchronous

Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write operations. These pins drive out the requested data during a read operation. Valid data is driven out on the rising edge of both the C and C When read access is deselected, Q CY7C1318CV18 − DQ CY7C1320CV18 − DQ

[17:0] [35:0]

clocks during read operations or K and K when in single clock mode.

are automatically tristated.

[x:0]

Synchronous Load. This input is brought LOW when a bus cycle sequence is defined. This definition

2 3

Synchronous

Input-

Synchronous

includes address and read/write direction. All transactions operate on a burst of 2 data. Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks during

write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered. CY7C1318CV18 − BWS CY7C1320CV18 − BWS0 controls D

[35:27]

controls D

and BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

[17:9].

, BWS2 controls D

[17:9]

and BWS3 controls

[26:18]

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select ignores the corresponding byte of data and it is not written into the device.

Address Inputs. These address inputs are multiplexed for both read and write operations. Internally, the

Synchronous

device is organized as 1M x 18 (2 arrays each of 512K x 18) for CY7C1318CV18, and 512K x 36 (2 arrays each of 256K x 36) for CY7C1320CV18.

CY7C1318CV18 – A0 is the input to the burst counter. These are incremented internally in a linear fashion. 20 address inputs are needed to access the entire memory array.

CY7C1320CV18 – A0 is the input to the burst counter. These are incremented internally in a linear fashion. 19 address inputs are needed to access the entire memory array. All the address inputs are ignored when the appropriate port is deselected.

Input-

Synchronous

Synchronous Read/Write Input. When LD is LOW, this input designates the access type (read when

is HIGH, write when R/W is LOW) for the loaded address. R/W must meet the setup and hold times

R/W around the edge of K.

to clock out the read data from

the device. C and C

can be used together to deskew the flight times of various devices on the board back

to the controller. See Application Example on page 7 for more information.

Input Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from

the device. C and C

can be used together to deskew the flight times of various devices on the board back

to the controller. See Application Example on page 7 for more information.

and to drive out data through Q edge of K.

when in single clock mode. All accesses are initiated on the rising

[x:0]

Input Clock Negative Input Clock Input. K is used to capture synchronous data being presented to the device and

to drive out data through Q

when in single clock mode.

[x:0]

for output data (C) of the DDR II. In single clock mode, CQ is generated with respect to K. The timing for the echo clocks is shown in Switching Characteristics on page 20.

Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock

for output data (C

) of the DDR II. In single clock mode, CQ is generated with respect to K. The timing for

the echo clocks is shown in Switching Characteristics on page 20.

impedance. CQ, CQ between ZQ and ground. Alternatively, this pin can be connected directly to V minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

, and Q

output impedance are set to 0.2 x RQ, where RQ is a resistor connected

[x:0]

, which enables the

DDQ

Document Number: 001-07160 Rev. *F Page 4 of 26

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Pin Definitions (continued)

Pin Name I/O Pin Description

DOFF

TDO Output TDO for JTAG.

TCK Input TCK Pin for JTAG.

TDI Input TDI Pin for JTAG.

TMS Input TMS Pin for JTAG.

NC N/A Not Connected to the Die. Can be tied to any voltage level.

NC/36M N/A Not Connected to the Die. Can be tied to any voltage level.

NC/72M N/A Not Connected to the Die. Can be tied to any voltage level.

NC/144M N/A Not Connected to the Die. Can be tied to any voltage level.

NC/288M N/A Not Connected to the Die. Can be tied to any voltage level.

REF

DDQ

Input DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing

in the DLL turned off operation is different from that listed in this data sheet. For normal operation, this pin can be connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in DDR I mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with DDR I timing.

Input-

Reference

Power Supply Power Supply Inputs to the Core of the Device.

Ground Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC measurement points.

Document Number: 001-07160 Rev. *F Page 5 of 26

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CY7C1318CV18 CY7C1320CV18

Functional Overview

The CY7C1318CV18, and CY7C1320CV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of one and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to V

the device behaves in DDR I mode with a read latency of

one clock cycle.

Accesses are initiated on the rising edge of the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K referenced to the rising edge of the output clocks (C/C when in single clock mode).

All synchronous data inputs (D controlled by the rising edge of the input clocks (K and K synchronous data outputs (Q controlled by the rising edge of the output clocks (C/C

[x:0]

when in single-clock mode).

All synchronous control (R/W, LD, BWS input registers controlled by the rising edge of the input clock (K).

CY7C1318CV18 is described in the following sections. The same basic descriptions apply to CY7C1320CV18.

Read Operations

The CY7C1318CV18 is organized internally as two arrays of 512K x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting R/W

HIGH and LD LOW at the rising edge of the positive input clock (K). The address presented to address inputs is stored in the read address register and the least significant bit of the address is presented to the burst counter. The burst counter increments the address in a linear fashion. Following the next K clock rise, the corresponding 18-bit word of data from this address location is driven onto Q timing reference. On the subsequent rising edge of C the next 18-bit data word from the address location generated by the burst counter is driven onto Q

0.45 ns from the rising edge of the output clock (C or C K

when in single clock mode, 200 MHz and 250 MHz device). To

[17:0]

maintain the internal logic, each read access must be allowed to complete. Read accesses can be initiated on every rising edge of the positive input clock (K).

The CY7C1318CV18 first completes the pending read transactions, when read access is deselected. Synchronous internal circuitry automatically tristates the output following the next rising edge of the positive output clock (C). This enables a seamless transition between devices without the insertion of wait states in a depth expanded memory.

Write Operations

Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock (K). The address presented to address inputs is stored in the write address register and the least significant bit of the address is presented to the burst counter. The burst counter increments the address in a linear fashion. On the following K clock rise the data presented to D data register, provided BWS

is latched and stored into the 18-bit write

[17:0]

are both asserted active. On the

[1:0]

) and all output timing is

, or K/K

) pass through input registers

). All

) pass through output registers

, or K/K

) inputs pass through

[0:X]

, using C as the output

[17:0]

. The requested data is valid

, or K and

subsequent rising edge of the negative input clock (K mation presented to D register, provided BWS of data are then written into the memory array at the specified

is also stored into the write data

[17:0]

are both asserted active. The 36 bits

[1:0]

) the infor-

location. Write accesses can be initiated on every rising edge of the positive input clock (K). This pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K

When Write access is deselected, the device ignores all inputs after the pending write operations are completed.

Byte Write Operations

Byte write operations are supported by the CY7C1318CV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS0 and BWS

, which are sampled with each set of 18-bit data words.

Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read/modify/write operations to a byte write operation.

Single Clock Mode

The CY7C1318CV18 can be used with a single clock that controls both the input and output registers. In this mode the device recognizes only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K

and C/C clocks. All timing parameters remain the same

in this mode. To use this mode of operation, tie C and C

HIGH at power on. This function is a strap option and not alterable during device operation.

DDR Operation

The CY7C1318CV18 enables high-performance operation through high clock frequencies (achieved through pipelining) and double data rate mode of operation. The CY7C1318CV18 requires a single No Operation (NOP) cycle when transitioning from a read to a write cycle. At higher frequencies, some applications may require a second NOP cycle to avoid contention.

If a read occurs after a write cycle, address and data for the write are stored in registers. The write information must be stored because the SRAM cannot perform the last word write to the array without conflicting with the read. The data stays in this register until the next write cycle occurs. On the first write cycle after the read(s), the stored data from the earlier write is written into the SRAM array. This is called a posted write.

If a read is performed on the same address on which a write is performed in the previous cycle, the SRAM reads out the most current data. The SRAM does this by bypassing the memory array and reading the data from the registers.

Depth Expansion

Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate.

Document Number: 001-07160 Rev. *F Page 6 of 26

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Programmable Impedance

Vterm = 0.75V

R = 50ohms

R = 250ohms

LD# C C#R/W#

DQ A

LD# C C#R/W#

DQ A

SRAM#1

SRAM#2

R = 250ohms

BUS

MASTER

(CPU

ASIC)

Addresses

Cycle Start#

R/W# Return CLK Source CLK

Return CLK#

Source CLK# Echo Clock1/Echo Clock#1 Echo Clock2/Echo Clock#2

CQ/CQ#

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω output impedance is adjusted every 1024 cycles at power up to account for drifts in supply voltage and temperature.

to enable the SRAM to adjust its output

, with V

=1.5V. The

DDQ

Echo Clocks

Echo clocks are provided on the DDR II to simplify data capture on high speed systems. Two echo clocks are generated by the DDR II. CQ is referenced with respect to C and CQ is referenced with respect to C

. These are free running clocks and are synchronized to the output clock of the DDR II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K

. The timing for the echo clocks is shown in Switching

Characteristics on page 20.

Application Example

Figure 1 shows two DDR II used in an application.

Figure 1. Application Example

DLL

These chips use a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the DLL is locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clocks K and K minimum of 30 ns. However, it is not necessary to reset the DLL to lock it to the desired frequency. The DLL automatically locks 1024 clock cycles after a stable clock is presented. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in DDR I mode (with one cycle latency and a longer access time). For information refer to the application note DLL Considerations in QDRII™/DDRII.

for a

Document Number: 001-07160 Rev. *F Page 7 of 26

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CY7C1318CV18 CY7C1320CV18

Truth Table

Notes

2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑

represents rising edge.

3. Device powers up deselected with the outputs in a tristate condition.

4. On CY7C1318CV18 and CY7C1320CV18, “A1” represents address location latched by the devices when transaction was initiated and “A2” represents the addresses sequence in the burst.

5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.

6. Data inputs are registered at K and K

rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7. It is recommended that K = K

and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging

symmetrically.

8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. BWS

, BWS1, BWS2, and BWS3 can be altered on different portions

of a write cycle, as long as the setup and hold requirements are achieved.

The truth table for the CY7C1318CV18, and CY7C1320CV18 follows.

Operation K LD R/W DQ DQ

Write Cycle:

L-H L L D(A1) at K(t + 1) ↑ D(A2) at K

Load address; wait one cycle; input write data on consecutive K and K

Read Cycle:

rising edges.

L-H L H Q(A1) at C(t + 1)↑ Q(A2) at C(t + 2) ↑

Load address; wait one and a half cycle; read data on consecutive C

and C rising edges.

NOP: No Operation L-H H X High-Z High-Z

Standby: Clock Stopped Stopped X X Previous State Previous State

[2, 3, 4, 5, 6, 7]

(t + 1) ↑

Burst Address Table

(CY7C1318CV18, CY7C1320CV18)

First Address (External) Second Address (Internal)

X..X0 X..X1

X..X1 X..X0

Write Cycle Descriptions

The write cycle description table for CY7C1318CV18 follows.

BWS0BWS1K

L L L–H – During the data portion of a write sequence :

Both bytes (D

) are written into the device.

[17:0]

L L – L-H During the data portion of a write sequence :

Both bytes (D

) are written into the device.

[17:0]

L H L–H – During the data portion of a write sequence :

Only the lower byte (D

[8:0]

L H – L–H During the data portion of a write sequence :

Only the lower byte (D

[8:0]

H L L–H – During the data portion of a write sequence :

Only the upper byte (D

[17:9]

H L – L–H During the data portion of a write sequence :

Only the upper byte (D

[17:9]

H H L–H – No data is written into the devices during this portion of a write operation.

H H – L–H No data is written into the devices during this portion of a write operation.

[2, 8]

Comments

) is written into the device, D

remains unaltered.

[17:9]

remains unaltered.

[17:9]

remains unaltered.

[8:0]

remains unaltered.

[8:0]

Document Number: 001-07160 Rev. *F Page 8 of 26

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Write Cycle Descriptions

The write cycle description table for CY7C1320CV18 follows.

BWS0BWS1BWS2BWS3K K Comments

[2, 8]

LLLLL–H–During the data portion of a write sequence, all four bytes (D

the device.

LLLL–L–HDuring the data portion of a write sequence, all four bytes (D

the device.

L H H H L–H – During the data portion of a write sequence, only the lower byte (D

into the device. D

remains unaltered.

[35:9]

L H H H – L–H During the data portion of a write sequence, only the lower byte (D

into the device. D

remains unaltered.

[35:9]

H L H H L–H – During the data portion of a write sequence, only the byte (D

the device. D

[8:0]

and D

remains unaltered.

[35:18]

H L H H – L–H During the data portion of a write sequence, only the byte (D

the device. D

[8:0]

and D

remains unaltered.

[35:18]

H H L H L–H – During the data portion of a write sequence, only the byte (D

the device. D

[17:0]

and D

remains unaltered.

[35:27]

H H L H – L–H During the data portion of a write sequence, only the byte (D

the device. D

[17:0]

and D

remains unaltered.

[35:27]

H H H L L–H – During the data portion of a write sequence, only the byte (D

the device. D

remains unaltered.

[26:0]

H H H L – L–H During the data portion of a write sequence, only the byte (D

the device. D

remains unaltered.

[26:0]

) are written into

[35:0]

) are written into

[35:0]

[8:0]

) is written into

[17:9]

) is written into

[17:9]

) is written into

[26:18]

) is written into

[26:18]

) is written into

[35:27]

) is written into

[35:27]

) is written

HHHHL–H–No data is written into the device during this portion of a write operation.

HHHH–L–HNo data is written into the device during this portion of a write operation.

Document Number: 001-07160 Rev. *F Page 9 of 26

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IEEE 1149.1 Serial Boundary Scan (JTAG)

These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8V I/O logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to V unconnected. Upon power up, the device comes up in a reset state, which does not interfere with the operation of the device.

Test Access Port—Test Clock

The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.

Test Mode Select (TMS)

The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.

Test Data-I n ( TDI)

The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State

Diagram on page 12. TDI is internally pulled up and can be

unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register.

Test Data-Out (TDO)

The TDO output pin is used to serially clock data out from the registers. The output is active, depending upon the current state of the TAP state machine (see Instruction Codes on page 15). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This Reset does not affect the operation of the SRAM and can be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a high-Z state.

TAP Registers

Registers are connected between the TDI and TDO pins to scan the data in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK.

through a pull up resistor. TDO must be left

Instruction Register

Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in TAP Controller Block Diagram on page 13. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described in the previous section.

When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This enables shifting of data through the SRAM with minimal delay. The bypass register is set LOW (V the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all of the input and output pins on the SRAM. Several No Connect (NC) pins are also included in the scan register to reserve pins for higher density devices.

The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the input and output ring.

The Boundary Scan Order on page 16 shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page 15.

) when

TAP Instruction Set

Eight different instructions are possible with the three-bit instruction register. All combinations are listed in Instruction

Codes on page 15. Three of these instructions are listed as

RESERVED and must not be used. The other five instructions are described in detail below.

Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller must be moved into the Update-IR state.

Document Number: 001-07160 Rev. *F Page 10 of 26

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IDCODE

The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test-Logic-Reset state.

SAMPLE Z

The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is supplied during the Update IR state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured in the boundary scan register.

The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible.

To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (t correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK

Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.

and tCH). The SRAM clock input might not be captured

captured in the boundary scan register.

PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.

EXTEST

The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects the boundary scan register for serial access between the TDI and TDO in the Shift-DR controller state.

EXTEST OUTPUT BUS TRISTATE

IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tristate mode.

The boundary scan register has a special bit located at bit #47. When this scan cell, called the “extest output bus tristate,” is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

Document Number: 001-07160 Rev. *F Page 11 of 26

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TAP Controller State Diagram

TEST-LOGIC RESET

TEST-LOGIC/ IDLE

SELECT DR-SCAN

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

EXIT2-DR

UPDATE-DR

SELECT IR-SCAN

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAU SE-IR

EXIT2-IR

UPDATE-IR

Note

9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

The state diagram for the TAP controller follows.

[9]

Document Number: 001-07160 Rev. *F Page 12 of 26

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TAP Controller Block Diagram

012..29

3031

Boundary Scan Register

Identification Register

012..

.106

012

Instruction Register

Bypass Register

Selection Circuitry

TAP Controller

TDI

TDO

TCK

TMS

Notes

10. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.

11. Overshoot: V

(AC) < V

DDQ

+ 0.85V (Pulse width less than t

CYC

/2), Undershoot: V

(AC) > −1.5V (Pulse width less than t

CYC

/2).

12. All Voltage referenced to Ground.

TAP Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions Min Max Unit

OH1

OH2

OL1

OL2

Output HIGH Voltage I

Output LOW Voltage IOL = 2.0 mA 0.4 V

Output LOW Voltage IOL = 100 μA0.2V

Input HIGH Voltage 0.65VDDV

Input LOW Voltage –0.3 0.35V

Input and Output Load Current GND ≤ VI ≤ V

[10, 11, 12]

= −2.0 mA 1.4 V

= −100 μA1.6 V

–5 5 μA

+ 0.3 V

Document Number: 001-07160 Rev. *F Page 13 of 26

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TAP AC Switching Characteristics

(a)

TDO

= 20 pF

= 50

GND

0.9V

1.8V

ALL INPUT PULSES

0.9V

Test Clock

Test Mode Select

TCK

TMS

Test Data In TDI

Test Data Out

TCYC

TMSH

TMSS

TDIS

TDIH

TDOV

TDOX

TDO

Notes

13. t

and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

14. Test conditions are specified using the load in TAP AC Test Conditions. t

R/tF

= 1 ns.

Over the Operating Range

Parameter Description Min Max Unit

TCYC

TCK Clock Cycle Time 50 ns

TCK Clock Frequency 20 MHz

TCK Clock HIGH 20 ns

TCK Clock LOW 20 ns

Setup Times

TMSS

TDIS

TMS Setup to TCK Clock Rise 5 ns

TDI Setup to TCK Clock Rise 5 ns

Capture Setup to TCK Rise 5 ns

Hold Times

TMSH

TDIH

TMS Hold after TCK Clock Rise 5 ns

TDI Hold after Clock Rise 5 ns

Capture Hold after Clock Rise 5 ns

Output Times

TDOV

TDOX

TCK Clock LOW to TDO Valid 10 ns

TCK Clock LOW to TDO Invalid 0 ns

[13, 14]

TAP Timing and Test Conditions

Figure 2 shows the TAP timing and test conditions.

Figure 2. TAP Timing and Test Conditions

[14]

Document Number: 001-07160 Rev. *F Page 14 of 26

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Identification Register Definitions

Instruction Field

Revision Number (31:29) 000 000 Version number.

Cypress Device ID (28:12) 11010100010010101 11010100010100101 Defines the type of SRAM.

Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of

ID Register Presence (0) 1 1 Indicates the presence of an

CY7C1318CV18 CY7C1320CV18

Value

Description

SRAM vendor.

ID register.

Scan Register Sizes

Instruction 3

Bypass 1

ID 32

Boundary Scan 107

Instruction Codes

Instruction Code Description

EXTEST 000 Captures the input and output ring contents.

IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.

SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between TDI and

RESERVED 011 Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures the input and output ring contents. Places the boundary scan register between TDI

RESERVED 101 Do Not Use: This instruction is reserved for future use.

RESERVED 110 Do Not Use: This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

This operation does not affect SRAM operation.

TDO. Forces all SRAM output drivers to a High-Z state.

and TDO. Does not affect the SRAM operation.

operation.

Document Number: 001-07160 Rev. *F Page 15 of 26

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Boundary Scan Order

Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID

0 6R 28 10G 56 6A 84 2J

16P299G575B853K

2 6N 30 11F 58 5A 86 3J

3 7P 31 11G 59 4A 87 2K

47N329F 605C881K

5 7R 33 10F 61 4B 89 2L

6 8R 34 11E 62 3A 90 3L

7 8P 35 10E 63 1H 91 1M

8 9R 36 10D 64 1A 92 1L

9 11P 37 9E 65 2B 93 3N

10 10P 38 10C 66 3B 94 3M

11 10N 39 11D 67 1C 95 1N

12 9P 40 9C 68 1B 96 2M

13 10M 41 9D 69 3D 97 3P

14 11N 42 11B 70 3C 98 2N

15 9M 43 11C 71 1D 99 2P

16 9N 44 9B 72 2C 100 1P

17 11L 45 10B 73 3E 101 3R

18 11M 46 11A 74 2D 102 4R

19 9L 47 Internal 75 2E 103 4P

20 10L 48 9A 76 1E 104 5P

21 11K 49 8B 77 2F 105 5N

22 10K 50 7C 78 3F 106 5R

23 9J 51 6C 79 1G

24 9K 52 8A 80 1F

25 10J 53 7A 81 3G

26 11J 54 7B 82 2G

27 11H 55 6B 83 1J

Document Number: 001-07160 Rev. *F Page 16 of 26

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Power Up Sequence in DDR II SRAM

DDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

Power Up Sequence

■ Apply power and drive DOFF either HIGH or LOW (all other

inputs can be HIGH or LOW).

❐ Apply V ❐ Apply V ❐ Drive DOFF HIGH.

■ Provide stable DOFF (HIGH), power, and clock (K, K) for 1024

cycles to lock the DLL.

before V

DDQ

before V

DDQ

or at the same time as V

REF

Figure 3. Power Up Waveforms

DLL Constraints

■ DLL uses K clock as its synchronizing input. The input must

have low phase jitter, which is specified as t

■ The DLL functions at frequencies down to 120 MHz.

■ If the input clock is unstable and the DLL is enabled, then the

DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide1024 cycles stable clock to relock to the desired clock frequency.

KC Var

Unstable Clock

> 1024 Stable clock

Start Normal Operation

Clock Start

DDQDD

(Clock Starts after Stable)

DDQDD

DOFF

DDQ

Stable (< +/- 0.1V DC per 50ns )

Fix High (or tie to V

DDQ

)

Document Number: 001-07160 Rev. *F Page 17 of 26

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Maximum Ratings

Notes

15. Power up: assumes a linear ramp from 0V to V

(min) within 200 ms. During this time V

< V

and V

DDQ

< VDD.

16. Outputs are impedance controlled. I

= –(V

DDQ

/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

17. Outputs are impedance controlled. I

= (V

DDQ

/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

18. V

REF

(min) = 0.68V or 0.46V

DDQ

, whichever is larger, V

REF

(max) = 0.95V or 0.54V

DDQ

, whichever is smaller.

19. The operation current is calculated with 50% read cycle and 50% write cycle.

Neutron Soft Error Immunity

Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with Power Applied.. –55°C to +125°C

Supply Voltage on VDD Relative to GND ........–0.5V to +2.9V

Supply Voltage on V

DC Applied to Outputs in High-Z .........–0.5V to V

DC Input Voltage

Relative to GND.......–0.5V to +V

DDQ

[11]

...............................–0.5V to VDD + 0.3V

DDQ

+ 0.3V

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V

Latch up Current..................................................... >200 mA

Parameter Description

LSBU Logical

Single-Bit

Upsets

LMBU Logical

Multi-Bit

Upsets

SEL Single Event

Latch up

* No LMBU or SEL events occurred during testing; this column represents a statistical χ cation Note AN 54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates”

, 95% confidence limit calculation. For more details refer to Appli-

Test

Conditions

Typ Max* Unit

25°C 320 368 FIT/

25°C 0 0.01 FIT/

85°C 0 0.1 FIT/

Operating Range

Range

Temperature (TA) V

Commercial 0°C to +70°C 1.8 ± 0.1V 1.4V to

Industrial –40°C to +85°C

Ambient

[15]

DDQ

[15]

Electrical Characteristics

DC Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions Min Typ Max Unit

DDQ

OH(LOW)

OL(LOW)

REF

[19]

Power Supply Voltage 1.7 1.8 1.9 V I/O Supply Voltage 1.4 1.5 V Output HIGH Voltage Note 16 V Output LOW Voltage Note 17 V Output HIGH Voltage I Output LOW Voltage IOL = 0.1 mA, Nominal Impedance V Input HIGH Voltage V Input LOW Voltage –0.3 V Input Leakage Current GND ≤ VI ≤ V Output Leakage Current GND ≤ VI ≤ V Input Reference Voltage VDD Operating Supply V

[12]

/2 – 0.12 V

DDQ

/2 – 0.12 V

DDQ

= −0.1 mA, Nominal Impedance V

DDQ

Output Disabled −5 5 μA

= 1/t

DDQ,

CYC

267 MHz (x18) 805 mA

(x36) 855

250 MHz (x18) 730

[18]

Typical Value = 0.75V 0.68 0.75 0.95 V

= Max,

= 0 mA,

OUT

f = f

MAX

– 0.2 V

DDQ

+ 0.1 V

REF

−5 5 μA

/2 + 0.12 V

DDQ

/2 + 0.12 V

DDQ

0.2 V

DDQ

REF

(x36) 775

200 MHz (x18) 600

(x36) 635

167 MHz (x18) 510

(x36) 540

+ 0.3 V – 0.1 V

Dev

Document Number: 001-07160 Rev. *F Page 18 of 26

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Electrical Characteristics (continued)

1.25V

0.25V

R = 50

5pF

INCLUDING

JIG AND

SCOPE

ALL INPUT PULSES

Device

= 50

REF

= 0.75V

REF

= 0.75V

[20]

0.75V

Under Te st

0.75V

Device Under Te st

OUTPUT

0.75V

REF

OUTPUT

(a)

Slew Rate = 2 V/ns

RQ = 250

(b)

RQ = 250

Note

20. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, V

REF

= 0.75V, RQ = 250Ω, V

DDQ

= 1.5V, input pulse

levels of 0.25V to 1.25V, and output loading of the specified I

OL/IOH

and load capacitance shown in (a) of AC Test Loads and Waveforms.

DC Electrical Characteristics

Over the Operating Range

[12]

Parameter Description Test Conditions Min Typ Max Unit

SB1

Automatic Power Down Current

Max VDD, Both Ports Deselected, V

≥ VIH or VIN ≤ VIL

MAX

= 1/t

CYC,

f = f Inputs Static

267 MHz (x18) 315 mA

(x36) 330

250 MHz (x18) 300

(x36) 320

200 MHz (x18) 290

(x36) 300

167 MHz (x18) 285

(x36) 295

AC Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions Min Typ Max Unit

Input HIGH Voltage V Input LOW Voltage – – V

[11]

+ 0.2 – – V

REF

– 0.2 V

REF

Capacitance

Tested initially and after any design or process change that may affect these parameters.

Parameter Description Test Conditions Max Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz, VDD = 1.8V, V C

CLK

Clock Input Capacitance 6 pF Output Capacitance 7pF

= 1.5V 5 pF

DDQ

Thermal Resistance

Tested initially and after any design or process change that may affect these parameters.

Parameter Description Test Conditions

Document Number: 001-07160 Rev. *F Page 19 of 26

Thermal Resistance

(Junction to Ambient) Thermal Resistance

(Junction to Case)

Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51.

Figure 4. AC Test Loads and Waveforms

165 FBGA

Package

18.7 °C/W

4.5 °C/W

Unit

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CY7C1318CV18 CY7C1320CV18

Switching Characteristics

Notes

21. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range.

22. This part has an internal voltage regulator; t

POWER

is the time that the power is supplied above V

minimum initially before a read or write operation can be initiated.

Over the Operating Range

[20, 21]

Cypress

Parameter

POWER

CYC

KHKH

KHCH

Consortium

Parameter

KHKH

KHKL

KLKH

KHKH

KHCH

Setup Times

SCDDR

AVKH

IVKH

DVKH

Hold Times

HCDDRtKHIX

KHAX

KHIX

KHDX

Description

Unit

Min Max Min Max Min Max Min Max

267 MHz 250 MHz 200 MHz 167 MHz

VDD(Typical) to the First Access

[22]

1–1–1–1–ms

K Clock and C Clock Cycle Time 3.75 8.4 4.0 8.4 5.0 8.4 6.0 8.4 ns

Input Clock (K/K and C/C) HIGH 1.5 – 1.6 – 2.0 – 2.4 – ns

Input Clock (K/K and C/C) LOW 1.5 – 1.6 – 2.0 – 2.4 – ns

K Clock Rise to K Clock Rise and C to C Rise

1.68 – 1.8 – 2.2 – 2.7 – ns

(rising edge to rising edge)

K/K Clock Rise to C/C Clock Rise

0.00 1.68 0.00 1.8 0.00 2.2 0.00 2.7 ns

(rising edge to rising edge)

Address Setup to K Clock Rise 0.3 – 0.5 – 0.6 – 0.7 – ns

Control Setup to K Clock Rise (LD, R/W) 0.3 – 0.5 – 0.6 – 0.7 – ns

Double Data Rate Control Setup to Clock (K/K) Rise (BWS

[X:0]

, BWS1, BWS2, BWS3)

Setup to Clock (K and K) Rise 0.3 – 0.35 – 0.4 – 0.5 – ns

0.3 – 0.35 – 0.4 – 0.5 – ns

Address Hold after K Clock Rise 0.3 – 0.5 – 0.6 – 0.7 – ns

Control Hold after K Clock Rise (LD, R/W) 0.3 – 0.5 – 0.6 – 0.7 – ns

Double Data Rate Control Hold after Clock (K/K) Rise (BWS

[X:0]

, BWS1, BWS2, BWS3)

Hold after Clock (K/K) Rise 0.3 – 0.35 – 0.4 – 0.5 – ns

0.3 – 0.35 – 0.4 – 0.5 – ns

Document Number: 001-07160 Rev. *F Page 20 of 26

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Switching Characteristics (continued)

Notes

23. These parameters are extrapolated from the input timing parameters (t

KHKH

- 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t

KC Var

) is already

included in the t

KHKH

). These parameters are only guaranteed by design and are not tested in production.

24. t

CHZ

, t

CLZ

are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ±100 mV from steady-state voltage.

25. At any voltage and temperature t

CHZ

is less than t

CLZ

and t

CHZ

less than tCO.

Over the Operating Range

[20, 21]

Cypress

Parameter

Consortium

Parameter

Output Times

DOH

CCQO

CQOH

CQD

CQDOHtCQHQX

CQH

CQHCQHtCQHCQH

CHZ

CLZ

CHQV

CHQX

CHCQV

CHCQX

CQHQV

CQHCQL

CHQZ

CHQX1

DLL Timing

KC Var

KC lock

KC ResettKC Reset

KC Var

KC lock

Description

Unit

Min Max Min Max Min Max Min Max

267 MHz 250 MHz 200 MHz 167 MHz

C/C Clock Rise (or K/K in single clock mode) to

– 0.45 – 0.45 – 0.45 – 0.50 ns

Data Valid

Data Output Hold after Output C/C Clock Rise

–0.45 – –0.45 – –0.45 – –0.50 – ns

(Active to Active)

C/C Clock Rise to Echo Clock Valid – 0.45 – 0.45 – 0.45 – 0.50 ns

Echo Clock Hold after C/C Clock Rise –0.45 – –0.45 – –0.45 – –0.50 – ns

Echo Clock High to Data Valid – 0.27 – 0.30 – 0.35 – 0.40 ns

Echo Clock High to Data Invalid –0.27 – –0.30 – –0.35 – –0.40 – ns

Output Clock (CQ/CQ) HIGH

CQ Clock Rise to CQ Clock Rise (rising edge to rising edge)

Clock (C/C) Rise to High-Z (Active to High-Z)

[24, 25]

Clock (C/C) Rise to Low-Z

[23]

[24, 25]

1.43 – 1.55 – 1.95 – 2.45 – ns

– 0.45 – 0.45 – 0.45 – 0.50 ns

–0.45 – –0.45 – –0.45 – –0.50 – ns

Clock Phase Jitter – 0.20 – 0.20 – 0.20 – 0.20 ns

DLL Lock Time (K, C) 1024 – 1024 – 1024 – 1024 – Cycles

K Static to DLL Reset 30–30–30–30– ns

Document Number: 001-07160 Rev. *F Page 21 of 26

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Switching Waveforms

Notes

26. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

27. Outputs are disabled (High-Z) one clock cycle after a NOP.

28. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.

Figure 5. Read/Write/Deselect Sequence

[26, 27, 28]

R/W

NOP

KHCH

READ READREAD NOP NOP WRITEWRITE

2345678 910

KHKH

CLZ

Q00 Q11Q01 Q10

CQDOH

DOH

CQD

CHZ

D20

D21 D30

CYC

D31

KHKH

Q40

CYC

KHCH

Q41

CCQO

CQH

CQHCQH

DON’T CARE

UNDEFINED

CQ#

CQOH

CCQO

CQOH

Document Number: 001-07160 Rev. *F Page 22 of 26

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Ordering Information

The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at

http://www.cypress.com/products

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices

Table 1. Ordering Information

Speed

(MHz) Ordering Code

267 CY7C1318CV18-267BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free Commercial

CY7C1320CV18-267BZXC

250 CY7C1318CV18-250BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1320CV18-250BZC

CY7C1318CV18-250BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1320CV18-250BZXC

200 CY7C1320CV18-200BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1318CV18-200BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1318CV18-200BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial

167 CY7C1318CV18-167BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1320CV18-167BZC

Package Diagram Package Type

Operating

Range

Document Number: 001-07160 Rev. *F Page 23 of 26

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Package Diagram

51-85180-*B

PIN 1 CORNER

15.00±0.10

13.00±0.10

7.00

1.00

Ø0.50 (165X)

Ø0.25 M C A B

Ø0.08 M C

0.15(4X)

0.35±0.06

SEATING PLANE

0.53±0.05

0.25 C

0.15 C

PIN 1 CORNER

TOP VIEW

BOTTOM VIEW

2345678910

10.00

14.00

1110986754321

15.00±0.10

13.00±0.10

1.00

5.00

0.36

-0.06 +0.14

1.40 MAX.

SOLDER PAD T YPE : NON-SOLDER MASK DEFINED (NSMD)

NOTES :

PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / ISSUE E

PACKAGE CODE : BB0AC

Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180

Document Number: 001-07160 Rev. *F Page 24 of 26

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Document History Page

Document Title: CY7C1318CV18/CY7C1320CV18, 18-Mbit DDR II SRAM 2-Word Burst Architecture Document Number: 001-07160

Rev. ECN No.

Submission

Date

** 433284 See ECN NXR New data sheet

*A 462615 See ECN NXR Changed t

*B 503690 See ECN VKN Minor change: Moved data sheet to web

*C 1523383 See ECN VKN/AESA Converted from preliminary to final

*D 2507747 See ECN VKN/PYRS Changed Ambient Temperature with Power Applied from “–10°C to +85°C” to “–55°C

*E 2518624 See ECN NXR/PYRS Changed JTAG ID (31:29) from 001 to 000

*F 2755838 08/25/2009 VKN/AESA Removed x8 and x9 part number details

Orig. of

Change

Description of Change

and t

from 10 ns to 5 ns and changed t

Characteristics table

from 40 ns to 20 ns, changed t

from 20 ns to 10 ns in TAP AC Switching

TDOV

TMSS

, t

TDIS

, tCS, t

TMSH

, t

TDIH

Modified Power-Up waveform

Updated Logic Block diagram Removed 300 MHz and 278 MHz speed bins Added 267 MHz speed bin Updated I Changed DLL minimum operating frequency from 80MHz to 120MHz Changed t Modified footnotes 20 and 28

specs

DD/ISB

max spec to 8.4ns

CYC

to +125°C” in the “Maximum Ratings“ on page 20 Updated power up sequence waveform and its description Added footnote #19 related to I Changed Θ

spec from 28.51 to 18.7; Changed Θ

spec from 5.91 to 4.5

Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information.

, t

Document Number: 001-07160 Rev. *F Page 25 of 26

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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

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© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-07160 Rev. *F Revised August 24, 2009 Page 26 of 26

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of thei r respective holders.

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Cypress CY7C1320CV18-250BZXC, 001-07160, CY7C1318CV18-200BZI, CY7C1320CV18-200BZC, CY7C1320CV18-167BZC User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Functional Description

Configurations

Selection Guide

Logic Block Diagram (CY7C1318CV18)

Logic Block Diagram (CY7C1320CV18)

Pin Configuration

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

Pin Definitions

Functional Overview

Read Operations

Write Operations

Byte Write Operations

Single Clock Mode

DDR Operation

Depth Expansion

Programmable Impedance

Echo Clocks

Application Example

Truth Table

Write Cycle Descriptions

Write Cycle Descriptions

IEEE 1149.1 Serial Boundary Scan (JTAG)

Disabling the JTAG Feature

Test Mode Select (TMS)

Test Data-I n ( TDI)

Test Data-Out (TDO)

Performing a TAP Reset

TAP Registers

Instruction Register

Bypass Register

Boundary Scan Register

Identification (ID) Register

TAP Instruction Set

IDCODE

SAMPLE Z

SAMPLE/PRELOAD

BYPASS

EXTEST

EXTEST OUTPUT BUS TRISTATE

Reserved

TAP Controller State Diagram

TAP Controller Block Diagram

TAP Electrical Characteristics

TAP AC Switching Characteristics

TAP Timing and Test Conditions

Identification Register Definitions

Scan Register Sizes

Instruction Codes

Boundary Scan Order

Power Up Sequence in DDR II SRAM

Power Up Sequence

DLL Constraints

Maximum Ratings

Neutron Soft Error Immunity

Operating Range

Electrical Characteristics

DC Electrical Characteristics

AC Electrical Characteristics

Capacitance

Thermal Resistance

Switching Characteristics

Switching Waveforms

Ordering Information

Package Diagram

Document History Page

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Products