Cypress CY7C1310AV18, CY7C1312AV18, CY7C1314AV18 User Manual
CY7C1310AV18
Logic Block Di
(CY7C1310AV18)
CY7C1312AV18
PRELIMINARY
CY7C1314AV18
18-Mb QDR™-II SRAM 2-Word Burst Architecture
Features
• Separate independent Read and Write data ports
— Supports concurrent transactions
• 167-MHz clock for high bandwidth
• 2-Word Burst on all accesses
• Double Data Rate (DDR) interfaces on both Read and
Write ports (data transferred at 333 MHz) @ 167MHz
• Two input clocks (K and K
— SRAM uses rising edges only
• Two output clocks (C and C
and flight time mismatching
• Echo clocks (CQ and CQ
speed systems
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• Available in x8, x18, and x36 configurations
• Full data coherancy , providing most current data
• Core Vdd=1.8V(+/-0.1V);I/O Vddq=1.4V to Vdd
• 13 x 15 x 1.4 mm 1.0-mm pitch FBGA package, 165 ball
(11x15 matrix)
• Variable drive HSTL output buffers
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1310AV18 – 2M x 8
CY7C1312AV18 – 1M x 18
CY7C1314AV18 – 512K x 36
agram
D
[7:0]
A
(19:0)
20
) for precise DDR timing
) account for clock skew
) simplify data capture in high
8
Write
Address
Register
Reg
Functional Description
The CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 are
1.8V Synchronous Pipelined SRAMs, equipped with QDR-II
architecture. QDR-II architecture consists of two separate
ports to access the memory array. The Read port has
dedicated Data Outputs to support Read operations and the
Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data
outputs to completely eliminate the need to “turn-around” the
data bus required with common I/O devices. Access to each
port is accomplished through a common address bus. The
Read address is latched on the rising edge of the K clock and
the Write address is latched on the rising edge of the K
Accesses to the QDR-II Read and Write ports are completely
independent of one another. In order to maximize data
throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with two 8-bit words (CY7C1310AV18) or 18-bit
words (CY7C1312AV18) or 36-bit words (CY7C1314AV18)
that burst sequentially into or out of the device. Since data can
be transferred into and out of the device on every rising edge
of both input clocks (K and K
is maximized while simplifying system design by eliminating
bus “turn-arounds.”
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K
registers controlled by the C or C
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Write
Reg
1M x 8 Array
input clocks. All data outputs pass through output
1M x 8 Array
and C and C), memory bandwidth
(or K or K in a single clock
Address
Register
20
A
clock.
(19:0)
K
K
DOFF
V
REF
WPS
BWS
[1:0]
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05497 Rev. *A Revised June 1, 2004
CLK
Gen.
Control
Logic
Write Add. Decode
Read Data Reg.
16
Read Add. Decode
8
8
Reg.
Reg.
Control
Logic
Reg.
RPS
C
C
8
8
8
CQ
CQ
Q
[7:0]
[+] Feedback
Logic Block Diagram (CY7C1312AV18)
D
[17:0]
18
PRELIMINARY
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
Address
A
(18:0)
19
K
K
Register
CLK
Gen.
DOFF
V
REF
WPS
BWS
[1:0]
Control
Logic
Logic Block Diagram (CY7C1314AV18)
D
[35:0]
36
Address
A
(17:0)
18
Register
Write
Reg
512K x 18 Array
Write Add. Decode
Read Data Reg.
Write
Reg
Write
Reg
512K x 18 Array
Read Add. Decode
36
18
18
Write
Reg
256K x 36 Array
256K x 36 Array
Reg.
Reg.
Address
Register
Control
Logic
Reg.
Address
Register
18
18
19
C
C
18
RPS
18
A
A
(18:0)
Q
[17:0]
(17:0)
CQ
CQ
36
36
RPS
C
C
36
Q
[35:0]
DOFF
V
REF
WPS
BWS
K
K
[3:0]
CLK
Gen.
Control
Logic
Write Add. Decode
Read Data Reg.
72
Read Add. Decode
36
36
Reg.
Reg.
Control
Logic
Reg.
Selection Guide
167 MHz 133 MHz Unit
Maximum Operating Frequency 167 133 MHz
Maximum Operating Current 800 700 mA
CQ
CQ
Document #: 38-05497 Rev. *A Page 2 of 21
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Pin Configurations
PRELIMINARY
CY7C1310AV18 (2M × 8) – 11 × 15 BGA
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
A
B
C
D
E
F
G
H
K
L
M
N
P
R
A
B
C
D
E
F
G
H
K
L
M
N
P
R
1
CQ
NC
NC
NC
NC
NC
NC
DOFF
J
NC
NC
NC
NC
NC
NC
TDO
23
/72M A
V
SS
NC
NC
D4 V
NC
NC
D5
V
REF
NC
NC
Q6
NC
D7
NC
TCK
NC
NC
NC V
Q4
NC
Q5 V
V
DDQ
NC
NC
D6
NC
NC
Q7
A
4567
BWS
A NC/288M
AAA
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
V
V
V
V
V
V
V
SS
V
SS
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
SS
V
SS
A
A
1
V
V
V
V
V
V
V
V
V
KWPS
K
SS
SS
SS
SS
SS
SS
SS
SS
SS
A
C
C
NC/144M
BWS
0
SS
VSS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
891011
RPS
A NC
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
AV
NC NC D3
NC
NC
NC NC
NC
V
DDQ
NC
NC
NC
NC D0
NC
NC
A
SS
V
/36M
NC
NC
D2
NC
NC
REF
Q1
NC
NC
NC
NC
NC
CQ
Q3
NC
Q2
NC
ZQ
D1V
NC
Q0
NC
NC
TDITMS
CY7C1312AV18 (1M × 18) – 11 × 15 BGA
234 56 71
/144M NC/36M
V
CQ
NC
NC
NC
NC V
NC
NC
DOFF
J
NC
NC
NC
NC
NC
NC
TDO
SS
Q9
NC
D11 V
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
D9
D10
Q10 V
Q11
D12
Q13 V
V
DDQ
D14
Q14
D15
D16
Q16
Q17
A
WPS
BWS
A NC
V
SS
V
SS
V
DDQ
V
DDQ
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
1
AAA
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
V
V
V
V
V
V
V
A
A
A
K
K
SS
SS
SS
SS
SS
SS
SS
SS
SS
A
C
NC/288M
BWS
0
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
AC
891011
RPS
A NC
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
AV
NC Q7 D8
NC
NC
NC Q5
NC
V
DDQ
NC
NC
NC
NC D2
NC
NC
A
SS
V
/72M
NC
NC
D6
NC
NC
REF
Q4
D3
NC
Q1
NC
D0
CQ
Q8
D7
Q6
D5
ZQ
D4V
Q3
Q2
D1
Q0
TDITMS
Document #: 38-05497 Rev. *A Page 3 of 21
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Pin Configurations (continued)
PRELIMINARY
CY7C1314AV18 (512k × 36) – 11 × 15 BGA
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
A
B
C
D
E
G
H
K
M
N
P
R
1
CQ
Q27
D27
D28
Q29
F
J
L
Q30
D30
DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
23
/288M NC/72M
V
SS
Q18
Q28
D20 V
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
D18
D19
Q19 V
Q20
D21
Q22 V
V
DDQ
D23
Q23
D24
D25
Q25
Q26
A
4
WPS
A
V
SS
V
SS
V
DDQ
V
DDQ
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
567
BWS
2
BWS
3
AAA
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
K
K
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
BWS
BWS
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
1
0
Pin Definitions
Pin Name I/O Pin Description
D
[x:0]
WPS Input-
BWS
, BWS1,
0
BWS
, BWS
2
3
A Input-
Input-
Synchronous
Synchronous
Input-
Synchronous
Synchronous
Data input signals, sampled on the rising edge of K and K clocks during valid write
operations.
CY7C1310AV18 - D
CY7C1312AV18 - D
CY7C1314AV18 - D
[7:0]
[17:0]
[35:0]
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When
asserted active, a write operation is initiated. Deasserting will deselect the Write port.
Deselecting the Write port will cause D
[x:0]
Byte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K and
K
clocks during write operations. Used to select which byte is written into the device
during the current portion of the write operations. Bytes not written remain unaltered.
CY7C1310AV18 − BWS
CY7C1312AV18 − BWS
CY7C1314AV18 − BWS0 controls D
and BWS
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte
controls D
3
controls D
0
controls D
0
[35:27].
and BWS1 controls D
[3:0]
and BWS1 controls D
[8:0]
, BWS1 controls D
[8:0]
Write Select will cause the corresponding byte of data to be ignored and not written into
the device.
Address Inputs. Sampled on the rising edge of the K (read address) and K
address) clocks during active read and write operations. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 2M x 8
(2 arrays each of 1M x 8) for CY7C1310AV18, 1M x 18 (2 arrays each of 512K x 18) for
CY7C1312AV18 and 512K x 36 (2 arrays each of 256K x 36) for CY7C1314AV18.
Therefore, only 20 address inputs are needed to access the entire memory array of
CY7C1310AV18, 19 address inputs for CY7C1312AV18 and 18 address inputs for
CY7C1314AV18. These inputs are ignored when the appropriate port is deselected.
891011
RPS
A D17
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
to be ignored.
NC/36M V
D16 Q7 D8
Q16
Q15
D14 Q5
Q13
VDDQ
D12
Q12
D11
D10 D2
Q10
Q9
A
[7:4]
[17:9].
, BWS2 controls D
[17:9]
/144M
SS
Q17
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
.
(write
CQ
Q8
D7
Q6
D5
ZQ
D4V
Q3
Q2
D1
Q0
TDITMS
[26:18]
Document #: 38-05497 Rev. *A Page 4 of 21
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CY7C1310AV18
CY7C1312AV18
PRELIMINARY
Pin Definitions (continued)
Pin Name I/O Pin Description
Q
[x:0]
RPS Input-
C Input-Clock Positive Output Clock Input. C is used in conjunction with C to clock out the Read data
C
K Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs
K
CQ Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized
CQ
ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the
DOFF
TDO Output TDO for JTAG.
TCK Input TCK pin for JTAG.
TDI Input TDI pin for JTAG.
TMS Input TMS pin for JTAG.
NC N/A Not connected to the die. Can be tied to any voltage level.
NC/36M N/A Address expansion for 36M. This is not connected to the die and so can be tied to any
NC/72M N/A Address expansion for 72M. This is not connected to the die and so can be tied to any
V
/72M Input Address expansion for 72M. This must be tied LOW on the 18M devices.
SS
/144M Input Address expansion for 144M. This must be tied LOW on the 18M devices.
V
SS
V
288M Input Address expansion for 288M. This must be tied LOW on the 18M devices.
SS/
Outputs-
Synchronous
Synchronous
Input-Clock Negative Output Clock Input. C is used in conjunction with C to clock out the Read data
Input-Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented
Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized
Input DLL Turn Off – Active LOW. Connecting this pin to ground will turn off the DLL inside
Data Output signals. These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C
operations or K and K
Q
are automatically tri-stated.
[x:0]
CY7C1310AV18 − Q
CY7C1312AV18 − Q
CY7C1314AV18 − Q
Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K).
When active, a Read operation is initiated. Deasserting will cause the Read port to be
deselected. When deselected, the pending access is allowed to complete and the output
drivers are automatically tri-stated following the next rising edge of the C clock. Each
read access consists of a burst of two sequential transfers.
from the device. C and C
devices on the board back to the controller. See application example for further details.
from the device. C and C
devices on the board back to the controller. See application example for further details.
to the device and to drive out data through Q
are initiated on the rising edge of K.
to the device and to drive out data through Q
to the output clock(C) of the QDR-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC timing table.
to the output clock(C
respect to K
system data bus impedance. CQ,CQ
where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to VDD, which enables the minimum impedance mode. This pin cannot
be connected directly to GND or left unconnected.
the device. The timings in the DLL turned off operation will be different from those listed
in this data sheet. More details on this operation can be found in the application note,
“DLL Operation in the QDR-II.”
voltage level.
voltage level.
. The timings for the echo clocks are shown in the AC timing table.
when in single clock mode. When the Read port is deselected,
[7:0]
[17:0]
[35:0]
can be used together to deskew the flight times of various
can be used together to deskew the flight times of various
when in single clock mode. All accesses
[x:0]
when in single clock mode.
[x:0]
) of the QDR-II. In the single clock mode, CQ is generated with
and Q
output impedance are set to 0.2 x RQ,
[x:0]
CY7C1314AV18
clocks during Read
Document #: 38-05497 Rev. *A Page 5 of 21
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PRELIMINARY
Pin Definitions (continued)
Pin Name I/O Pin Description
V
V
V
V
REF
DD
SS
DDQ
Input-
Reference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs
and Outputs as well as AC measurement points.
Power Supply Power supply inputs to the core of the device.
Ground Ground for the device.
Power Supply Power supply inputs for the outputs of the device.
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
Introduction
Functional Overview
The CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 are
synchronous pipelined Burst SRAMs equipped with both a
Read port and a Write port. The Read port is dedicated to
Read operations and the Write port is dedicated to Write
operations. Data flows into the SRAM through the Write port
and out through the Read Port. These devices multiplex the
address inputs in order to minimize the number of address pins
required. By having separate Read and Write ports, the QDR-II
completely eliminates the need to “turn-around” the data bus
and avoids any possible data contention, thereby simplifying
system design. Each access consists of two 8-bit data
transfers in the case of CY7C1310AV18, two 18-bit data
transfers in the case of CY7C1312AV18 and two 36-bit data
transfers in the case of CY7C1314AV18, in one clock cycles.
Accesses for both ports are initiated on the rising edge of the
positive Input Clock (K). All synchronous input timings are
referenced from the rising edge of the input clocks (K and K
and all output timings are referenced to the rising edge of
output clocks (C and C
All synchronous data inputs (D
registers controlled by the input clocks (K and K
synchronous data outputs (Q
registers controlled by the rising edge of the output clocks (C
and C
or K and K when in single clock mode).
All synchronous control (RPS
through input registers controlled by the rising edge of the
input clocks (K and K
CY7C1312AV18 is described in the following sections. The
same basic descriptions apply to CY7C1310AV18 and
CY7C1314AV18.
Read Operations
The CY7C1312AV18 is organized internally as two arrays of
512Kx18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
RPS
active at the rising edge of the Positive Input Clock (K).
The address is latched on the rising edge of the K Clock. The
address presented to Address inputs is stored in the Read
address register. Following the next K clock rise the corresponding lowest order 18-bit word of data is driven onto the
Q
using C as the output timing reference. On the subse-
[17:0]
quent rising edge of C, the next 18-bit data word is driven onto
the Q
rising edge of the output clock (C and C
. The requested data will be valid 0.45 ns from the
[17:0]
single clock mode).
Synchronous internal circuitry will automatically tri-state the
outputs following the next rising edge of the Output Clocks
(C/C
). This will allow for a seamless transition between
or K and K when in single clock mode).
) inputs pass through input
[x:0]
) outputs pass through output
[x:0]
, WPS, BWS
) inputs pass
[x:0]
). All
).
or K and K when in
devices without the insertion of wait states in a depth
expanded memory.
Write Operations
Write operations are initiated by asserting WPS
active at the
rising edge of the Positive Input Clock (K). On the same K
clock rise, the data presented to D
into the lower 18-bit Write Data register provided BWS
is latched and stored
[17:0]
both asserted active. On the subsequent rising edge of the
Negative Input Clock (K
mation presented to D
Register provided BWS
bits of data are then written into the memory array at the
), the address is latched and the infor-
is stored into the Write Data
[17:0]
are both asserted active. The 36
[1:0]
specified location. When deselected, the write port will ignore
all inputs after the pending Write operations have been
completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1312AV18.
A write operation is initiated as described in the Write
)
Operation section above. The bytes that are written are determined by BWS
data word. Asserting the appropriate Byte Write Select input
and BWS1 which are sampled with each 18-bit
0
during the data portion of a write will allow the data being
presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
Single Clock Mode
The CY7C1312AV18 can be used with a single clock that
controls both the input and output registers. In this mode, the
device will recognize only a single pair of input clocks (K and
K
) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C
HIGH at power on. This function is
a strap option and not alterable during device operation.
Concurrent Transactions
The Read and Write ports on the CY7C1312AV18 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the transaction on the other port. Also, reads and writes can be started
in the same clock cycle. If the ports access the same location
at the same time, the SRAM will deliver the most recent information associated with the specified address location. This
includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.
[1:0]
are
Document #: 38-05497 Rev. *A Page 6 of 21
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PRELIMINARY
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
Depth Expansion
The CY7C1312AV18 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the Positive Input Clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and V
output driver impedance. The value of RQ must be 5x the
to allow the SRAM to adjust its
SS
value of the intended line impedance driven by the SRAM. The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω
V
= 1.5V.The output impedance is adjusted every 1024
DDQ
cycles upon powerup to account for drifts in supply voltage and
temperature.
Application Example
DATA IN
DATA OUT
Address
BUS
MASTER
(CPU
or
ASIC)
RPS#
WPS#
BWS#
CLKIN/CLKIN#
Source K
Source K#
[1]
SRAM #1
R
Vt
R
D
A
W
P
P
S
S
#
#
, with
B
W
S
#
CQ/CQ#
CC#
Echo Clocks
Echo clocks are provided on the QDR-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the QDR-II. CQ is referenced with respect to C
and CQ
is referenced with respect to C. These are
free-running clocks and are synchronized to the output
clock(C/C
generated with respect to K and CQ
to K
) of the QDR-II. In the single clock mode, CQ is
is generated with respect
. The timings for the echo clocks are shown in the AC
Timing table.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF
pin. The DLL can also be reset by slowing the cycle time
of input clocks K and K
\
R = 250ohms
ZQ
Q
K#
K
to greater than 30 ns.
SRAM #4
R
W
B
P
P
D
A
R
W
S
S
#
#
#
Vt
Vt
ZQ
CQ/CQ#
S
CC#
Q
K#
K
R = 250ohms
Delayed K
Truth Table
Delayed K#
[ 2, 3, 4, 5, 6, 7]
R
R = 50ohms
Vt = Vddq/2
Operation K RPS WPS DQ DQ
Write Cycle:
Load address on the rising edge of K
on K and K
rising edges.
Read Cycle:
clock; input write data
L-H X L D(A + 0)at K(t) ↑ D(A + 1) at K
L-H L X Q(A + 0) at C
(t + 1)↑ Q(A + 1) at C(t + 2) ↑
(t) ↑
Load address on the rising edge of K clock; wait one and a
half cycle; read data on C
NOP: No Operation L-H H H D=X
and C rising edges.
Q=High-Z
D=X
Q=High-Z
Standby: Clock Stopped Stopped X X Previous State Previous State
Notes:
1. The above application shows 4 QDRII being used.
2. X = “Don't Care,” H = Logic HIGH, L= Logic LOW,
3. Device will power-up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A+00, A+01 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K
7. It is recommended that K = K
charging symmetrically.
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS
write cycle, as long as the set-up and hold requirements are achieved.
rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
↑represents rising edge.
, BWS1, BWS2, and BWS3 can be altered on different portions of a
0
Document #: 38-05497 Rev. *A Page 7 of 21
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