Cypress CY7C131, CY7C140, CY7C130A, CY7C141, CY7C131A User Manual

CY7C130, CY7C130A
CY7C131, CY7C131A

CY7C140, CY7C141

1K x 8 Dual-Port Static RAM

Features

R/W

L

BUSY

L

CE

L

OE

L

A

9L

A

0L

A

0R

A

9R

R/W

R

CE

R

OE

R

CE

R

OE

R

CE

L

OE

L

R/W

L

R/W

R

I/O

7L

I/O

0L

I/O

7R

I/O

0R

BUSY

R

INT

L

INT

R

ARBITRATION

LOGIC

(7C130/7C131 ONLY)

AND

INTERRUPT LOGIC

CONTROL

I/O

CONTROL

I/O

MEMORY

ARRAY

ADDRESS

DECODER

ADDRESS
DECODER

[2]

[3]

[3]

Logic Block Diagram

Notes

1. CY7C130 and CY7C130A are functionally identical; CY7C131 and CY7C131A are functionally identical.

2. CY7C130/130A/CY7C131/131A (Master): BUSY

is open drain output and requires pull-up resistor .

CY7C140/CY7C141 (Slave): BUSY

is input.

3. Open drain outputs: pull-up resistor required.

■

True dual-ported memory cells, which allow simultaneous
reads of the same memory location

■

1K x 8 organization

■

0.65 micron CMOS for optimum speed and power

■

High speed access: 15 ns

■

Low operating power: ICC = 110 mA (maximum)

■

Fully asynchronous operation

■

Automatic power down

■

Master CY7C130/130A/CY7C131/131A easily expands data
bus width to 16 or more bits using slave CY7C140/CY7C141

■

BUSY output flag on CY7C130/130A/CY7C131/131A; BUSY
input on CY7C140/CY7C141

■

INT flag for port-to-port communication

■

Available in 48-pin DIP (CY7C130/130A/140), 52-pin PLCC,
52-pin TQFP

■

Pb-free packages available

Functional Description

The CY7C130/130A/CY7C131/131A/CY7C140
are high speed CMOS 1K by 8 dual-port static RAMs. Two ports
are provided permitting independent access to any location in
memory. The CY7C130/130A/ CY7C131/131A can be used as
either a standalone 8-bit dual-port static RAM or as a master
dual-port RAM in conjunction with the CY7C140/CY7C141 slave
dual-port device in systems requiring 16-bit or greater word
widths. It is the solution to applications requiring shared or
buffered data, such as cache memory for DSP, bit-slice, or multi­processor designs.

Each port has independent control pins; chip enable (CE
enable (R/W
on each port, BUSY

), and output enable (OE). Two flags are provided

and INT . BUSY signals that the port is trying
to access the same location currently being accessed by the
other port. INT is an interrupt flag indicating that data is placed
in a unique location (3FF for the left port and 3FE for the right
port). An automatic power down feature is controlled indepen­dently on each port by the chip enable (CE

The CY7C130/130A and CY7C140 are available in 48-pin DIP.
The CY7C131/131A and CY7C141 are available in 52-pin
PLCC, 52-pin Pb-free PLCC, 52-pin PQFP, and 52-pin Pb-free
PQFP.

[1]

and CY7C141

) pins.

), write

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-06002 Rev. *E Revised December 09, 2008

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CY7C130, CY7C130A
CY7C131, CY7C131A

CY7C140, CY7C141

Pin Configurations

13
14
15
16
17
18
19
20
21
22
23 26

27

28

32
31
30
29

33

36
35
34

24 25

GND

1
2
3
4
5
6
7
8
9
10
11

38

39

40

44
43

42
41

45

48
47
46

12 37

R/W

L

CE

L

BUSY

L

INT

L

OE

L

A

0L

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L

I/O

0L

I/O

1L

I/O

2L

I/O

3L

I/O

4L

I/O

5L

I/O

6L

I/O

7L

CE

R

R/W

R

BUSY

R

INT

R

OE

R

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

I/O

7R

I/O

6R

I/O

5R

I/O

4R

I/O

3R

I/O

2R

I/O

1R

I/O

0R

V

CC

7C130
7C140

1

V

CC

OE

R

A

0R

8
9
10
11
12
13
14
15
16
17
18
19
20

46
45
44
43
42
41
40
39
38
37
36
35
34

2122 23 24 25 26 27 28 29 30 31 32 33

7 6 5 4 3 2 52 51 50 49 48 47

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

NC
I/O

7R

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L

I/O

0L

I/O

1L

I/O

2L

I/O

3L

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

4L5L6L

7L

0R1R2R3R4R5R6R

NC

GND

OE

BUSY

INT

A

NC

R/W

CE

R/W

BUSY

INT

NC

0L

L

L

L

L

L

CE

R

R

R

R

7C131
7C141

46
1
2
3
4
5
6
7
8
9
10
11
12
13

39
38
37
36
35
34
33
32
31
30
29
28
27

1415 16 17 18 19 20 21 22 23 24 25 26

52 5150 49 48 47 45 44 43 42 41 40

V

CC

OE

BUSY

INT

A

NC

R/W

CE

R/W

BUSY

INT

NC

0L

L

L

L

L

L

CE

R

R

R

R

OE

R

A

0R

A

1R

A

2R

A

3R

A

4R

A

5R

A

6R

A

7R

A

8R

A

9R

NC
I/O

7R

A

1L

A

2L

A

3L

A

4L

A

5L

A

6L

A

7L

A

8L

A

9L

I/O

0L

I/O

1L

I/O

2L

I/O

3L

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

4L5L6L

7L

0R1R2R3R4R5R6R

NC

GND

7C131
7C141

Figure 1. Pin Diagram - DIP (Top View)

Figure 2. Pin Diagram - PLCC (Top View) Figure 3. Pin Diagram - PQFP (Top View)

Document #: 38-06002 Rev. *E Page 2 of 19

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CY7C130, CY7C130A
CY7C131, CY7C131A

CY7C140, CY7C141

Pin Definitions

Note

4. 15 and 25 ns version available only in PLCC/PQFP packages.

Left Port Right Port Description

CE

L

R/W

L

OE

L

A

0L–A11/12L

–I/O

I/O

0L

INT

L

BUSY

L

V

CC

15/17L

CE

R

R/W

R

OE

R

A0R–A

11/12R

I/O0R–I/O
INT

R

BUSY

R

15/17R

Chip Enable
Read/Write Enable
Output Enable
Address
Data Bus Input/Output
Interrupt Flag
Busy Flag
Power

GND Ground

Selection Guide

[4]

7C131-25

7C141-25

15 25 30 35 45 55 ns

75 65 65 45 45 35 mA

Parameter

Maximum Access Time
Maximum Operating

Com’l/Ind 190 170 170 120 120 110 mA

Current
Maximum Standby

Com’l/Ind

Current

Shaded areas contain preliminary information.

7C131-15

7C131A-15

7C141-15

7C130A-30

[4]

7C130-30
7C131-30

7C140-30
7C141-30

7C130-35
7C131-35
7C140-35
7C141-35

7C130-45
7C131-45
7C140-45
7C141-45

7C130-55
7C131-55
7C140-55
7C141-55

Unit

Document #: 38-06002 Rev. *E Page 3 of 19

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CY7C130, CY7C130A
CY7C131, CY7C131A

CY7C140, CY7C141

Maximum Ratings

[5]

Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested .

°

Storage Temperature .................................–65°C to +150

C

Ambient Temperature with

Power Applied ............................................–55°C to +125°C

Supply Voltage to Ground Potential

(Pin 48 to Pin 24)............................................–0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State...................................... ... .......–0.5V to +7.0V

DC Input Voltage................................ ... .........–3.5V to +7.0V

Output Current into Outputs (LOW).............................20 mA

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch Up Current.................................................... >200 mA

Operating Range

Range Ambient Temperature V

Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%

[6]

Military

–55°C to +125°C 5V ± 10%

CC

Electrical Characteristics

Over the Operating Range

[7]

Parameter Description Test Conditions

V

OH

V

OL

V

IH

V

IL

I

IX

I

OZ

I

OS

I

CC

I

SB1

I

SB2

I

SB3

I

SB4

Shaded areas contain preliminary information.

Notes

5. The voltage on any input or I/O pin cannot exceed the power pin during power up.

6. T

A

7. See the last page of this specification for Group A subgroup testing information.

8. BUSY

9. Duration of the short circuit should not exceed 30 seconds.

10.This parameter is guaranteed but not tested.

11. At f = f

Output HIGH Voltage VCC = Min, IOH = –4.0 mA 2.4 2.4 2.4 2.4 V
Output LOW Voltage IOL = 4.0 mA 0.4 0.4 0.4 0.4 V

IOL = 16.0 mA

[8]

Input HIGH Voltage 2.2 2.2 2.2 2.2 V
Input LOW Voltage 0.8 0.8 0.8 0.8 V
Input Leakage Current GND < VI < V
Output Leakage

Current
Output Short

Circuit Current

[9, 10]

VCC Operating
Supply Current

Standby Current
Both Ports, TTL Inputs

Standby Current
One Port,
TTL Inputs

Standby Current
Both Ports,
CMOS Inputs

Standby Current
One Port,
CMOS Inputs

is the “instant on” case temperature

and INT pins only.

, address and data inputs are cycling at the maximum frequency of read cycle of 1/tRC and using AC Test Waveforms input levels of GND to 3V.

MAX

GND < VO < VCC,
Output Disabled

VCC = Max,
V

= GND

OUT

CE = VIL,
Outputs Open, f = f

CEL and CER > VIH,
f = f

MAX

CE

or CER > VIH,

L

Active Port Outputs Open
f = f

MAX

Both Ports CEL and CER >

– 0.2V,

V

CC

V

> VCC – 0.2V

IN

or V

< 0.2V, f = 0

IN

One Port CEL or

> VCC – 0.2V,

CE

R

V

> VCC – 0.2V

IN

or V

< 0.2V,

IN

Active Port Outputs Open, f =

[11]

f

MAX

[11]

[11]

CC

MAX

[11]

[4]

7C130-35,45
7C131-35,45
7C140-35,45
7C141-35,45

7C130-55
7C131-55
7C140-55
7C141-55

Unit

7C131-15

7C131A-15

7C141-15

7C130-30

[4]

7C130A-30

7C131-25,30

7C140-30

7C141-25,30

Min Max Min Max Min Max Min Max

0.5 0.5 0.5 0.5

–5 +5 –5 +5 –5 +5 –5 +5 μA
–5 +5 –5 +5 –5 +5 –5 +5 μA

–350 –350 –350 –350 mA

Com’l 190 170 120 110 mA

Com’l 75 65 45 35 mA

Com’l 135 115 90 75 mA

Com’l

15 15 15 15 mA

Com’l 125 105 85 70 mA

Document #: 38-06002 Rev. *E Page 4 of 19

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CY7C130, CY7C130A
CY7C131, CY7C131A

CY7C140, CY7C141

Capacitance

3.0V

5V

OUTPUT

R1 893Ω

R2
347Ω

30 pF

INCLUDING

JIGAND

SCOPE

GND

90%

90%

10%

≤ 5ns

≤5

ns

5V

OUTPUT

R1 893Ω

R2
347Ω

5pF

INCLUDING

JIGAND

SCOPE

(a)

(b)

OUTPUT 1.40V

Equivalent to:

THÉVENIN EQUIVALENT

5V

281Ω

30

pF

BUSY

OR

INT

BUSY Output Load

(CY7C130/CY7C131 ONLY)

10%

ALL INPUT PULSES

250Ω

[10]

Parameter Description Test Conditions Max Unit

C

IN

C

OUT

Input Capacitance TA = 25°C, f = 1 MHz,

= 5.0V

V

Output Capacitance 10 pF

CC

15 pF

Figure 4. AC Test Loads and Waveforms

Document #: 38-06002 Rev. *E Page 5 of 19

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CY7C130, CY7C130A
CY7C131, CY7C131A

CY7C140, CY7C141

Switching Characteristics

Notes

12.Test conditions assume signal transition times of 5 ns or less , timing ref erence levels of 1.5 V, input pulse levels of 0 to 3.0V an d output loa ding of the specif ied
I

OL/IOH,

and 30 pF load capacitance.

13.AC Test Conditions use V

OH

= 1.6V and VOL = 1.4V.

14.At any given temperature and voltage condition for any given device, t

HZCE

is less than t

LZCE

and t

HZOE

is less than t

LZOE

.

15.t

LZCE

, t

LZWE

, t

HZOE

, t

LZOE

, t

HZCE

and t

HZWE

are tested with CL = 5 pF as in part (b) of AC Test Loads. Transit ion is measured ±500 mV from steady st ate voltage .

16.The internal write time of the memory is defined by the overlap of CS

LOW and R/W LOW. Both signals must be low to initiate a write and either signal can

terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.

Over the Operating Range

[7, 12]

Parameter Description

Read Cycle

t

RC

t

AA

t

OHA

t

ACE

t

DOE

t

LZOE

t

HZOE

t

LZCE

t

HZCE

t

PU

t

PD

Write Cycle

t

WC

t

SCE

t

AW

t

HA

t

SA

t

PWE

t

SD

t

HD

t

HZWE

t

LZWE

Shaded areas contain preliminary information.

Read Cycle Time 15 25 30 ns
Address to Data Valid

[13]

Data Hold from Address Change 0 00ns
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power Up

[13]
[13]

[10, 14, 15]

[10, 14, 15]

[10, 14, 15]

[10, 14, 15]

[10]

CE HIGH to Power Down

[16]

Write Cycle Time 15 25 30 ns
CE LOW to Write End 12 20 25 ns
Address Setup to Write End 12 20 25 ns
Address Hold from Write End 2 22ns
Address Setup to Write Start 0 00ns
R/W Pulse Width 12 15 25 ns
Data Setup to Write End 10 15 15 ns
Data Hold from Write End 0 00ns
R/W LOW to High Z
R/W HIGH to Low Z

[15]
[15]

[10]

7C131-15
7C131A-15

7C141-15

[4]

7C130-25

[4]

7C131-25
7C140-25
7C141-25

7C130-30

7C130A-30

7C131-30
7C140-30
7C141-30

Unit

Min Max Min Max Min Max

15 25 30 ns

15 25 30 ns
10 15 20 ns

3 33ns

10 15 15 ns

3 55ns

10 15 15 ns

0 00ns

15 25 25 ns

10 15 15 ns

0 00ns

Document #: 38-06002 Rev. *E Page 6 of 19

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