Cypress CY7C1305BV25, CY7C1307BV25 User Manual

Q

CY7C1305BV25
CY7C1307BV25

18-Mbit Burst of 4 Pipelined SRAM with

DR™ Architecture

Features

• Separate independent Read and Write data ports

• Supports concurrent transactions

• 167-MHz clock for high bandwidth

• 2.5 ns Clock-to-Valid access time

• 4-Word Burst for reducing the address bus frequency

• Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 333 MHz) @167 MHz

• Two input clocks (K and K

• SRAM uses rising edges only

• Two input clocks for output dat a (C and C
clock-skew and flight-time mismatches.

• Single multiplexed address input bus latches address
inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 2.5V core power supply with HSTL Inputs and Outputs

• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JT A G in terface

) for precise DDR timing

) to minimize

Configurations

Functional Description

The CY7C1305BV25/CY7C1307BV25 are 2.5V Synchronous
Pipelined SRAMs equipped with QDR architecture. QDR
architecture consists of two separate ports to access the
memory array. The Read port has dedicated Data Outputs to
support Read operations and the Write Port has dedicated
Data Inputs to support Write operations. QDR architecture has
separate data inputs and data outputs to completely eliminate
the need to “turn-around” the data bus required with common
I/O devices. Access to each port is accomplished through a
common address bus. Addresses for Read and Write
addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the device’s Read and Write ports are
completely independent of one another. In order to maximize
data throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with four 18-bit words (CY7C1305BV25) and four
36-bit words (CY7C1307BV25) that burst sequentially into or
out of the device. Since data can be transferred into and out
of the device on every rising edge of both input clocks (K/K

) memory bandwidth is maximized while simplifying

C/C
system design by eliminating bus “turn-arounds.”

Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled
by the K or K
registers controlled by the C or C
conducted with on-chip synchronous self-timed write circuitry.

input clocks. All data outputs pass through output

input clocks. Writes are

and

• CY7C1305BV25 – 1M x 18

• CY7C1307BV25 – 512K x 36

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05630 Rev. *A Revised April 3, 2006

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Logic Block Diagram (CY7C1305BV25)

D

A

[17:0]

[17:0]

18

18

Address
Register

Write

Reg

256Kx18 Array

Write

Reg

256Kx18 Array

Write

Reg

256Kx18 Array

Write

Reg

256Kx18 Array

Address
Register

CY7C1305BV25
CY7C1307BV25

A

(17:0)

18

K
K

CLK

Gen.

Write Add. Decode

Vref
WPS
BWS

[0:1]

Control
Logic

Logic Block Diagram (CY7C1307BV25)

D

A

(16:0)

[35:0]

17

K
K

36

Address
Register

CLK

Gen.

Write Add. Decode

Read Data Reg.

Write

Write

Reg

Reg

128K x 36 Array

128K x 36 Array

Read Data Reg.

72

36

36

Write

Write

Reg

Reg

128K x 36 Array

128K x 36 Array

Read Add. Decode

Read Add. Decode

Reg.

Reg.

Control
Logic

Reg.

Address
Register

Control
Logic

18

17

RPS

C
C

RPS

C
C

18

A

Q

(16:0)

[17:0]

144

72

72

Reg.

Reg.

Reg.

36

36

Q

[35:0]

Vref
WPS
BWS

[0:3]

Control
Logic

Selection Guide

CY7C1305BV25-167
CY7C1307BV25-167 Unit

Maximum Operating Frequency 167 MHz
Maximum Operating Current 400 mA

Document #: 38-05630 Rev. *A Page 2 of 21

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CY7C1305BV25
CY7C1307BV25

\

Pin Configuration

165-ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1305BV25 (1M x 18)

1 2 3 4567891011

A NC GND/ 144M NC/ 36M WPS
B NC Q9 D9 A NC K BWS
C NC NC D10 VSS A NC A VSS NC Q7 D8
D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7
E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6
F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5
G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5
H NC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4
K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3
L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2
M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2
N NC D17 Q16 VSS A A A VSS NC NC D1
P NC NC Q17 A A C A A NC D0 Q0
R TDO TCK A A A C

BWS

K NC RPS A GND/ 72M NC

1

ANCNCQ8

0

AAATMSTDI

CY7C1307BV25 (512K x 36)

12 34567891011

A NC GND/ 288M NC/ 72M WPS
B Q27 Q18 D18 A BWS
C D27 Q28 D19 VSS A NC A VSS D16 Q7 D8
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6
F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5
G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5
H NC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4
K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3
L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2
M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2
N D34 D26 Q25 VSS A A A VSS Q10 D9 D1
P Q35 D35 Q26 A A C A A Q9 D0 Q0
R TDO TCK A A A C

BWS

K BWS

2

KBWS0AD17Q17 Q8

3

AAATMSTDI

RPS NC/ 36M GND/ 144 M NC

1

Document #: 38-05630 Rev. *A Page 3 of 21

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CY7C1305BV25
CY7C1307BV25

Pin Definitions

Name I/O Description

D

[x:0]

Input-

Synchronous

WPS Input-

Synchronous

BWS
BWS

, BWS1,

0

, BWS

2

3

Input-

Synchronous

A Input-

Synchronous

Q

[x:0]

Outputs-

Synchronous

RPS Input-

Synchronous

C Input-Clock Positive Input Clock for Output Data. C is used in conjunction with C

C

Input-Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the

K Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs

K

Input-Clock Negative Input Clock Input. K is used to capture synchronous inputs to the device and

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the

TDO Output TDO pin for JTAG
TCK Input TCK pin for JTAG
TDI Input TDI pin for JTAG
TMS Input TMS pin for JTAG

Data input signals, sampled on the rising edge of K and K clocks during valid write
operations.

CY7C1305BV25 – D
CY7C1307BV25 – D

[17:0]
[35:0]

Write Port Select, active LOW. Sampled on the rising edge of the K clock. When
asserted active, a Write operation is initiated. Deassertin g will deselect the Write port.
Deselecting the Write port will cause D

to be ignored.

[x:0]

Byte Write Select 0, 1, 2, and 3–active LOW. Sampled on the rising edge of the K and
K

clocks during Write operations. Used to select which byte is written into the device
during the current portion of the Write operations. Bytes not written remain unaltered.
CY7C1305BV25 - BWS0 controls D
CY7C1307BV25 - BWS0 controls D
and BWS
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a

controls D

3

[35:27]

and BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

[17:9].

, BWS2 controls D

[17:9]

[26:18]

Byte Write Select will cause the corresponding byte of data to be ignored and not written
into the device.

Address Inputs. Sampled on the rising edge of the K clock during active Read and Write
operations. These address inputs are multiplexed for both Read and Write operations.
Internally, the device is organized as 1M x 18 (4 arrays each of 256K x 18) for
CY7C1305BV25 and 512K x 36 (4 arrays each of 128K x 36) for CY7C1307BV25.
Therefore, only 18 address inputs for CY7C1305BV25 and 17 address inputs for
CY7C1307BV25. These inputs are ignored when the appropriate port is deselected.

Data Output signals. These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C
operations or K and K

are automatically three-stated.

Q

[x:0]

CY7C1305BV25 - Q
CY7C1307BV25 - Q

when in single clock mode. When the Read port is deselected,

[17:0]
[35:0]

clocks during Read

Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K).
When active, a Read operation is initiated. Deasserting will cause the Read port to be
deselected. When deselected, the pending access is allowed to complete and the output
drivers are automatically three-stated following the next rising edge of the C clock. Each
read access consists of a burst of four sequential 18-bit or 36-bit transfers.

to clock out the

Read data from the device. C and C

can be used together to deskew the flight times of
various devices on the board back to the controller. See application example for further
details.

Read data from the device. C and C

can be used together to deskew the flight times of
various devices on the board cack to the controller. See application example for further
details.

to the device and to drive out data through Q
are initiated on the rising edge of K.

to drive out data through Q

system data bus impedance. Q
a resistor connected between ZQ and ground. Alternately, this pin can be connected
directly to V
connected directly to VSS or left unconnected.

, which enables the minimum impedance mode. This pin cannot be

DDQ

when in single clock mode.

[x:0]

output impedance are set to 0.2 x RQ, where RQ is

[x:0]

when in single clock mode. All accesses

[x:0]

Document #: 38-05630 Rev. *A Page 4 of 21

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CY7C1305BV25
CY7C1307BV25

Pin Definitions (continued)

Name I/O Description

NC/36M N/A Address expansion for 36M. This is not connected to the die. Can be connected to any

voltage level on CY7C1305BV25/CY7C1307BV25.

GND/72M Input Address expansion for 72M. This sh ould be tied LOW on the CY7C1305BV2 5 .
NC/72M N/A Address expansion for 72M. This can be connected to any voltage level on

GND/144M Input Address expansion for 144M. This should be tied LOW on

GND/288M Input Address expansion for 144M. This should be tied LOW on CY7C1307BV25.
V

V
V
V

REF

DD
SS
DDQ

Input-

Reference

Power Supply Power supply inputs to the cor e of the de vi ce

Ground Ground for the device

Power Supply Power supply inputs for the outputs of the device

NC N/A Not connected to the die. Can be tied to any voltage level.

CY7C1307BV25.

CY7C1305BV25/CY7C1307BV25.

Reference Voltage Input. Static input used to set the reference level for HSTL inputs
and Outputs as well as AC measurement points.

Introduction

Functional Overview

The CY7C1305BV25/CY7C1307BV25 are synchronous
pipelined Burst SRAMs equipped with both a Read port and a
Write port. The Read port is dedicated to Read operations and
the Write Port is dedicated to Write operations. Data flows into
the SRAM through the Write port and out through the Read
port. These devices multiplex the address inputs in order to
minimize the number of address pins required. By having
separate Read and Write ports, the device completely elimi­nates the need to “turn-around” the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of four 18-bit data transfers in the case
of CY7C1305BV25 and four 36-bit data transfers in the case
of CY7C1307BV25, in two clock cycles.

Accesses for both ports are initiated on the rising edge of the
positive input clock (K). All synchronous input timing is refer­enced from the rising edge of the input clocks (K and K
all output timing is referenced to the rising edge of output
clocks (C and C, or K and K when in single clock mode).

All synchronous data inputs (D
registers controlled by the rising edge of input clocks (K and

). All synchronous data outputs (Q

K
registers controlled by the rising edge of the output clocks (C

) pass through input

[x:0]

) pass through output

[x:0]

and C, or K and K when in single clock mode).
All synchronous control (RPS

, WPS, BWS

through input registers controlled by the rising e dge of input

) inputs pass

[0:x]

clocks (K and K).
CY7C1305BV25 is described in the following sections. The

same basic descriptions apply to CY7C1307BV25.

Read Operations

The CY7C1305BV25 is organized internally as 4 arrays of
256K x 18. Accesses are completed in a burst of four
sequential 18-bit data words. Read operations are initiated by
asserting RPS
Clock (K). The address presented to Address inputs are stored

active at the rising edge of the Positive Input

in the Read address register. Following the next K clock rise
the corresponding lowest order 18-bit word of data is driven
onto the Q

using C as the output timing reference. On the

[17:0]

) and

subsequent rising edge of C
onto the Q
words have been driven out onto Q

. This process continues until all four 18-bit data

[17:0]

will be valid 2.5 ns from the rising e dge of the output clock
(C and C

, or K and K when in single clock mode, 250-MHz

the next 18-bit data word is driven

. The requested data

[17:0]

device). In order to maintain the internal logic, each Read
access must be allowed to complete. Each Read access
consists of four 18-bit data words and takes 2 clock cycles to
complete. Therefore, Read accesses to the device can not be
initiated on two consecutive K clock rises. The internal logic of
the device will ignore the second Read request. Read
accesses can be initiated on every other K clock rise. Doing
so will pipeline the data flow such that data is transferred out
of the device on every rising edge of the output clocks (C and
C,

or K and K when in single clock mode).

When the read port is deselected, the CY7C1305BV25 will first
complete the pending read transactions. Synchronous internal
circuitry will automatically three-state the outputs following the
next rising edge of the positive output clock (C). This will allow
for a seamless transition between devices without the
insertion of wait states in a depth expanded memory.

Write Operations

Write operations are initiated by asserting WPS

active at the
rising edge of the positive input clock (K). On the following K
clock rise the data presented to D
into the lower 18-bit Write Data register provided BWS
both asserted active. On the subsequent rising edge of the
negative input clock (K

) the information presented to D
also stored into the Write Data Register provided BWS
both asserted active. This process continues for one more

is latched and stored

[17:0]

[1:0]

[17:0]

[1:0]

are

is

are

cycle until four 18-bit words (a total of 72 bits) of data are
stored in the SRAM. The 72 bits of data are then written into
the memory array at the specified location. Therefore, Write
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device wil l ignore the
second Write request. Write accesses can be initiated on
every other rising edge of the positive clock (K). Doing so will
pipeline the data flow such that 18-bits of data can be trans­ferred into the device on every rising edge of the input cl ocks
(K and K

).

Document #: 38-05630 Rev. *A Page 5 of 21

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CY7C1305BV25
CY7C1307BV25

When deselected, the write port will ignore all inputs after the
pending Write operations have been completed.

Byte Write Operations

Byte Write operations are supported by the CY7C1305BV25.
A write operation is initiated as described in the Write
Operation section above. The bytes that are written are deter­mined by BWS0 and BWS1, which are sampled with each set
of 18-bit data word. Asserting the appropriate Byte Write
Select input during the data portion of a write will allow the data
being presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that b yte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.

Single Clock Mode

The CY7C1305BV25 can be used with a single clock that
controls both the input and output registers. In this mode the
device will recognize only a single pair of input clocks (K and
K

) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C
a strap option and not alterable during device operation.

Concurrent Transactions

The Read and Write ports on the CY7C1305BV25 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the trans­action on the other port. If the ports access the same location
at the same time, the SRAM will deliver the most recent infor­mation associated with the specified address location. This

Application Example

HIGH at power-on. This function is

[1]

includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.

Read and Write accesses must be scheduled such that one
transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on
the previous state of the SRAM. If both ports were deselected,
the Read port will take priority. If a Read was initiated on the
previous cycle, the Write port will assume priority (since Read
operations can not be initiated on consecutive cycles). If a
Write was initiated on the previous cycle, the Read port will
assume priority (since Write operations can not be initiated on
consecutive cycles). Therefore, asserting both port selects
active from a deselected state will result in alternating
Read/Write operations being initiated, with the first access
being a Read.

Depth Expansion

The CY7C1305BV25 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the positive input clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and V
output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω
V

=1.5V. The output impedance is adjusted every 1024

DDQ

cycles upon power-up to account for drifts in supply voltage
and temperature.

to allow the SRAM to adjust its

SS

, with

Note:

1. The above application shows four QDR-I being used.

Document #: 38-05630 Rev. *A Page 6 of 21

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CY7C1305BV25
CY7C1307BV25

Truth Table

[2, 3, 4, 5, 6, 7, 8, 9]

Operation K RPS WPS DQ DQ DQ DQ

Write Cycle:

Load address on the rising

L-H H

[8]

[9]

L

D(A+00) at
K(t+1) ↑

D(A+01) at
K

(t+1) ↑

D(A+10) at
K(t+2) ↑

D(A+11) at

K(t+2) ↑
edge of K; wait one cycle;
input write data on two
consecutive K and K

rising

edges.
Read Cycle:

Load address on the rising

L-H L

[9]

X Q(A+00) at

C(t+1) ↑

Q(A+01) at
C

(t+1) ↑

Q(A+10) at
C(t+2) ↑

Q(A+11) at

C(t+2) ↑
edge of K; wait one cycle;
read data on two consec­utive C and C

NOP: No operation L-H H H D = X

rising edges.

Q = High-Z

D = X
Q = High-Z

D = X
Q = High-Z

D = X

Q = High-Z

Standby: Clock stopped Stopped X X Previous state Previous state Previous state Previous state

Write Cycle Descriptions (CY7C1305BV25)

BWS0BWS

L L L-H – During the Data portion of a Write sequence, both bytes (D
L L – L-H During the Data portion of a Write sequence, both bytes (D
L H L-H – During the Data portion of a Write sequence, only the lower byte (D

L H – L-H During the Data portion of a Write sequence, only the lower byte (D

H L L -H – During the Data portion of a Write sequence, only the upper byte (D

H L – L-H During the Data portion of a Write sequence, only the upper byte (D

KK Comments

1

device. D

device. D

[17:9]

[17:9]

the device. D

the device. D

[2, 10]

will remain unaltered.

will remain unaltered.

will remain unaltered.

[8:0]

will remain unaltered.

[8:0]

) are written into the device.

[17:0]

) are written into the device.

[17:0]

) is written into the

[8:0]

) is written into the

[8:0]

) is written into

[17:9]

) is written into

[17:9]

H H L-H – No data is written into the device during this portion of a Write operation.
H H – L-H No data is written into the device during this portion of a Write operation.

Notes:

2. X = Don't Care, H = Logic HIGH, L = Logic LOW,

3. Device will power-up deselected and the outputs in a three-state condition.

4. “A” represents address location latched by the devices when transaction was initiated. A+00, A+01, A+1 0 and A+1 1 represents the address sequence in the burst.

5. “t” represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively succeeding the “t” clock cycle.

6. Data inputs are registered at K and K

7. It is recommended that K = K
symmetrically.

8. If this signal was LOW to initiate the previous cycle, this signal becomes a don’t care for this operation.

9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will
ignore the second Read request.

10.Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS
the case of CY7C1307BV25 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved.

rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission li ne charging

↑represents rising edge.

and BWS1 in the case of CY7C1305BV25 and BWS2 and BWS3 in

0

Document #: 38-05630 Rev. *A Page 7 of 21

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