Cypress CY7C1306BV25, CY7C1303BV25 User Manual

Q

tecture

CY7C1303BV25

CY7C1306BV25

18-Mbit Burst of 2 Pipelined SRAM with

DR™ Archi

Features

• Separate independent Read and Write data ports
— Supports concurrent tra nsactions

• 167-MHz Clock for high bandwidth
— 2.5 ns Clock-to-Valid access time

• 2-Word Burst on all accesses

• Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 333 MHz) @167 MHz

• Two input clocks (K and K
— SRAM uses rising edg es only

• Two input clocks for output dat a (C and C
clock-skew and flight-time mismatches.

• Single multiplexed address input bus latches address
inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• 2.5V core power supply with HSTL Inputs and Outputs

• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

• Variable drive HSTL output buffers

• Expanded HSTL output voltage (1.4V–1.9V)

• JT A G In terface

• Variable Impedance HSTL

) for precise DDR timing

) to minimize

Configurations

CY7C1303BV25 – 1M x 18
CY7C1306BV25 – 512K x 36

Functional Description

The CY7C1303BV25 and CY7C1306BV25 are 2.5V
Synchronous Pipelined SRAMs equipped with QDR™ archi­tecture. QDR architecture consists of two separate ports to
access the memory array. The Read port has dedicated Data
Outputs to support Read operations and the Write Port has
dedicated Data inputs to support Write operations. Access to
each port is accomplished through a common address bus.
The Read address is latched on the rising edge of the K clock
and the Write address is latched on the rising edge of K
QDR has separate data inputs and data outputs to completely
eliminate the need to “turn-around” the data bus required with
common I/O devices. Accesses to the CY7C1303BV25/
CY7C1306BV25 Read and Write ports are completely
independent of one another. All accesses are initiated
synchronously on the rising edge of the positive input clock
(K). In order to maximize data throughput, both Read and
Write ports are equipped with Double Data Rate (DDR) inter­faces. Therefore, data can be transferred into the device on
every rising edge of both input clocks (K and K
device on every rising edge of the output clock (C and C
and K

when in single clock mode) thereby maximizing perfor­mance while simplifying system design. Each address location
is associated with two 18-bit words (CY7C1303BV25) or two
36-bit words (CY7C1306BV25) that burst sequentially into or
out of the device.

Depth expansion is accomplished with a Port Select input for
each port. Each Port Selects allow each port to operate
independently.

All synchronous inputs pass through input registers controlled
by the K or K
registers controlled by the C or C
conducted with on-chip synchronous self-timed write circuitry.

input clocks. All data outputs pass through output

input clocks. Writes are

) and out of the

clock.

, or K

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05627 Rev. *A Revised April 3, 2006

[+] Feedback

Logic Block Diagram (CY7C1303BV25)

D

A

(18:0)

Vref

WPS
BWS

BWS

[17:0]

19

K
K

0
1

18

Address
Register

CLK
Gen.

Control
Logic

Write
Data Reg

512Kx18
Memory

Array

Write Add. Decode

Read Data Reg.

512Kx18
Memory

Array

36

Write
Data Reg

18

18

Read Add. Decode

Reg.

Reg.

Address
Register

Control
Logic

Reg.

18

CY7C1303BV25
CY7C1306BV25

A

(18:0)

19

RPS

C
C

18

18

Q

[17:0]

Logic Block Diagram (CY7C1306BV25)

D

A

(17:0)

Vref

WPS
BWS

BWS

BWS
BWS

[35:0]

18

K
K

0
1

2
3

36

Address
Register

CLK
Gen.

Control
Logic

Write
Data Reg

256Kx36
Memory

Array

Write Add. Decode

Read Data Reg.

Write
Data Reg

256Kx36
Memory

Array

72

36

36

Read Add. Decode

Reg.

Reg.

Address
Register

Control
Logic

Reg.

36

36

18

RPS

C
C

36

A

(17:0)

Q

[35:0]

Selection Guide

CY7C1303BV25-167
CY7C1306BV25-167 Unit

Maximum Operating Frequency 167 MHz
Maximum Operating Current 500 mA

Document #: 38-05627 Rev. *A Page 2 of 19

[+] Feedback

CY7C1303BV25
CY7C1306BV25

Pin Configuration

165-ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1303BV25 (1M x 18)

1 2 34567891011

A NC Gnd/ 144M NC/ 36M WPS
B NC Q9 D9 A NC K BWS
C NC NC D10 VSS A A A VSS NC Q7 D8
D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7
E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6
F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5
G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5
H NC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4
K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3
L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2
M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2
N NC D17 Q16 VSS A A A VSS NC NC D1
P NC NC Q17 A A C A A NC D0 Q0
R TDO TCK A A A C

BWS

1

K NC RPS A Gnd/ 72M NC

ANCNCQ8

0

AAATMSTDI

CY7C1306BV25 (512K x 36)

1 2 34567891011

A NC Gnd/ 288M NC/72M WPS
B Q27 Q18 D18 A BWS
C D27 Q28 D19 VSS A A A VSS D16 Q7 D8
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6
F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5
G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5
H NC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4
K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3
L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2
M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2
N D34 D26 Q25 VSS A A A VSS Q10 D9 D1
P Q35 D35 Q26 A A C A A Q9 D0 Q0
R TDO TCK A A A C

BWS

2
3

K BWS
KBWS0AD17Q17Q8

AAATMSTDI

RPS NC/36M Gnd/ 144M NC

1

Document #: 38-05627 Rev. *A Page 3 of 19

[+] Feedback

CY7C1303BV25
CY7C1306BV25

Pin Definitions

Name I/O Description

D

[x:0]

Input-

Synchronous

WPS Input-

Synchronous

BWS
BWS

, BWS1,

0

, BWS

2

Input-

Synchronous

3

A Input-

Synchronous

Q

[x:0]

Outputs-

Synchronous

RPS Input-

Synchronous

C Input-Clock Positive Input Clock for Output Data. C is used in conjunction with C

C

Input-Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read

K Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the

K

Input-Clock Negative Input Clock Input. K is used to capture synchronous inputs to the device and to drive

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system

TDO Output TDO pin for JTAG.
TCK Input TCK pin for JTAG.
TDI Input TDI pin for JTAG.
TMS Input TMS pin for JTAG.

Data input signals, sampled on the rising edge of K and K clocks during valid write opera­tions.

CY7C1303BV25 – D
CY7C1306BV25 – D

[17:0]
[35:0]

Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active,
a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port
will cause D

to be ignored.

[x:0]

Byte Write Select 0, 1, 2 and 3 - active LOW. Sampled on the rising edge of the K and K clocks
during Write operations. Used to select which byte is written into the device during the current
portion of the Write operations.
CY7C1303BV25 - BWS
CY7C1306BV25 - BWS0 controls D
controls D
Bytes not written remain unaltered. Deselecting a Byte Write Select will cause the corresponding

[35:27]

controls D

0

and BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

[17:9].

, BWS2 controls D

[17:9]

[26:18]

and BWS3

byte of data to be ignored and not written into the device.
Address Inputs. Sampled on the rising edge of the K clock during active Read operations and

on the rising edge of K

for Write operations. These address inputs are multiplexed for both Read
and Write operations. Internally, the device is organized as 1M x 18 (2 arrays each of 512K x 18)
for CY7C1303BV25 and 512K x 36 (2 arrays each of 256K x 36) for CY7C1306BV25. Therefore,
only 19 address inputs are needed to access the entire memory array of CY7C1303BV25 and
18 address inputs for CY7C1306BV25. These inputs are ignored when the appropriate port is
deselected.

Data Output signals. These pins drive out the requested data during a Read operation. Valid
data is driven out on the rising edge of both the C and C
K

when in single clock mode. When the Read port is deselected, Q
three-stated.
CY7C1303BV25 - Q
CY7C1306BV25 - Q

[17:0]
[35:0]

clocks during Read operations or K and

are automatically

[x:0]

Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K). When
active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
three-stated following the next rising edge of the K clock. Each read access consists of a burst
of two sequential 18-bit or 36-bit transfers.

to clock out the Read

data from the device. C and C

can be used together to deskew the flight times of various devices

on the board back to the controller. See application example for further details.

data from the device. C and C

can be used together to deskew the flight times of various devices

on the board back to the controller. See application example for further details.

device and to drive out data through Q
on the rising edge of K.

out data through Q

data bus impedance. Q
connected between ZQ and ground. Alternately, this pin can be connected directly to V

when in single clock mode.

[x:0]

output impedance are set to 0.2 x RQ, where RQ is a resistor

[x:0]

enables the minimum impedance mode. This pin cannot be connected directly to GND or left

when in single clock mode. All accesses are initiated

[x:0]

DDQ

, which

unconnected.

Document #: 38-05627 Rev. *A Page 4 of 19

[+] Feedback

CY7C1303BV25
CY7C1306BV25

Pin Definitions (continued)

Name I/O Description

NC/36M N/A Address expansion for 36M. This pin is not connected to the die and so can be tied to any

GND/72M Input Address expansion for 72M. This pin has to be tied to GND on CY7C1303BV25.
NC/72M N/A Address expansion for 72M. This pin can be tied to any voltage level on CY7C1306BV25.
GND/144M Input Address expansion for 144M. This pin has to be tied to GND on

GND/288M Input Address expansion for 288M. This pin has to be tied to GND on CY7C1306BV25.
NC N/A Not connected to the die. Can be tied to any voltage level.
V

V
V
V

REF

DD
SS
DDQ

Input-

Reference

Power Supply Power supply inputs to the core of the device.

Ground Ground for the device.

Power Supply Power supply inputs for the outputs of the device.

voltage level on CY7C1303BV25/CY7C1306BV25.

CY7C1303BV25/CY7C1306BV25.

Reference V oltage Input. S tatic input used to set the reference level for HSTL inputs and Outputs
as well as AC measurement points.

Introduction

Functional Overview

The CY7C1303BV25/CY7C1306BV25 are synchronous
pipelined Burst SRAM equipped with both a Read port and a
Write port. The Read port is dedicated to Read operations and
the Write port is dedicated to Write operations. Data flows into
the SRAM through the Write port and out through the Read
port. These devices multiplex the address inputs in order to
minimize the number of address pins required. By having
separate Read and Write ports, this architecture completely
eliminates the need to “turn-around” the data bus and avoids
any possible data contention, thereby simplifying system
design. 38-05627Each access consists of two 18-bit data
transfers in the case of CY7C1303BV25, and two 36-bit data
transfers in the case of CY7C1306BV25, in one clock cycle.

Accesses for both ports are initiated on the rising edge of the
Positive Input Clock (K). All synchronous input timing is refer­enced from the rising edge of the input clocks (K and K
all output timings are referenced to rising edge of output clocks
(C and C

All synchronous data inputs (D
registers controlled by the rising edge of the input clocks (K
and K
output registers controlled by the rising edge of the output
clocks (C and C

All synchronous control (RPS
through input registers controlled by the rising e dge of input
clocks (K and K

or K and K when in single clock mode).

) pass through input

[x:0]

). All synchronous data outputs (Q

, or K and K when in single clock mode).

, WPS, BWS

).

) pass through

[x:0]

) inputs pass

[x:0]

The following descriptions take CY7C1303BV25 as an
example. The same basic descriptions apply to
CY7C1306BV25.

Read Operations

The CY7C1303BV25 is organized internally as 2 arrays of
512K x 18. Accesses are completed in a burst of two
sequential 18-bit data words. Read operations are initiated by
asserting RPS

active at the rising edge of the positive input
clock (K). The address is latched on the rising edge of the K
clock. Following the next K clock rise the corresponding lower
order 18-bit word of data is driven onto the Q

[17:0]

) and

using C as

the output timing reference. On the subsequent rising edge of
C

the higher order data word is driven onto the Q

requested data will be valid 2.5 ns from the rising edge of the

[17:0]

. The

output clock (C and C, or K and K when in single clock mode,
250-MHz device).

Synchronous internal circuitry will automatically three-state
the outputs following the next rising edge of the positive output
clock (C). This will allow for a seamless transition between
devices without the insertion of wait states in a depth
expanded memory.

Write Operations

Write operations are initiated by asserting WPS

active at the
rising edge of the positive input clock (K). On the same K clock
rise the data presented to D
lower 18-bit Write Data register provided BWS
asserted active. On the subsequent rising edge of the negative
input clock (K
presented to D
provided BWS
are then written into the memory array at the specified

), the address is latched and the information

is stored into the Write Data register

[17:0]

are both asserted active. The 36 bits of data

[1:0]

is latched and stored into the

[17:0]

[1:0]

are both

location.
When deselected, the Write port will ignore all inputs after the

pending Write operations have been completed.

Byte Write Operations

Byte Write operations are supported by the CY7C1303BV25.
A Write operation is initiated as described in the Write
Operation section above. The bytes that are written are deter­mined by BWS0 and BWS1 which are sampled with each set
of 18-bit data word. Asserting the appropriate Byte Write
Select input during the data portion of a write will allow the data
being presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.

Single Clock Mode

The CY7C1303BV25 can be used with a single clock mode. In
this mode the device will recognize only the pair of input clocks
(K and K

) that control both the input and output registers. This

Document #: 38-05627 Rev. *A Page 5 of 19

[+] Feedback

CY7C1303BV25
CY7C1306BV25

operation is identical to the operation if the device had zero
skew between the K/K

and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C

HIGH at power-up.This function is

a strap option and not alterable during device operation.

Concurrent Transactions

The Read and Write ports on the CY7C1303BV25 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the trans­action on the other port. Also, reads and writes can be started
in the same clock cycle. If the ports access the same location
at the same time, the SRAM will deliver the most recent infor­mation associated with the specified address location. This
includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.

Application Example

[1]

Depth Expansion

The CY7C1303BV25 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the Positive Input Clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and V
output driver impedance. The value of RQ must be 5X the

to allow the SRAM to adjust its

SS

value of the intended line impedance driven by the SRAM, The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω
V

=1.5V. The output impedance is adjusted every 1024

DDQ

cycles to account for drifts in supply voltage and temperature.

, with

Truth Table

[2, 3, 4, 5, 6, 7]

Operation K RPS WPS DQ DQ

Write Cycle:
Load address on the rising edge of K
data on K and K

rising edges.

clock; input write

Read Cycle:
Load address on the rising edge of K clock; wait one
cycle; read data on 2 consecutive C and C

rising edges.

NOP: No Operation L-H H H D = X

Standby: Clock Stopped Stopped X X Previous

Notes:

1. The above application shows 4 QDR-I being used.

2. X = Don't Care, H = Logic HIGH, L = Logic LOW, ↑represents rising edge.

3. Device will power-up deselected and the outputs in a three-state condition.

4. “A” represents address location latched by the devices when transaction was initiated. A+0, A+1 represent the addresses sequence in the burst.

5. “t” represents the cycle at which a Read/Write operation is started. t+1 is the first clock cycle succeeding the “t” clock cycle.

6. Data inputs are registered at K and K

7. It is recommended that K = K
symmetrically.

rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission li ne charging

L-H X L D(A+0) at

K(t) ↑

L-H L X Q(A+0) at

C(t+1)↑

Q = High-Z

State

D(A+1) at
K

(t) ↑

Q(A+1) at
C

(t+1) ↑

D = X
Q = High-Z

Previous
State

Document #: 38-05627 Rev. *A Page 6 of 19

[+] Feedback