Cypress CY7C1302DV25 User Manual

Q
CY7C1302DV25
9-Mbit Burst of Two Pipelined SRAMs
• Separate independent Read and Write data ports — Supports concurrent tra nsactions
• 167-MHz clock for high bandwidth — 2.5 ns Clock-to-Valid access time
• 2-word burst on all accesses
• Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 333 MHz) @ 167 MHz
• Two input clocks (K and K
) for precise DDR timing
— SRAM uses rising edg es only
• Two input clocks for output dat a (C and C
) to minimize
clock-skew and flight-time mismatches.
• Single multiplexed address input bus latches address inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 2.5V core power supply with HSTL Inputs and Outputs
• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JT A G In terface
Configurations
CY7C1302DV25 – 512K x 18
with
DR™ Architecture
Functional Description
The CY7C1302DV25 is a 2.5V Synchronous Pipelined SRAM equipped with QDR™ architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated data outputs to support Read operations and the Write Port has dedicated data inputs to support Write operations. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of K data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Accesses to the CY7C1302DV25 Read and Write ports are completely independent of one another. All accesses are initiated synchronously on the rising edge of the positive input clock (K). In order to maximize data throughput, both Read and Write ports are equipped with DDR interfaces. Therefore, data can be transferred into the device on every rising edge of both input clocks (K and K edge of the output clock (C and C domain) thereby maximizing performance while simplifying system design. Each address location is associated with two 18-bit words that burst sequentially into or out of the device.
Depth expansion is accomplished with a Port Select input for each port. Each Port Select allows each port to operate independently.
All synchronous inputs pass through input registers controlled by the K or K registers controlled by the C or C domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
clock. QDR has separate data inputs and
) and out of the device on every rising
, or K and K in a single clock
input clocks. All data outputs pass through output
(or K or K in a single clock
Logic Block Diagram (CY7C1302DV25)
D
[17:0]
A
(17:0)
18
K
Vref
WPS BWS
0
BWS
1
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document #: 38-05625 Rev. *A Revised March 23, 2006
18
Address Register
CLK Gen.K
Control Logic
Write Data Reg
256Kx18 Memory Array
Write Add. Decode
Read Data Reg.
Write Data Reg
256Kx18 Memory Array
36
18
18
Read Add. Decode
Reg.
Reg.
Address Register
Control Logic
Reg.
18
18
18
RPS
C C
18
A
(17:0)
Q
[17:0]
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CY7C1302DV25
Selection Guide
CY7C1302DV25-167 Unit
Maximum Operating Frequency 167 MHz Maximum Operating Current 500 mA
Pin Configuration
165-ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1302DV25 (512K x 18)
1 2 34567891011
A NC Gnd/144M NC/36M WPS B NC Q9 D9 A NC K BWS C NC NC D10 VSS A A A VSS NC Q7 D8 D NC D11 Q10 VSS VSS VSS VSS VSS NC NC D7 E NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 F NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 G NC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5 H NC VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
J NC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4 K NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 L NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 M NC NC D16 VSS VSS VSS VSS VSS NC Q1 D2 N NC D17 Q16 VSS A A A VSS NC NC D1 P NC NC Q17 A A C A A NC D0 Q0 R TDOTCKAAAC
BWS
1
K NC RPS NC/18M Gnd/72M NC
0
ANCNCQ8
AAATMSTDI
Pin Definitions
Name I/O Description
D
[17:0]
WPS
Input-
Synchronous
Input-
Synchronous
BWS BWS
,
0 1
Input-
Synchronous
A Input-
Synchronous
Q
[17:0]
RPS
Outputs-
Synchronous
Input-
Synchronous
Data input signals, sampled on the rising edge of K and K clocks during valid Write opera­tions.
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active,
a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D
to be ignored.
[17:0]
Byte Write Select 0, 1, active LOW. Sampled on the rising edge of the K and K clocks during Write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered. BWS
controls D
0
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
and BWS1 controls D
[8:0]
[17:9].
Select will cause the corresponding byte of data to be ignored and not written into the device. Address Inputs. Sampled on the rising edge of the K (read address) and K
for active Read and Write operations. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 512K x 18 (2 arrays each of 256K x 18). These inputs are ignored when the appropriate port is deselected.
Data Output signal s. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C when in single clock mode. When the Read port is deselected, Q three-stated.
Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K). When active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically three-stated following the next rising edge of the C clock. Each read access consists of a burst of two sequential transfers.
(write address) clocks
clocks during Read operations or K and K
are automatically
[17:0]
Document #: 38-05625 Rev. *A Page 2 of 18
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CY7C1302DV25
Pin Definitions (continued)
Name I/O Description
C Input-
Clock
Positive Input Clock for Output Data. C is used in conjunction with C from the device. C and C
can be used together to deskew the flight times of various devices on
the board back to the controller. See application example for further details.
C Input-Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read data
from the device. C and C
can be used together to deskew the flight times of various devices on
the board cack to the controller. See application example for further details.
K Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q on the rising edge of K.
K
Input-Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q
when in single clock mode. All accesses are initiated
[17:0]
when in single clock mode.
[17:0]
ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. Q between ZQ and ground. Alternately, this pin can be connected directly to V
output impedance is set to 0.2 x RQ, where RQ is a resistor connected
[17:0]
the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. TDO Output TDO for JTAG. TCK Input TCK pin for JTAG. TDI Input TDI pin for JTAG. TMS Input TMS pin for JTAG. NC/18M N/A Address expansion for 18M. This is not connected to the die and so can be tied to any voltage
level. NC/36M N/A Address expansion for 36M. This is not connected to the die and so can be tied to any voltage
level. GND/72M Input Address expansion for 72M. This must be tied LOW. GND/144M Input Address expansion for 144M. This must be tied LOW. NC N/A Not connected to the die. Can be tied to any voltage level. V
V V V
REF
DD SS DDQ
Input-
Reference
Power Supply Power supply inputs to the core of the device.
Ground Grou nd for the device.
Power Supply Power supply inputs for the outputs of the device.
Reference Volt age Input. Static input used to set the reference level for HSTL inputs and Outputs
as well as AC measurement points.
to clock out the Read data
, which enables
DDQ
Introduction
Functional Overview
The CY7C1302DV25 is a synchronous pipelined Burst SRAM equipped with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate Read and Write ports, the QDR-I completely eliminates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. 38-05625
Accesses for both ports are initiated on the rising edge of the Positive Input Clock (K). All synchronous input timing is refer­enced from the rising edge of the input clocks (K and K all output timing is referenced to the output clocks (C and C, or K and K when in single clock mode).
All synchronous data inputs (D registers controlled by the input clocks (K and K
) pass through input
[17:0]
) and
). All
synchronous data outputs (Q registers controlled by the rising edge of the output clocks (C and C
, or K and K when in single clock mode).
All synchronous control (RPS through input registers controlled by the rising edge of input clocks (K and K
).
Read Operations
The CY7C1302DV25 is organized internally as 2 arrays of 256K x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting RPS
active at the rising edge of the positive input clock (K). The address is latched on the rising edge of the K clock. Following the next K clock rise the corresponding lower order 18-bit word of data is driven onto the Q the output timing reference. On the subsequent rising edge of
the higher order data word is driven onto the Q
C requested data will be valid 2.5 ns from the rising edge of the output clock (C and C
, or K and K when in single clock mode,
167-MHz device).
) pass through output
[17:0]
, WPS, BWS
[1:0]
[17:0]
) inputs pass
using C as
. The
[17:0]
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CY7C1302DV25
Synchronous internal circuitry will automatically three-state the outputs following the next rising edge of the positive output clock (C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the rising edge of the positive input clock (K). On the same K clock rise the data presented to D Write Data register provided BWS active. On the subsequent rising edge of the negative input
is latched into the lower 18-bit
[17:0]
are both asserted
[1:0]
clock (K), the address is latched and the information presented to D BWS written into the memory array at the specified location.
is stored into the Write Data register provided
[17:0]
are both asserted active. The 36 bits of data are then
[1:0]
When deselected, the Write port will ignore all inputs after the pending Write operations have been completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1302DV25. A Write operation is initiated as described in the Write Operation section above. The bytes that are written are deter­mined by BWS of 18-bit data word. Asserting the appropriate Byte Write
and BWS1 which are sampled with each set
0
Select input during the data portion of a write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that b yte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation. 38-05625
Single Clock Mode
The CY7C1302DV25 can be used with a single clock mod e. In this mode the device will recognize only the pair of input clocks (K and K
Application Example
) that control both the input and output
[1]
registers. This operation is identical to the operation if the device had zero skew between the K/K
and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C
HIGH at power-up.This function is a strap option and not alterable during device operation.
Concurrent Tr a ns a ct ion s
The Read and Write ports on the CY7C1302DV25 operate completely independently of one another. Since each port latches the address inputs on different clock edges, the user can Read or Write to any location, regardless of the trans­action on the other port. Also, reads and writes can be started in the same clock cycle. If the ports access the same location at the same time, the SRAM will deliver the most recent infor­mation associated with the specified address location. This includes forwarding data from a Write cycle that was initiated on the previous K clock rise.
Depth Expansion
The CY7C1302DV25 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). Each port select input can deselect the specified port. Deselecting a port will not affect the other port. All pending transactions (Read and Write) will be completed prior to the device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V output driver impedance. The value of RQ must be 5X the
to allow the SRAM to adjust its
SS
value of the intended line impedance driven by the SRAM, The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175 and 350 =1.5V . The output impedance is adjusted every 1024 cycles to
, with V
DDQ
account for drifts in supply voltage and temperature.
Note:
1. The above application shows 4 QDR-I being used.
Document #: 38-05625 Rev. *A Page 4 of 18
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CY7C1302DV25
Truth Table
[2, 3, 4, 5, 6, 7]
Operation K RPS WPS DQ DQ
Write Cycle:
L-H X L D(A+0) at K(t) D(A+1) at K
(t) Load address on the rising edge of K clock; input write data on K and K
rising
edges. Read Cycle:
L-H L X Q(A+0) at C(t+1) Q(A+1) at C
(t+1) Load address on the rising edge of K clock; wait one cycle; read data on 2 consecutive C and C rising edges.
NOP: No Operation L-H H H D = X
Q = High-Z
D = X
Q = High-Z
Standby: Clock Stopped Stopped X X Previous State Previous State
Write Cycle Descriptions
BWS0BWS
L L L-H During the Data portion of a Write sequence, both bytes (D L L L-H During the Data portion of a Write sequence, both bytes (D L H L-H During the Data portion of a Write sequence, only the lower byte (D
L H L-H During the Data portion of a Write sequence, only the lower byte (D
H L L-H During the Data portion of a Write sequence, only the byte (D
H L L-H During the Data portion of a Write sequence, only the byte (D
KK Comments
1
[2,8]
device. D
device. D
D
[8:0]
D
[8:0]
[17:9]
[17:9]
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
) are written into the device.
[17:0]
) are written into the device.
[17:0]
) is written into the
[8:0]
) is written into the
[8:0]
) is written into the device.
[17:9]
) is written into the device.
[17:9]
H H L-H No da ta is written into the device during this portion of a Write operation. H H L-H No da ta is written into the device during this portion of a Write operation.
Notes:
2. X = Don't Care, H = Logic HIGH, L = Logic LOW,
3. Device will power-up deselected and the outputs in a three-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A+0, A+1 represent the addresses sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t+1 is the first clock cycle succeeding the “t” clock cycle.
6. Data inputs are registered at K and K
7. It is recommended that K = K symmetrically. 38-05625
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS as the set-up and hold requirements are achieved. 38-05625
rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission li ne charging
represents rising edge.
, BWS1 can be altered on different portions of a Wri te cycle, as l ong
0
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CY7C1302DV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-1900. The TAP operates using JEDEC standard 2.5V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (V
) to prevent clocking of the device. TDI and TMS are inter-
SS
nally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the T AP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction codes). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (V edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the
) for five rising
DD
TDI and TDO pins as shown in TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.
When the TAP controller is in the Capture IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (V
) when the BYPASS instruction is executed.
SS
Boundary Scan Register
The boundary scan register is connected to all of the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices.
The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc­tions can be used to capture the contents of the Input and Output ring.
The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table.
TAP Instruction Set
Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instruc­tions are described in detail below.
Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction
Document #: 38-05625 Rev. *A Page 6 of 18
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