Cypress CY7C1298H User Manual

CY7C1298H

1-Mbit (64K x 18) Pipelined DCD Sync SRAM

Features

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)
— Depth expansion without wait state

• 64K × 18-bit common I/O architecture

• 3.3V core power supply (V

• 2.5V/3.3V I/O power supply (V

• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel
Pentium

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous Output Enable

• Available in JEDEC-standard lead-free 100-Pin TQFP
package

• “ZZ” Sleep Mode option

®

interleaved or linear burst sequences

DD

)

DDQ

)

®

Functional Description

The CY7C1298H SRAM integrates 64K x 18 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE

), depth-expansion Chip Enables (CE2 and CE3), Burst

1

Control inputs (ADSC
(BW
inputs include the Output Enable (OE

Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
Address Strobe Controller (ADSC
burst addresses can be internally generated as controlled by
the Advance pin (ADV

Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two bytes wide as
controlled by the byte write control inputs. GW
causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal­izing system performance.

The CY7C1298H operates from a +3.3V core power supply
while all outputs operate either with a +2.5V or +3.3V supply.
All inputs and outputs are JEDEC-standard
JESD8-5-compatible.

, and BWE), and Global Write (GW). Asynchronous

[A:B]

).

[1]

, ADSP, and ADV), Write Enables

) and the ZZ pin.

) or

) are active. Subsequent

active LOW

Selection Guide

166 MHz 133 MHz Unit

Maximum Access Time 3.5 4.0 ns
Maximum Operating Current 240 225 mA
Maximum CMOS Standby Cur rent 40 40 mA

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05665 Rev. *B Revised July 5, 2006

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Functional Block Diagram

A
B

A

CY7C1298H

0, A1, A

MODE

ADV

CLK

ADSC
ADSP

BW

B

BW

A

BWE

GW

CE

1

CE

2

CE

3

ADDRESS
REGISTER

2

A

Q1

BURST

COUNTER AND

LOGIC

CLR

Q0

DQ

B,

DQP

B

BYTE

WRITE REGISTER

DQ

A ,

DQP

A

BYTE

WRITE REGISTER

ENABLE

REGISTER

PIPELINED

ENABLE

[1:0]

DQ

B ,

DQP

B

BYTE

WRITE DRIVER

MEMORY

DQ

A,

DQP

A

ARRAY

BYTE

WRITE DRIVER

SENSE
AMPS

OUTPUT

REGISTERS

OUTPUT
BUFFERS

E

INPUT

REGISTERS

DQ

s,

DQP
DQP

OE

ZZ

SLEEP

CONTROL

Document #: 38-05665 Rev. *B Page 2 of 16

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Pin Configurations

CY7C1298H

100-Pin TQFP

Top View

NC
NC
NC

V

DDQ

V

SSQ

NC

NC
DQ
DQ

V

SSQ

V

DDQ

DQ
DQ

NC

V

NC

V
DQ
DQ

V

DDQ

V

SSQ

DQ
DQ

DQP

NC

V

SSQ

V

DDQ

NC
NC
NC

DD

SS

1CE2

A

100

A

99

NCNCBWBBW

CE

97969594939291

98
1
2
3
4

5
6

7

B
B

8
9

10
11

B
B

12
13
14
15

16
17

B
B

18
19
20
21

B
B
B

22
23
24
25
26
27
28
29
30

A

CE3VDDV

SS

CLKGWBWEOEADSC

90

898887

CY7C1298H

ADSP

ADV

8584838281

86

A

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

A

A
NC
NC
V

DDQ

V

SSQ

NC
DQP

A

DQ

A

DQ

A

V

SSQ

V

DDQ

DQ

A

DQ

A

V

SS

NC
V

DD

ZZ
DQ

A

DQ

A

V

DDQ

V

SSQ

DQ

A

DQ

A

NC
NC
V

SSQ

V

DDQ

NC
NC
NC

31323334353637383940414243444546474849

A

MODE

A

1A0

A

A

A

SS

V

NC/36M

NC/72M

V

DD

A

NC/9M

NC/18M

A

A

A

50

A

NC/4M

NC/2M

Document #: 38-05665 Rev. *B Page 3 of 16

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CY7C1298H

Pin Descriptions

Pin Type Description

, A Input-

A0, A

BW

GW

1

[A:B]

Synchronous

Input-

Synchronous

Input-

Synchronous

BWE

Input-

Synchronous

CLK Input-

Clock

CE

CE

CE

OE

1

2

3

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Asynchronous

ADV

Input-

Synchronous

ADSP

Input-

Synchronous

ADSC

Input-

Synchronous

ZZ Input-

Asynchronous

DQs
DQP

V

DD

V

SS

V

DDQ

V

SSQ

[A:B]

I/O-

Synchronous

Power Supply Power supply inputs to the core of the device.

Ground Ground for the core of the device.

I/O Power

Supply

I/O Ground Ground for the I/O circuitry.

MODE Input-

Static

NC No Connects. Not internally connected to the die. 2M, 4M, 9M, 18M, 72M, 144M, 288M, 576M and

Address Inputs used to select one of the 64K address locations. Sampled at the rising edge
of the CLK if ADSP

or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A

fed to the two-bit counter.

[1:0]

are

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW

and BWE).

[A:B]

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV

is asserted LOW, during a burst operation.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE

and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only

2

when a new external address is loaded.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

CE

and CE3 to select/deselect the device. CE

1

is sampled only when a new external address is

2

loaded.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE

and CE2 to select/deselect the device. CE3 is sampled only when a new external address is

1

loaded.
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When

LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE

is masked during the first clock of a read cycle when emerging from a deselected

state.
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it

automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When

asserted LOW, addresses presented to the device are captured in the address registers. A
also loaded into the burst counter. When ADSP
nized. ASDP

is ignored when CE1 is deasserted HIGH.

and ADSC are both asserted, only ADSP is recog-

[1:0]

are

Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A
also loaded into the burst counter. When ADSP

and ADSC are both asserted, only ADSP is recog-

[1:0]

are

nized.
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical

“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. The ZZ pin has an internal pull-down.

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by the addresses presented during the previous clock rise of the read cycle. The direction of the
pins is controlled by OE
and DQP

are placed in a tri-state condition.

[A:B]

. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs

Power supply for the I/O circuitry.

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V

floating selects interleaved burst sequence. This is a strap pin and should remain static during

DD

or left

device operation. Mode Pin has an internal pull-up.

1G are address expansion pins and are not internally connected to the die.

Document #: 38-05665 Rev. *B Page 4 of 16

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CY7C1298H

Functional Overview

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.

The CY7C1298H supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486‰
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.

Byte write operations are qualified with the Byte Write Enable
(BWE

) and Byte Write Select (BW
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.

Synchronous Chip Selects CE
asynchronous Output Enable (OE
selection and output tri-state control. ADSP
is HIGH.

Single Read Accesses

This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP
chip selects are all asserted active, and (3) the write signals
(GW

, BWE) are all deasserted HIGH. ADSP is ignored if CE
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre­sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within t
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always tri-stated during the
first cycle of the access. After the first cycle of the access, the
outputs are controlled by the OE
read cycles are supported.

The CY7C1298H is a double-cycle deselect part. Once the
SRAM is deselected at clock rise by the chip select and either
ADSP

or ADSC signals, its output will tri-state immediately

after the next clock rise.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP
(2) chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
The write signals (GW
ignored during this first cycle.

ADSP

triggered write accesses require two clock cycles to
complete. If GW
data presented to the DQx inputs is written into the corre­sponding address location in the memory core. If GW
then the write operation is controlled by BWE

) or the Controller Address Strobe (ADSC).

) inputs. A Global Write

[A:B]

, CE2, CE3 and an

1

) provide for easy bank

is ignored if CE

or ADSC is asserted LOW, (2)

if OE is active LOW. The only exception

co

signal. Consecutive single

is asserted LOW, and

, BWE, and BW

) and ADV inputs are

[A:B]

is asserted LOW on the second clock rise, the

is HIGH,

and BW

[A:B]

signals. The CY7C1298H provides byte write capability that
is described in the Write Cycle Description table. Asserting the
Byte Write Enable input (BWE) with the selected Byte Write
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided
to simplify the write operations.

Because the CY7C1298H is a common I/O device, the Output
Enable (OE
to the DQ
a safety precaution, DQ are automatically tri-stated whenever

) must be deasserted HIGH before presenting data

inputs. Doing so will tri-state the output drivers. As

a write cycle is detected, regardless of the state of OE.

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following condi­tions are satisfied: (1) ADSC

is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW
and BW
desired byte(s). ADSC

) are asserted active to conduct a write to the

[A:B]

triggered write accesses require a
single clock cycle to complete. The address presented is
loaded into the address register and the address
advancement logic while bei ng d elive re d to the m emory co re.
The ADV input is ignored during this cycle. If a global write is
conducted, the data presented to the DQ
corresponding address location in the memory core. If a byte

1

write is conducted, only the selected bytes are written. Bytes

is written into the

X

not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.

Because the CY7C1298H is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ

1

a safety precaution, DQ
whenever a write cycle is detected, regardless of the state of

inputs. Doing so will tri-state the output drivers. As

X

are automatically tri-stated

X

OE.

Burst Sequences

The CY7C1298H provides a two-bit wraparound counter, fed
by A
sequence. The interleaved burst sequence is designed specif-

, that implements either an interleaved or linear burst

[1:0]

ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user se lectable
through the MODE input. Both read and write burst operations
are supported

Asserting ADV

LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
inactive for the duration of t
LOW.

s, ADSP, and ADSC must remain

after the ZZ input returns

ZZREC

, BWE,

Document #: 38-05665 Rev. *B Page 5 of 16

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