Cypress CY7C1294DV18, CY7C1292DV18 User Manual
CY7C1292DV18
CY7C1294DV18
9-Mbit QDR- II™ SRAM 2-Word
Burst Architecture
Features
• Separate Independent Read and Write data ports
— Supports concurrent tra nsactions
• 250-MHz clock for high bandwidth
• 2-Word Burst on all accesses
• Double Data Rate (DDR) interfaces on both Read and
Write ports (data transferred at 500 MHz) @ 250 MHz
• Two input clocks (K and K
— SRAM uses rising edg es only
• Two input clocks for output dat a (C and C
clock-skew and flight-time mismatches
• Echo clocks (CQ and CQ
high-speed systems
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• Available in x 18 and x 36 configurations
• Full data coherency, providing most current data
•Core V
• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
• Offered in both lead-free and non-lead free packages
• Variable drive HSTL output buffers
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
= 1.8V (±0.1V); I/O V
DD
) for precise DDR timing
) to minimize
) simplify data capture in
= 1.4V to V
DDQ
DD
Functional Description
The CY7C1292DV18 and CY7C1294DV18 are 1.8V
Synchronous Pipelined SRAMs, equipped with QDR™-II
architecture. QDR-II architecture consists of two separate
ports to access the memory array. The Read port has
dedicated Data Outputs to support Read operations and the
Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data
outputs to completely eliminate the need to “turn-around” the
data bus required with common I/O devices. Access to each
port is accomplished through a common address bus. The
Read address is latched on the rising edge of the K clock and
the Write address is latched on the rising edge of the K
Accesses to the QDR-II Read and Write ports are completely
independent of one another. In order to maximize data
throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with two 18-bit words (CY7C1292DV18) or 36-bit
words (CY7C1294DV18) that burst sequentially into or out of
the device. Since data can be transferred into and out of the
device on every rising edge of both input clocks (K and K
C and C
system design by eliminating bus “turn-arounds.”
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K
registers controlled by the C or C
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
), memory bandwidth is maximized while simplifying
input clocks. All data outputs pass through output
(or K or K in a single clock
clock.
and
Configurations
CY7C1292DV18 – 512K x 18
CY7C1294DV18 – 256K x 36
Selection Guide
250 MHz 200 MHz 167 MHz Unit
Maximum Operating Frequency 250 200 167 MHz
Maximum Operating Current 600 550 500 mA
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-00350 Rev. *A Revised July 20, 2006
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Logic Block Diagram (CY7C1292DV18)
D
[17:0]
18
Address
A
(17:0)
18
Register
Write
Reg
256K x 18 Array
CY7C1292DV18
CY7C1294DV18
Write
Reg
256K x 18 Array
Address
Register
18
A
(17:0)
K
K
CLK
Gen.
DOFF
V
REF
WPS
BWS
[1:0]
Control
Logic
Logic Block Diagram (CY7C1294DV18)
D
[35:0]
36
Address
A
(16:0)
DOFF
17
K
K
Register
CLK
Gen.
Write Add. Decode
Read Data Reg.
Write
Reg
Write Add. Decode
Read Data Reg.
128K x 36 Array
36
18
Write
Reg
128K x 36 Array
18
Read Add. Decode
Reg.
Reg.
Read Add. Decode
Control
Logic
Reg.
Address
Register
Control
Logic
18
18
RPS
C
C
17
18
RPS
C
C
A
Q
[17:0]
(16:0)
CQ
CQ
CQ
Q
CQ
[35:0]
V
REF
WPS
BWS
[3:0]
Control
Logic
72
36
36
Reg.
Reg.
Reg.
36
36
36
Document #: 001-00350 Rev. *A Page 2 of 23
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Pin Configurations
165-ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1292DV18 (512K x 18)
CY7C1292DV18
CY7C1294DV18
A
B
C
D
E
F
G
H
K
L
M
N
P
R
A
B
C
D
E
F
G
H
K
L
M
N
P
R
J
2345671
CQ
DOFF
J
TDO
NC/144M NC/36M BWS
NC
NC
NC
NC V
NC
NC
NC
NC
NC
NC
NC
NC
Q9
NC
D11 V
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
D9
D10
Q10 V
Q11
D12
Q13 V
V
DDQ
D14
Q14
D15
D16
Q16
Q17
A
A NC
V
SS
V
SS
V
DDQ
V
DDQ
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
1
AAA
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
KWPS NC/288M
K
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
BWS
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
0
891011
NC/18M NC/72MRPS
A NC
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
NC
NC Q7 D8
V
NC
D6
NC
NC
REF
Q4
D3
NC
Q1
NC
D0
NC
NC
NC Q5
NC
V
DDQ
NC
NC
NC
NC D2
NC
NC
A
CQ
Q8
D7
Q6
D5
ZQ
D4V
Q3
Q2
D1
Q0
TDITMS
CY7C1294DV18 (256K x 36)
1
CQ
Q27
D27
D28
Q29
Q30
D30
DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
23
4
NC/288M NC/72M BWS
Q18
Q28
D20 V
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
D18
D19
Q19 V
Q20
D21
Q22 V
V
DDQ
D23
Q23
D24
D25
Q25
Q26
A
V
V
V
V
V
V
A
V
SS
V
SS
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
SS
V
SS
A
A
567
2
BWS
3
A NC/18M A
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
KWPS BWS
K
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
BWS
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
891011
SS
SS
SS
SS
NC/36M NC/144MRPS
Q17
D16 Q7 D8
Q16
Q15
D14 Q5
Q13
VDDQ
D12
Q12
D11
D10 D2
Q10
Q9
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
A
1
0
A D17
V
V
V
DDQ
V
DDQ
V
DDQ
V
DDQ
DDQ
V
DDQ
V
DDQ
V
V
A
A
CQ
Q8
D7
Q6
D5
ZQ
D4V
Q3
Q2
D1
Q0
TDITMS
Document #: 001-00350 Rev. *A Page 3 of 23
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CY7C1292DV18
CY7C1294DV18
Pin Definitions
Pin Name I/O Pin Description
D
[x:0]
Input-
Synchronous
WPS Input-
Synchronous
BWS0, BWS1,
BWS
, BWS
2
3
Input-
Synchronous
A Input-
Synchronous
Q
[x:0]
Outputs-
Synchronous
RPS Input-
Synchronous
C Input-Clock Positive Input Clock for Output Data. C is used in conjunction with C
C Input-Clock Negative Input Clock for Output Dat a. C is used in conjunction with C to clock out the Read
K Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
K
Input-Clock Negative Input Clock Input. The rising edge of K is used to capture synchronous inputs being
CQ Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the
CQ
Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the
ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system
Data input signals, sampled on the rising edge of K and K clocks during valid write
operations.
CY7C1292DV18 - D
CY7C1294DV18 - D
[17:0]
[35:0]
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted
active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the
Write port will cause D
to be ignored.
[x:0]
Byte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K and K clocks
during Write operations. Used to select which byte is written into the device during the current
portion of the Write operations. Bytes not written remain unaltered.
CY7C1292DV18 − BWS
CY7C1294DV18 − BWS
BWS
controls D
3
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
[35:27].
controls D
0
controls D
0
, BWS1 controls D
[8:0]
, BWS1 controls D
[8:0]
.
[17:9]
,BWS2 controls D
[17:9]
[26:18]
and
Select will cause the corresponding byte of data to be ignored and not written into the device.
Address Inputs. Sampled on the rising edge of the K (Read address) and K
(Write address)
clocks during active Read and Write operations. These address inputs are multiplexed for both
Read and Write operations. Internally, the device is organized as 512K x 18 (2 arrays each of
256K x 18) for CY7C1292DV18 and 256K x 36 (2 arrays each of 128K x 36) for CY7C1294DV18.
Therefore 18 address inputs for CY7C1292DV18 and 17 address inputs for CY7C1294DV18.
These inputs are ignored when the appropriate port is deselected.
Data Output signals. These pins drive out the requested data during a Read operation. Valid
data is driven out on the rising edge of both the C and C
and K
when in single clock mode. When the Read port is deselected, Q
tri-stated.
CY7C1292DV18 − Q
CY7C1294DV18 − Q
[17:0]
[35:0]
clocks during Read operations or K
are automatically
[x:0]
Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When
active, a Read operation is initiated. Deasserting will cause the Read port to be deselected.
When deselected, the pending access is allowed to complete and the output drivers are
automatically tri-stated following the next rising edge of the C clock. Each read access consists
of a burst of two sequential transfers.
to clock out the Read
data from the device. C and C
can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
data from the device. C
and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
device and to drive out data through Q
on the rising edge of K.
presented to the device and to drive out data through Q
when in single clock mode. All accesses are initiated
[x:0]
when in single clock mode.
[x:0]
input clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC Timing table.
input clock for output data (C
respect to K
. The timings for the echo clocks are shown in the AC Timing table.
data bus impedance. CQ, CQ
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to
V
, which enables the minimum impedance mode. This pin cannot be connected directly to
DDQ
GND or left unconnected.
) of the QDR-II. In the single clock mode, CQ is generated with
, and Q
output impedance are set to 0.2 x RQ, where RQ is a
[x:0]
Document #: 001-00350 Rev. *A Page 4 of 23
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Pin Definitions (continued)
Pin Name I/O Pin Description
DOFF
TDO Output TDO for JTAG.
TCK Input TCK pin for JTAG.
TDI Input TDI pin for JTAG.
TMS Input TMS pin for JTAG.
NC N/A Not connected to the die. Can be tied to any voltage level.
NC/18M N/A Not connected to the die. Can be tied to any voltage level.
NC/36M N/A Not connected to the die. Can be tied to any voltage level.
NC/72M N/A Not connected to the die. Can be tied to any voltage level.
NC/144M N/A Not connected to the die. Can be tied to any voltage level.
NC/288M N/A Not connected to the die. Can be tied to any voltage level.
V
REF
V
DD
V
SS
V
DDQ
Input DLL Turn Off, active LOW . Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
Input-
Reference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and
Outputs as well as AC measurement points.
Power Supply Power supply inputs to the core of the device.
Ground Ground for the device.
Power Supply Power supply inputs for the outputs of the device.
CY7C1292DV18
CY7C1294DV18
Functional Overview
The CY7C1292DV18 and CY7C1294DV18 are synch ronous
pipelined Burst SRAMs equipped with both a Read port and a
Write port. The Read port is dedicated to Read operations and
the Write port is dedicated to Write operations. Data flows into
the SRAM through the Write port and out through the Read
port. These devices multiplex the address inputs in order to
minimize the number of address pins required. By having
separate Read and Write ports, the QDR-II completely eliminates the need to “turn-around” the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of two 18-bit data transfers in the case
of CY7C1292DV18 and two 36-bit data transfers in the case
of CY7C1294DV18 in one clock cycle.
Accesses for both ports are initiated on the rising edge of the
positive Input Clock (K). All synchronous input timings are
referenced from the rising edge of the input clocks (K and K
and all output timings are referenced to the rising edge of
output clocks (C and C
All synchronous data inputs (D
registers controlled by the input clocks (K and K
synchronous data outputs (Q
registers controlled by the rising edge of the output clocks (C
and C
or K and K when in single clock mode).
All synchronous control (RPS
through input registers controlled by the rising edge of the
input clocks (K and K
CY7C1292DV18 is described in the following sections. The
same basic descriptions apply to CY7C1294DV18.
or K and K when in single clock mode).
) inputs pass through input
[x:0]
) outputs pass through output
[x:0]
, WPS, BWS
) inputs pass
[x:0]
). All
).
Read Operations
The CY7C1292DV18 is organized internally as 2 arrays of
256K x 18. Accesses are completed in a burst of two
sequential 18-bit data words. Read operations are initiated by
asserting RPS
Clock (K). The address is latched on the rising edge of the K
active at the rising edge of the Positive Input
Clock. The address presented to Address inputs is stored in
the Read address register. Following the next K clock rise the
corresponding lowest order 18-bit word of data is driven onto
the Q
subsequent rising edge of C, the next 18-bit data word is
driven onto the Q
ns from the rising edge of the output clock (C and C
K
when in single clock mode).
using C as the output timing reference. On the
[17:0]
. The requested data will be valid 0.45
[17:0]
Synchronous internal circuitry will automatically tri-state the
outputs following the next rising edge of the Output Clocks
(C/C
)
). This will allow for a seamless transition between
devices without the insertion of wait states in a depth
expanded memory.
Write Operations
Write operations are initiated by asserting WPS
active at the
rising edge of the Positive Input Clock (K). On the same K
clock rise, the data presented to D
into the lower 18-bit Write Data register provided BWS
is latched and stored
[17:0]
both asserted active. On the subsequent rising edge of the
Negative Input Clock (K), the address is latched and the information presented to D
register provided BWS
bits of data are then written into the memory array at the
is stored into the Write Data
[17:0]
are both asserted active. The 36
[1:0]
specified location. When deselected, the write port will ignore
all inputs after the pending Write operations have been
completed.
or K and
are
[1:0]
Document #: 001-00350 Rev. *A Page 5 of 23
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CY7C1292DV18
CY7C1294DV18
Byte Write Operations
Byte Write operations are supported by the CY7C1292DV18.
A Write operation is initiated as described in the Write Operations section above. The bytes that are written are determined
by BWS
word. Asserting the appropriate Byte Write Select input during
the data portion of a Write will allow the data being presented
to be latched and written into the device. Deasserting the Byte
Write Select input during the data portion of a write will allow
the data stored in the device for that byte to remain unaltered.
This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation.
Single Clock Mode
The CY7C1292DV18 can be used with a single clock that
controls both the input and output registers. In this mode, the
device will recognize only a single pair of input clocks (K and
K
) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power on. This function is
a strap option and not alterable during device operation.
Concurrent Transactions
The Read and Write ports on the CY7C1292DV18 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the transaction on the other port. Also, reads and writes can be started
in the same clock cycle. If the ports access the same location
at the same time, the SRAM will deliver the most recent information associated with the specified address location. This
includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.
and BWS1, which are sampled with each 18-bit data
0
and C/C clocks. All timing parameters
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and V
output driver impedance. The value of RQ must be 5x the
value of the intended line impedance driven by the SRAM. The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω
= 1.5V.The output impedance is adjusted every 1024
V
DDQ
cycles upon power-up to account for drifts in supply voltage
and temperature.
Echo Clocks
Echo clocks are provided on the QDR-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the QDR-II. CQ is referenced with respect to C
and CQ
free-running clocks and are synchronized to the output clock
(C/C
with respect to K and CQ
timings for the echo clocks are shown in the AC Timing table.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. During power-up, when the DOFF
DLL gets locked after 1024 cycles of stable clock. The DLL can
also be reset by slowing or stopping the input clock K and K
for a minimum of 30 ns. However, it is not necessary for the
DLL to be specifically reset in order to lock the DLL to the
desired frequency. The DLL will automatically lock 1024 clock
cycles after a stable clock is presented.the DLL may be
disabled by applying ground to the DOFF
refer to the application note “DLL Considerations in
QDRII/DDRII/QDRII+/DDRII+”.
is referenced with respect to C. These are
) of the QDR-II. In the single clock mode, CQ is generated
to allow the SRAM to adjust its
SS
, with
is generated with respect to K. The
is tied HIGH, the
pin. For information
Depth Expansion
The CY7C1292DV18 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the Positive Input Clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
Document #: 001-00350 Rev. *A Page 6 of 23
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CY7C1292DV18
CY7C1294DV18
Application Example
DATA IN
DATA OUT
Address
BUS
MASTER
(CPU
or
ASIC)
Truth Table
RPS#
WPS#
BWS#
CLKIN/CLKIN#
Source K
Source K#
Delayed K
Delayed K#
[2, 3, 4, 5, 6, 7]
[1]
Vt
R
R
D
A
R = 50οηµσ
SRAM #1
R
B
W
P
W
P
S
S
S
#
#
#
Vt = Vddq/2
CC#
CQ/CQ#
K
R = 250οηµσ
ZQ
Q
K#
SRAM #4
R
W
B
P
P
D
A
R
W
S
S
S
#
#
Vt
Vt
CC#
#
CQ/CQ#
K
R = 250οηµσ
ZQ
Q
K#
Operation K RPS WPS DQ DQ
Write Cycle:
Load address on the rising edge of K
data on K and K
rising edges.
Read Cycle:
clock; input write
L-H X L D(A + 0) at K(t) ↑ D(A + 1) at K(t) ↑
L-H L X Q(A + 0) at C(t + 1)↑ Q(A + 1) at C(t + 2) ↑
Load address on the rising edge of K clock; wait one
and a half cycle; read data on C
NOP: No Operation L-H H H D = X,
and C rising edges.
Q = High-Z
D = X,
Q = High-Z
Standby: Clock Stopped Stopped X X Previous State Previous State
Write Cycle Descriptions
(CY7C1292DV18)
[2, 8]
BWS
L L L-H – During the Data portion of a Write sequence: both bytes (D
L L – L-H During the Data portion of a Write sequence: both bytes (D
L H L-H – During the Data portion of a Write sequence: only the lower byte (D
L H – L-H During the Data portion of a Write sequence: only the lower byte (D
H L L-H – During the Data portion of a Write sequence: only the upper byte (D
H L – L-H During the Data portion of a Write sequence: only the upper byte (D
BWS
0
KK Comments
1
device. D
device. D
device. D
device. D
will remain unaltered.
[17:9]
will remain unaltered.
[17:9]
will remain unaltered.
[8:0]
will remain unaltered.
[8:0]
) are written into the device.
[17:0]
) are written into the device.
[17:0]
) is written into the
[8:0]
) is written into the
[8:0]
) is written into the
[17:9]
) is written into the
[17:9]
H H L-H – No data is written into the devices during this portion of a Write operation.
H H – L-H No data is written into the devices during this portion of a Write operation.
Notes:
1. The above application shows four QDR-II being used.
2. X = “Don't Care,” H = Logic HIGH, L= Logic LOW,
3. Device will power-up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and secon d clock cycles respectively succee ding the “t” clock cycle.
6. Data inputs are registered at K and K
7. It is recommended that K = K
charging symmetrically.
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Tr uth Table. NWS
portions of a Write cycle, as long as the set-up and hold requirements are achieved.
rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
↑represents rising edge.
, NWS1, BWS0, BWS1, BWS2 and BWS3 can be altered on different
0
Document #: 001-00350 Rev. *A Page 7 of 23
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