Cypress CY7C1294DV18, CY7C1292DV18 User Manual

CY7C1292DV18
CY7C1294DV18

9-Mbit QDR- II™ SRAM 2-Word

Burst Architecture

Features

• Separate Independent Read and Write data ports
— Supports concurrent tra nsactions

• 250-MHz clock for high bandwidth

• 2-Word Burst on all accesses

• Double Data Rate (DDR) interfaces on both Read and
Write ports (data transferred at 500 MHz) @ 250 MHz

• Two input clocks (K and K
— SRAM uses rising edg es only

• Two input clocks for output dat a (C and C
clock-skew and flight-time mismatches

• Echo clocks (CQ and CQ
high-speed systems

• Single multiplexed address input bus latches address
inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• Available in x 18 and x 36 configurations

• Full data coherency, providing most current data

•Core V

• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

• Offered in both lead-free and non-lead free packages

• Variable drive HSTL output buffers

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

= 1.8V (±0.1V); I/O V

DD

) for precise DDR timing

) to minimize

) simplify data capture in

= 1.4V to V

DDQ

DD

Functional Description

The CY7C1292DV18 and CY7C1294DV18 are 1.8V
Synchronous Pipelined SRAMs, equipped with QDR™-II
architecture. QDR-II architecture consists of two separate
ports to access the memory array. The Read port has
dedicated Data Outputs to support Read operations and the
Write Port has dedicated Data Inputs to support Write opera­tions. QDR-II architecture has separate data inputs and data
outputs to completely eliminate the need to “turn-around” the
data bus required with common I/O devices. Access to each
port is accomplished through a common address bus. The
Read address is latched on the rising edge of the K clock and
the Write address is latched on the rising edge of the K
Accesses to the QDR-II Read and Write ports are completely
independent of one another. In order to maximize data
throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with two 18-bit words (CY7C1292DV18) or 36-bit
words (CY7C1294DV18) that burst sequentially into or out of
the device. Since data can be transferred into and out of the
device on every rising edge of both input clocks (K and K
C and C
system design by eliminating bus “turn-arounds.”

Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled
by the K or K
registers controlled by the C or C
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.

), memory bandwidth is maximized while simplifying

input clocks. All data outputs pass through output

(or K or K in a single clock

clock.

and

Configurations

CY7C1292DV18 – 512K x 18
CY7C1294DV18 – 256K x 36

Selection Guide

250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 250 200 167 MHz
Maximum Operating Current 600 550 500 mA

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-00350 Rev. *A Revised July 20, 2006

[+] Feedback

Logic Block Diagram (CY7C1292DV18)

D

[17:0]

18

Address

A

(17:0)

18

Register

Write
Reg

256K x 18 Array

CY7C1292DV18
CY7C1294DV18

Write
Reg

256K x 18 Array

Address
Register

18

A

(17:0)

K
K

CLK
Gen.

DOFF

V

REF

WPS
BWS

[1:0]

Control

Logic

Logic Block Diagram (CY7C1294DV18)

D

[35:0]

36

Address

A

(16:0)

DOFF

17

K
K

Register

CLK

Gen.

Write Add. Decode

Read Data Reg.

Write
Reg

Write Add. Decode

Read Data Reg.

128K x 36 Array

36

18

Write
Reg

128K x 36 Array

18

Read Add. Decode

Reg.

Reg.

Read Add. Decode

Control

Logic

Reg.

Address
Register

Control

Logic

18

18

RPS

C
C

17

18

RPS

C
C

A

Q

[17:0]

(16:0)

CQ

CQ

CQ

Q

CQ

[35:0]

V

REF

WPS
BWS

[3:0]

Control

Logic

72

36

36

Reg.

Reg.

Reg.

36

36

36

Document #: 001-00350 Rev. *A Page 2 of 23

[+] Feedback

Pin Configurations

165-ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1292DV18 (512K x 18)

CY7C1292DV18
CY7C1294DV18

A
B
C
D

E
F
G

H

K
L
M
N
P

R

A
B
C
D

E
F
G

H

K
L
M
N
P

R

J

2345671

CQ

DOFF

J

TDO

NC/144M NC/36M BWS
NC
NC
NC

NC V
NC
NC

NC
NC
NC
NC
NC
NC

Q9
NC

D11 V

NC
Q12
D13

V

REF

NC

NC
Q15

NC

D17

NC
TCK

D9
D10
Q10 V
Q11
D12
Q13 V

V

DDQ

D14
Q14
D15
D16
Q16
Q17

A

A NC

V

SS

V

SS

V

DDQ

V

DDQ
DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

SS

V

SS

A

A

1

AAA

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

A
A
A

KWPS NC/288M
K

V

SS
SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

A
C

C

BWS

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

A
A
A

0

891011

NC/18M NC/72MRPS

A NC

V

SS

V

SS

V

DDQ

V

DDQ

V

DDQ

V

DDQ
DDQ

V

DDQ

V

DDQ

V

SS

V

SS

A
A

NC

NC Q7 D8

V

NC
D6
NC
NC

REF

Q4
D3
NC
Q1
NC
D0

NC
NC
NC Q5

NC

V

DDQ

NC
NC
NC
NC D2
NC
NC

A

CQ

Q8

D7
Q6

D5

ZQ

D4V
Q3
Q2

D1
Q0

TDITMS

CY7C1294DV18 (256K x 36)

1

CQ

Q27
D27
D28
Q29
Q30
D30

DOFF

D31
Q32
Q33
D33
D34
Q35

TDO

23

4

NC/288M NC/72M BWS

Q18
Q28

D20 V
D29

Q21

D22

V

REF

Q31

D32
Q24
Q34

D26

D35
TCK

D18
D19
Q19 V
Q20
D21
Q22 V

V

DDQ

D23
Q23
D24
D25
Q25
Q26

A

V
V

V
V
V
V

A

V

SS

V

SS
DDQ
DDQ

DDQ
DDQ
DDQ

DDQ
DDQ

V

SS

V

SS

A

A

567

2

BWS

3

A NC/18M A

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

A
A

A

KWPS BWS
K

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

A
C

C

BWS

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

A
A

A

891011

SS
SS

SS
SS

NC/36M NC/144MRPS

Q17
D16 Q7 D8
Q16
Q15
D14 Q5
Q13

VDDQ

D12
Q12
D11
D10 D2
Q10

Q9

D15

D6

Q14

D13

V

REF

Q4
D3

Q11

Q1
D9
D0

A

1
0

A D17
V
V

V

DDQ

V

DDQ

V

DDQ

V

DDQ
DDQ

V

DDQ

V

DDQ

V
V

A
A

CQ

Q8

D7
Q6

D5

ZQ

D4V
Q3
Q2

D1
Q0

TDITMS

Document #: 001-00350 Rev. *A Page 3 of 23

[+] Feedback

CY7C1292DV18
CY7C1294DV18

Pin Definitions

Pin Name I/O Pin Description

D

[x:0]

Input-

Synchronous

WPS Input-

Synchronous

BWS0, BWS1,
BWS

, BWS

2

3

Input-

Synchronous

A Input-

Synchronous

Q

[x:0]

Outputs-

Synchronous

RPS Input-

Synchronous

C Input-Clock Positive Input Clock for Output Data. C is used in conjunction with C

C Input-Clock Negative Input Clock for Output Dat a. C is used in conjunction with C to clock out the Read

K Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the

K

Input-Clock Negative Input Clock Input. The rising edge of K is used to capture synchronous inputs being

CQ Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the

CQ

Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system

Data input signals, sampled on the rising edge of K and K clocks during valid write
operations.

CY7C1292DV18 - D
CY7C1294DV18 - D

[17:0]
[35:0]

Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted
active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the
Write port will cause D

to be ignored.

[x:0]

Byte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K and K clocks
during Write operations. Used to select which byte is written into the device during the current
portion of the Write operations. Bytes not written remain unaltered.
CY7C1292DV18 − BWS
CY7C1294DV18 − BWS
BWS

controls D

3

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write

[35:27].

controls D

0

controls D

0

, BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

.

[17:9]

,BWS2 controls D

[17:9]

[26:18]

and

Select will cause the corresponding byte of data to be ignored and not written into the device.
Address Inputs. Sampled on the rising edge of the K (Read address) and K

(Write address)
clocks during active Read and Write operations. These address inputs are multiplexed for both
Read and Write operations. Internally, the device is organized as 512K x 18 (2 arrays each of
256K x 18) for CY7C1292DV18 and 256K x 36 (2 arrays each of 128K x 36) for CY7C1294DV18.
Therefore 18 address inputs for CY7C1292DV18 and 17 address inputs for CY7C1294DV18.
These inputs are ignored when the appropriate port is deselected.

Data Output signals. These pins drive out the requested data during a Read operation. Valid
data is driven out on the rising edge of both the C and C
and K

when in single clock mode. When the Read port is deselected, Q
tri-stated.
CY7C1292DV18 − Q
CY7C1294DV18 − Q

[17:0]
[35:0]

clocks during Read operations or K

are automatically

[x:0]

Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When
active, a Read operation is initiated. Deasserting will cause the Read port to be deselected.
When deselected, the pending access is allowed to complete and the output drivers are
automatically tri-stated following the next rising edge of the C clock. Each read access consists
of a burst of two sequential transfers.

to clock out the Read

data from the device. C and C

can be used together to deskew the flight times of various devices

on the board back to the controller. See application example for further details.

data from the device. C

and C can be used together to deskew the flight times of various devices

on the board back to the controller. See application example for further details.

device and to drive out data through Q
on the rising edge of K.

presented to the device and to drive out data through Q

when in single clock mode. All accesses are initiated

[x:0]

when in single clock mode.

[x:0]

input clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC Timing table.

input clock for output data (C
respect to K

. The timings for the echo clocks are shown in the AC Timing table.

data bus impedance. CQ, CQ
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to
V

, which enables the minimum impedance mode. This pin cannot be connected directly to

DDQ

GND or left unconnected.

) of the QDR-II. In the single clock mode, CQ is generated with

, and Q

output impedance are set to 0.2 x RQ, where RQ is a

[x:0]

Document #: 001-00350 Rev. *A Page 4 of 23

[+] Feedback

Pin Definitions (continued)

Pin Name I/O Pin Description

DOFF

TDO Output TDO for JTAG.
TCK Input TCK pin for JTAG.
TDI Input TDI pin for JTAG.
TMS Input TMS pin for JTAG.
NC N/A Not connected to the die. Can be tied to any voltage level.
NC/18M N/A Not connected to the die. Can be tied to any voltage level.
NC/36M N/A Not connected to the die. Can be tied to any voltage level.
NC/72M N/A Not connected to the die. Can be tied to any voltage level.
NC/144M N/A Not connected to the die. Can be tied to any voltage level.
NC/288M N/A Not connected to the die. Can be tied to any voltage level.
V

REF

V

DD

V

SS

V

DDQ

Input DLL Turn Off, active LOW . Connecting this pin to ground will turn off the DLL inside the device.

The timings in the DLL turned off operation will be different from those listed in this data sheet.

Input-

Reference

Reference Voltage Input. Static input used to set the reference level for HSTL inputs and
Outputs as well as AC measurement points.

Power Supply Power supply inputs to the core of the device.

Ground Ground for the device.

Power Supply Power supply inputs for the outputs of the device.

CY7C1292DV18
CY7C1294DV18

Functional Overview

The CY7C1292DV18 and CY7C1294DV18 are synch ronous
pipelined Burst SRAMs equipped with both a Read port and a
Write port. The Read port is dedicated to Read operations and
the Write port is dedicated to Write operations. Data flows into
the SRAM through the Write port and out through the Read
port. These devices multiplex the address inputs in order to
minimize the number of address pins required. By having
separate Read and Write ports, the QDR-II completely elimi­nates the need to “turn-around” the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of two 18-bit data transfers in the case
of CY7C1292DV18 and two 36-bit data transfers in the case
of CY7C1294DV18 in one clock cycle.

Accesses for both ports are initiated on the rising edge of the
positive Input Clock (K). All synchronous input timings are
referenced from the rising edge of the input clocks (K and K
and all output timings are referenced to the rising edge of
output clocks (C and C

All synchronous data inputs (D
registers controlled by the input clocks (K and K
synchronous data outputs (Q
registers controlled by the rising edge of the output clocks (C
and C

or K and K when in single clock mode).

All synchronous control (RPS
through input registers controlled by the rising edge of the
input clocks (K and K

CY7C1292DV18 is described in the following sections. The
same basic descriptions apply to CY7C1294DV18.

or K and K when in single clock mode).

) inputs pass through input

[x:0]

) outputs pass through output

[x:0]

, WPS, BWS

) inputs pass

[x:0]

). All

).

Read Operations

The CY7C1292DV18 is organized internally as 2 arrays of
256K x 18. Accesses are completed in a burst of two
sequential 18-bit data words. Read operations are initiated by
asserting RPS
Clock (K). The address is latched on the rising edge of the K

active at the rising edge of the Positive Input

Clock. The address presented to Address inputs is stored in
the Read address register. Following the next K clock rise the
corresponding lowest order 18-bit word of data is driven onto
the Q
subsequent rising edge of C, the next 18-bit data word is
driven onto the Q
ns from the rising edge of the output clock (C and C
K

when in single clock mode).

using C as the output timing reference. On the

[17:0]

. The requested data will be valid 0.45

[17:0]

Synchronous internal circuitry will automatically tri-state the
outputs following the next rising edge of the Output Clocks
(C/C

)

). This will allow for a seamless transition between
devices without the insertion of wait states in a depth
expanded memory.

Write Operations

Write operations are initiated by asserting WPS

active at the
rising edge of the Positive Input Clock (K). On the same K
clock rise, the data presented to D
into the lower 18-bit Write Data register provided BWS

is latched and stored

[17:0]

both asserted active. On the subsequent rising edge of the
Negative Input Clock (K), the address is latched and the infor­mation presented to D
register provided BWS
bits of data are then written into the memory array at the

is stored into the Write Data

[17:0]

are both asserted active. The 36

[1:0]

specified location. When deselected, the write port will ignore
all inputs after the pending Write operations have been
completed.

or K and

are

[1:0]

Document #: 001-00350 Rev. *A Page 5 of 23

[+] Feedback

CY7C1292DV18
CY7C1294DV18

Byte Write Operations

Byte Write operations are supported by the CY7C1292DV18.
A Write operation is initiated as described in the Write Opera­tions section above. The bytes that are written are determined
by BWS
word. Asserting the appropriate Byte Write Select input during
the data portion of a Write will allow the data being presented
to be latched and written into the device. Deasserting the Byte
Write Select input during the data portion of a write will allow
the data stored in the device for that byte to remain unaltered.
This feature can be used to simplify Read/Modify/Write opera­tions to a Byte Write operation.

Single Clock Mode

The CY7C1292DV18 can be used with a single clock that
controls both the input and output registers. In this mode, the
device will recognize only a single pair of input clocks (K and
K

) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power on. This function is
a strap option and not alterable during device operation.

Concurrent Transactions

The Read and Write ports on the CY7C1292DV18 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the trans­action on the other port. Also, reads and writes can be started
in the same clock cycle. If the ports access the same location
at the same time, the SRAM will deliver the most recent infor­mation associated with the specified address location. This
includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.

and BWS1, which are sampled with each 18-bit data

0

and C/C clocks. All timing parameters

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and V
output driver impedance. The value of RQ must be 5x the
value of the intended line impedance driven by the SRAM. The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω

= 1.5V.The output impedance is adjusted every 1024

V

DDQ

cycles upon power-up to account for drifts in supply voltage
and temperature.

Echo Clocks

Echo clocks are provided on the QDR-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the QDR-II. CQ is referenced with respect to C
and CQ
free-running clocks and are synchronized to the output clock
(C/C
with respect to K and CQ
timings for the echo clocks are shown in the AC Timing table.

DLL

These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. During power-up, when the DOFF
DLL gets locked after 1024 cycles of stable clock. The DLL can
also be reset by slowing or stopping the input clock K and K
for a minimum of 30 ns. However, it is not necessary for the
DLL to be specifically reset in order to lock the DLL to the
desired frequency. The DLL will automatically lock 1024 clock
cycles after a stable clock is presented.the DLL may be
disabled by applying ground to the DOFF
refer to the application note “DLL Considerations in
QDRII/DDRII/QDRII+/DDRII+”.

is referenced with respect to C. These are

) of the QDR-II. In the single clock mode, CQ is generated

to allow the SRAM to adjust its

SS

, with

is generated with respect to K. The

is tied HIGH, the

pin. For information

Depth Expansion

The CY7C1292DV18 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the Positive Input Clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.

Document #: 001-00350 Rev. *A Page 6 of 23

[+] Feedback

CY7C1292DV18
CY7C1294DV18

Application Example

DATA IN

DATA OUT

Address

BUS

MASTER

(CPU

or

ASIC)

Truth Table

RPS#

WPS#

BWS#

CLKIN/CLKIN#

Source K

Source K#

Delayed K

Delayed K#

[2, 3, 4, 5, 6, 7]

[1]

Vt

R

R

D
A

R = 50οηµσ

SRAM #1

R

B

W

P

W

P

S

S

S

#

#

#

Vt = Vddq/2

CC#

CQ/CQ#

K

R = 250οηµσ

ZQ

Q

K#

SRAM #4

R

W

B

P

P

D
A

R

W

S

S

S

#

#

Vt
Vt

CC#

#

CQ/CQ#

K

R = 250οηµσ

ZQ

Q

K#

Operation K RPS WPS DQ DQ

Write Cycle:
Load address on the rising edge of K
data on K and K

rising edges.

Read Cycle:

clock; input write

L-H X L D(A + 0) at K(t) ↑ D(A + 1) at K(t) ↑

L-H L X Q(A + 0) at C(t + 1)↑ Q(A + 1) at C(t + 2) ↑
Load address on the rising edge of K clock; wait one
and a half cycle; read data on C

NOP: No Operation L-H H H D = X,

and C rising edges.

Q = High-Z

D = X,
Q = High-Z

Standby: Clock Stopped Stopped X X Previous State Previous State

Write Cycle Descriptions

(CY7C1292DV18)

[2, 8]

BWS

L L L-H – During the Data portion of a Write sequence: both bytes (D
L L – L-H During the Data portion of a Write sequence: both bytes (D
L H L-H – During the Data portion of a Write sequence: only the lower byte (D

L H – L-H During the Data portion of a Write sequence: only the lower byte (D

H L L-H – During the Data portion of a Write sequence: only the upper byte (D

H L – L-H During the Data portion of a Write sequence: only the upper byte (D

BWS

0

KK Comments

1

device. D

device. D

device. D

device. D

will remain unaltered.

[17:9]

will remain unaltered.

[17:9]

will remain unaltered.

[8:0]

will remain unaltered.

[8:0]

) are written into the device.

[17:0]

) are written into the device.

[17:0]

) is written into the

[8:0]

) is written into the

[8:0]

) is written into the

[17:9]

) is written into the

[17:9]

H H L-H – No data is written into the devices during this portion of a Write operation.
H H – L-H No data is written into the devices during this portion of a Write operation.

Notes:

1. The above application shows four QDR-II being used.

2. X = “Don't Care,” H = Logic HIGH, L= Logic LOW,

3. Device will power-up deselected and the outputs in a tri-state condition.

4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.

5. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and secon d clock cycles respectively succee ding the “t” clock cycle.

6. Data inputs are registered at K and K

7. It is recommended that K = K
charging symmetrically.

8. Assumes a Write cycle was initiated per the Write Port Cycle Description Tr uth Table. NWS
portions of a Write cycle, as long as the set-up and hold requirements are achieved.

rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line

↑represents rising edge.

, NWS1, BWS0, BWS1, BWS2 and BWS3 can be altered on different

0

Document #: 001-00350 Rev. *A Page 7 of 23

[+] Feedback

CY7C1292DV18
CY7C1294DV18

Write Cycle Descriptions

(CY7C1294DV18)

[2, 8]

BWS0BWS1BWS2BWS3KK Comments

L L L L L-H - During the Data portion of a Write sequence, all four bytes (D

into the device.

L L L L - L-H During the Data portion of a Write sequence, all four bytes (D

into the device.

[35:0]

[35:0]

L H H H L-H - During the Data portion of a Write sequence, only the lower byte (D

into the device. D

will remain unaltered.

[35:9]

L H H H - L-H During the Data portion of a Write sequence, only the lower byte (D

into the device. D

H L H H L-H - During the Data portion of a Write sequence, only the byte (D

the device. D

[8:0]

H L H H - L-H During the Data portion of a Write sequence, only the byte (D

the device. D

[8:0]

H H L H L-H - During the Data portion of a Write sequence, only the byte (D

the device. D

[17:0]

H H L H - L-H During the Data portion of a Write sequence, only the byte (D

the device. D

[17:0]

H H H L L-H During the Data portion of a Write sequence, only the byte (D

the device. D

[26:0]

H H H L - L-H During the Data portion of a Write sequence, only the byte (D

the device. D

[26:0]

will remain unaltered.

[35:9]

and D

and D

and D

and D

will remain unaltered.

[35:18]

will remain unaltered.

[35:18]

will remain unaltered.

[35:27]

will remain unaltered.

[35:27]

will remain unaltered.

will remain unaltered.

[17:9]

[17:9]

[26:18]

[26:18]

[35:27]

[35:27]

H H H H L-H - No data is written into the device during this portion of a Write operation.
H H H H - L-H No data is written into the device during this portion of a Write operation.

) are written

) are written

) is written

[8:0]

) is written

[8:0]

) is written into

) is written into

) is written into

) is written into

) is written into

) is written into

Document #: 001-00350 Rev. *A Page 8 of 23

[+] Feedback

CY7C1292DV18
CY7C1294DV18

IEEE 1149.1 Serial Boundary Scan (JTAG)

These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-1 900. The TAP operates using
JEDEC standard 1.8V I/O logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V

) to prevent clocking of the device. TDI and TMS are inter-

SS

nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.

Test Access Port—Test Clock

The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.

Test Mode Select

The TMS input is used to give commands to the T AP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.

Test Data-Out (TDO)

The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.

TAP Registers

Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.

When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V

) when the BYPASS instruction is executed.

SS

Boundary Scan Register

The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.

The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc­tions can be used to capture the contents of the Input and
Output ring.

The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.

TAP Instruction Set

Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc­tions are described in detail below.

Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.

Document #: 001-00350 Rev. *A Page 9 of 23

[+] Feedback

CY7C1292DV18
CY7C1294DV18

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR sta te. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.

The user must be aware that the T AP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.

To guaran tee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (t
captured correctly if there is no way in a design to stop (o r
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK
boundary scan register.

Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.

and tCH). The SRAM clock input might not be

CS

captured in the

The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.

EXTEST

The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.

EXTEST OUTPUT BUS TRI-STATE

IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
pre-set LOW to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.

Reserved

These instructions are not implemented but are reserved for
future use. Do not use these instructions.

Document #: 001-00350 Rev. *A Page 10 of 23

[+] Feedback

CY7C1292DV18
CY7C1294DV18

TAP Controller State Diagram

1

TEST-LOGIC
RESET

0

0

TEST-LOGIC/

1

IDLE

[9]

1

SELECT
DR-SCAN

0

1

CAPTURE-DR

0

SHIFT-DR

1

EXIT1-DR

1

SELECT
IR-SCAN

0

1

CAPTURE-IR

0

0

SHIFT-IR

0

1

1

EXIT1-IR

1

0

PAUSE-DR

1

0

EXIT2-DR

1

UPDATE-DR

1

Note:

9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

0

0

PAUSE-IR

0

1

0

EXIT2-IR

1

UPDATE-IR

1

0

0

Document #: 001-00350 Rev. *A Page 11 of 23

[+] Feedback

TAP Controller Block Diagram

Selection
Circuitry

TDI

Bypass Register

Instruction Register

CY7C1292DV18
CY7C1294DV18

0

Selection

012

Circuitry

TDO

29

3031

012..

Identification Register

106

.

.

012..

Boundary Scan Register

TCK

TAP Controller

TMS

TAP Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Max. Unit

V

OH1

V

OH2

V

OL1

V

OL2

V

IH

V

IL

I

X

Notes:

10.These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.

11.Overshoot: V

12.All voltage referenced to Ground.

Output HIGH Voltage I
Output HIGH Voltage I

OH
OH

Output LOW Voltage IOL = 2.0 mA 0.4 V
Output LOW Voltage IOL = 100 µA0.2V
Input HIGH Voltage 0.65V
Input LOW Voltage –0.3 0.35V
Input and OutputLoad Current GND ≤ VI ≤ V

(AC) < V

IH

+0.85V (Pulse width less than t

DDQ

/2), Undershoot: VIL(AC) > –1.5V (Pulse width less than t

CYC

[10, 11, 12]

= −2.0 mA 1.4 V
= −100 µA1.6 V

V

+ 0.3 V

DD

DD

DD

DD

−55µA

/2).

CYC

V

Document #: 001-00350 Rev. *A Page 12 of 23

[+] Feedback

CY7C1292DV18
CY7C1294DV18

TAP AC Switching Characteristics Over the Operating Range

[13, 14]

Parameter Description Min. Max. Unit

t

TCYC

t

TF

t

TH

t

TL

TCK Clock Cycle Time 50 ns
TCK Clock Frequency 20 MHz
TCK Clock HIGH 20 ns
TCK Clock LOW 20 ns

Set-up Times

t

TMSS

t

TDIS

t

CS

TMS Set-up to TCK Clock Rise 5 ns
TDI Set-up to TCK Clock Rise 5 ns
Capture Set-up to TCK Rise 5 ns

Hold Times

t

TMSH

t

TDIH

t

CH

TMS Hold after TCK Clock Rise 5 ns
TDI Hold after Clock Rise 5 ns
Capture Hold after Clock Rise 5 ns

Output Times

t

TDOV

t

TDOX

TAP Timing and Test Conditions

TCK Clock LOW to TDO Valid 10 ns
TCK Clock LOW to TDO Invalid 0 ns

[13]

0.9V

TDO

= 50Ω

Z

0

GND

(a)

Test Clock
TCK

Test Mode Select
TMS

Test Data-In
TDI

Test Data-Out
TDO

C

50Ω

L

= 20 pF

t

TMSS

t

TDIS

ALL INPUT PULSES

1.8V

0V

TH

t

TL

t

TMSH

t

TDIH

t

0.9V

t

TCYC

t

Notes:

13.Test conditions are specified using the load in TAP AC test conditions. t
and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

14.t

CS

R/tF

= 1 ns.

TDOV

t

TDOX

Document #: 001-00350 Rev. *A Page 13 of 23

[+] Feedback

CY7C1292DV18
CY7C1294DV18

Identification Register Definitions

Value

Instruction Field

Revision Number (31:29) 000 000 Version number.
Cypress Device ID (28:12) 11010011010010110 11010011010100110 Defines the type of SRAM.
Cypress JEDEC ID (11:1) 00000110100 00000110100 Unique identification of SRAM vendor.
ID Register Presence (0) 1 1 Indicates the presence of an ID re gister.

Scan Register Sizes

Register Name Bit Size

Instruction 3
Bypass 1
ID 32
Boundary Scan Cells 107

Instruction Codes

Instruction Code Description

EXTEST 000 Captures the Input/Output ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between

TDI and TDO. This operation does not affect SRAM operation.

SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register

between TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register

between TDI and TDO. Does not affect the SRAM operation.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not

affect SRAM operation.

DescriptionCY7C1292DV18 CY7C1294DV18

Document #: 001-00350 Rev. *A Page 14 of 23

[+] Feedback

CY7C1292DV18
CY7C1294DV18

Boundary Scan Order

Bit # Bump ID Bit # Bump ID Bit # B ump ID Bit # Bump ID

0 6R 27 11H 54 7B 81 3G
1 6P 28 10G 55 6B 82 2G
26N 299G 566A 831J
3 7P 30 11F 57 5B 84 2J
4 7N 31 11G 58 5A 85 3K
57R 329F 594A 863J
6 8R 33 10F 60 5C 87 2K
7 8P 34 11E 61 4B 88 1K
8 9R 35 10E 62 3A 89 2L

9 11P 36 10D 63 1H 90 3L
10 10P 37 9E 64 1A 91 1M
11 10N 38 10C 65 2B 92 1L
12 9P 39 11D 66 3B 93 3N
13 10M 40 9C 67 1C 94 3M
14 11N 41 9D 68 1B 95 1N
15 9M 42 11B 69 3D 96 2M
16 9N 43 11C 70 3C 97 3P
17 11L 44 9B 71 1D 98 2N
18 11M 45 10B 72 2C 99 2P
19 9L 46 11A 73 3E 100 1P
20 10L 47 Internal 74 2D 101 3R
21 11K 48 9A 75 2E 102 4R
22 10K 49 8B 76 1E 103 4P
23 9J 50 7C 77 2F 104 5P
24 9K 51 6C 78 3F 105 5N
25 10J 52 8A 79 1G 106 5R
26 11J 53 7A 80 1F

Document #: 001-00350 Rev. *A Page 15 of 23

[+] Feedback

~

~

CY7C1292DV18
CY7C1294DV18

Power-Up Sequence in QDR-II SRAM

[16]

QDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.

Power-Up Sequence

• Apply power with DOFF

tied HIGH (All other inputs can be

HIGH or LOW)
—Apply V

—Apply V

before V

DD
DDQ

before V

DDQ

or at the same time as V

REF

REF

• Provide stable power and clock (K, K) for 1024 cycles to
lock the DLL.

Power-up Waveforms

K

K

Unstable Clock

Clock Start

(Clock Starts after Stable)

V

DLL Constraints

• DLL uses K clock as its synchronizing input. The input
should have low phase jitter, which is specified as t

• The DLL will function at frequencies down to 80 MHz.

• If the input clock is unstable and the DLL is enabled, then
the DLL may lock onto an incorrect frequency, causing
unstable SRAM behavior. T o avoid this, provide 1024 cycles
stable clock to relock to the desired clock frequency.

~

~

> 1024 Stable clock

Start Normal
Operation

/

V

DDQ

DD

KC Var

.

/

V

V

DD

DDQ

/

V

DD

Stable (< +/- 0.1V DC per 50ns )

V

DDQ

Fix High (or tied to V

DOFF

Notes:

15.It is recommended that the DOFF

16.During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.

pin be pulled HIGH via a pull up resistor of 1Kohm.

DDQ

)

Document #: 001-00350 Rev. *A Page 16 of 23

[+] Feedback

CY7C1292DV18
CY7C1294DV18

Maximum Ratings

(Above which the useful life may be impaired.)

Storage Temperature .................................–65°C to +150°C

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current...................................... ... ........... > 200 mA

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on VDD Relative to GND........–0.5V to +2.9V

Supply Voltage on V

Relative to GND......–0.5V to +V

DDQ

DD

DC Voltage Applied to Outputs

in High-Z State.................................... –0.5V to V

DC Input Voltage

[11]

...............................–0.5V to VDD + 0.3V

DDQ

+ 0.3V

Electrical Characteristics Over the Operating Range

Operating Range

Range

T emperature (TA)V

Com’l 0°C to +70°C 1.8 ± 0.1 V 1.4V to V
Ind’l –40°C to +85°C

[12, 19]

Ambient

DD

[19]

V

DDQ

[19]

DC Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Typ. Max. Unit

V

DD

V

DDQ

V

OH

V

OL

V

OH(LOW)

V

OL(LOW)

V

IH

V

IL

I

X

I

OZ

V

REF

I

DD

Power Supply Voltage 1.7 1.8 1.9 V
I/O Supply Voltage 1.4 1.5 V
Output HIGH Voltage Note 17 V
Output LOW Voltage Note 18 V
Output HIGH Voltage I

= −0.1 mA, Nominal Impedance V

OH

Output LOW Voltage IOL = 0.1 mA, Nominal Impedance V
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current GND ≤ VI ≤ V
Output Leakage Current GND ≤ VI ≤ V
Input Reference Voltage
VDD Operating Supply V

[11]

[11]

DDQ

Output Disabled −55µA

= 1/t

DDQ,

OUT

CYC

= 0 mA,

167 MHz 500 mA
200 MHz 550 mA

[20]

Typical Value = 0.75V 0.68 0.75 0.95 V

= Max., I

DD

f = f

MAX

/2 – 0.12 V

DDQ

/2 – 0.12 V

DDQ

– 0.2 V

DDQ

SS

V

+ 0.1 V

REF

–0.3 V

−55µA

DD

/2 + 0.12 V

DDQ

/2 + 0.12 V

DDQ

DDQ

0.2 V
+0.3 V

DDQ

– 0.1 V

REF

250 MHz 600 mA

I

SB1

Automatic Power-down
Current

Max. VDD, Both Ports
Deselected, V
V

≤ VIL f = f

IN

Inputs Static

IN

MAX

≥ VIH or

= 1/t

167 MHz 240 mA
200 MHz 260 mA

CYC,

250 MHz 280 mA

DD

V

V

AC Input Requirements

Over the Operating Range

Parameter Description Test Conditions Min. Typ. Max. Unit

V

IH

V

IL

Capacitance

Input HIGH Volt age V

+ 0.2 – – V

REF

Input LOW Voltage – – V

[21]

- 0.2 V

REF

Parameter Description Test Conditions Max. Unit

C

Input Capacitance TA = 25°C, f = 1 MHz,

IN

C

CLK

C

O

Notes:

17.Output are impedance controlled. I

18.Output are impedance controlled. I

19.Power-up: Assumes a linear ramp from 0V to V
(Min.) = 0.68V or 0.46V

20.V

REF

21.Tested initially and af ter any design or process change that may affect these parameters.

Clock Input Capacitance 6 pF
Output Capacitance 7 pF

= –(V

OH

= (V

OL

, whichever is larger, V

DDQ

/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ωs.

DDQ

/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.

DDQ

(min.) within 200 ms. During this time V

DD

REF

V

= 1.8V

DD

V

= 1.5V

DDQ

(Max.) = 0.95V or 0.54V

DDQ

< V

and V

IH

DD

, whichever is smaller.

DDQ

< VDD.

5pF

Document #: 001-00350 Rev. *A Page 17 of 23

[+] Feedback

CY7C1292DV18
CY7C1294DV18

Thermal Resistance

[21]

Parameter Description Test Conditions 165 FBGA Unit

Θ

JA

Θ

JC

Thermal Resistance (Junction to Ambient) Test conditions follow standard test
Thermal Resistance (Junction to Case) 5.91 °C/W

methods and procedures for measuring
thermal impedance, per EIA/JESD51.

28.51 °C/W

AC Test Loads and Waveforms

V

= 0.75V

REF

(a)

0.75V

Z

0

RQ =
250

= 50Ω

Ω

V

REF

R

= 50Ω

L

= 0.75V

V

REF

OUTPUT

Device
Under
Test

ZQ

0.75V

RQ =
250

(b)

and load capacitance shown in (a) of AC Test Loads.

OL/IOH

R = 50Ω

5pF

Ω

0.25V

ALL INPUT PULSES

1.25V

0.75V

Slew Rate = 2 V/ns

[22]

= 1.5V, input

DDQ

V

REF

OUTPUT

Device
Under
Test

ZQ

Note:

22.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, V
pulse levels of 0.25V to 1.25V, and output loading of the specified I

Document #: 001-00350 Rev. *A Page 18 of 23

[+] Feedback

CY7C1292DV18
CY7C1294DV18

Switching Characteristics Over the Operating Range

Cypress

Parameter

t

POWER

t

CYC

t

KH

t

KL

Consortium

Parameter Description

t

KHKH

t

KHKL

t

KLKH

t

KHKH

VDD(Typical) to the first Access
K Clock and C Clock Cycle Time 4.0 6.3 5.0 7.9 6.0 7.9 ns
Input Clock (K/K and C/C) HIGH
Input Clock (K/K and C/C) LOW

[24]

[22, 23]

250 MHz 200 MHz 167 MHz

UnitMin. Max. Min. Max. Min. Max.

111ms

1.6 – 2.0 – 2.4 – ns

1.6 – 2.0 – 2.4 – ns

K Clock Rise to K Clock Rise and C to C Rise

t

KHKH

t

KHCH

(rising edge to rising edge)

1.8 – 2.2 – 2.7 – ns

K/K Clock Rise to C/C Clock Rise

t

KHCH

t

KHKH

(rising edge to rising edge)

0.0 1.8 0.0 2.2 0.0 2.7 ns

Set-up Times

t

SA

t

SC

t

AVKH

t

IVKH

Address Set-up to Clock (K/K) Rise 0.35 – 0.4 – 0.5 – ns
Control Set-up to K Clock Rise (RPS, WPS)

0.35 – 0.4 – 0.5 – ns

Double Data Rate Control Set-up to Clock

t

SCDDR

t

SD

t

IVKH

t

DVKH

) Rise (BWS0, BWS1, BWS3, BWS4) 0.35 – 0.4 – 0.5 – ns

(K/K
D

Set-up to Clock (K/K) Rise

[X:0]

0.35 – 0.4 – 0.5 – ns

Hold Times

t

HA

t

HC

t

KHAX

t

KHIX

Address Hold after Clock (K/K) Rise
Control Hold after K Clock Rise (RPS, WPS)

0.35 – 0.4 – 0.5 – ns

0.35 – 0.4 – 0.5 – ns

Double Data Rate Control Hold after Clock

t

HCDDR

t

HD

t

KHIX

t

KHDX

(K/K

) Rise (BWS0, BWS1, BWS3, BWS4) 0.35 – 0.4 – 0.5 – ns

D

Hold after Clock (K/K) Rise

[X:0]

0.35 – 0.4 – 0.5 – ns

Output Times

C/C Clock Rise (or K/K in Single Clock Mode)

t

CO

t

CHQV

to Data Valid

– 0.45 – 0.45 – 0.50 ns

Data Output Hold after Output C/C Clock Rise

t

DOH

t

CCQO

t

CQOH

t

CQD

t

CQDOH

t

CHZ

t

CLZ

t

CHQX

t

CHCQV

t

CHCQX

t

CQHQV

t

CQHQX

t

CHQZ

t

CHQX1

(Active to Active)
C/C Clock Rise to Echo Clock Valid
Echo Clock Hold after C/C Clock Rise
Echo Clock High to Data Valid – 0.30 – 0.35 – 0.40 ns
Echo Clock High to Data Invalid –0.30 – –0.35 – –0.40 – ns
Clock (C/C) Rise to High-Z

(Active to High-Z)
Clock (C/C) Rise to Low-Z

[25,26]

[25,26]

–0.45 – -0.45 – -0.50 – ns

– 0.45 – 0.45 – 0.50 ns

–0.45 – –0.45 – –0.50 – ns

– 0.45 – 0.45 – 0.50 ns

–0.45 – –0.45 – –0.50 – ns

DLL Timing

t

KC Var

t

KC lock

t

KC ResettKC Reset

Notes:

23.All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum freq uency above 133 MHz is operating at a lower clock freque ncy ,
it requires the input timings of the frequency range in which it is being operated and will output dat a with the output timings of that frequency range.

24.This part has a voltage regulator internally; t
can be initiated.

25.t

CHZ

26.At any given voltage and temperature t

t

KC Var

t

KC lock

Clock Phase Jitter – 0.20 – 0.20 – 0.20 ns
DLL Lock Time (K, C) 1024 – 1024 – 1024 – cycles
K Static to DLL Reset 30 – 30 – 30 – ns

is the time that the power needs to be supplied above V

POWER

, t

, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.

CLZ

is less than t

CHZ

CLZ

and t

less than tCO.

CHZ

minimum initially before a read or write operation

DD

Document #: 001-00350 Rev. *A Page 19 of 23

[+] Feedback

CY7C1292DV18
CY7C1294DV18

Switching Waveforms

[27, 28, 29]

Read/Write/Deselect Sequence

READ READ WRITE WRITEWRITE

12

K

K

RPS

WPS

A

D

A0

t

KH

tSAt

t

KL

tt

SC

A1

tSAt

HA

D11D10 D60

NOPREAD

34

t

CYC

t

HC

A2

HA

D30 D50 D51 D61

A3 A4

D31

58

t

6

KHKH

7

WRITE NOP

A6A5

9

10

t

t

SD

HD

Q

t

CLZ

t

KHCH

C

C

CQ

CQ

Notes:

27.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1.

28.Output are disabled (High-Z) one clock cycle after a NOP.

29.In this example, if address A2 = A1,then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole
diagram.

t

KH

t

t

KHCH

KL

t

t

KHKH

t

CQOH

CO

t

CQOH

t

CCQO

Q00 Q01

t

DOH

t

CYC

t

CCQO

t

SD

t

CQDOH

t

HD

Q20

Q21

t

CQD

DON’T CARE

Q40

Q41

t

CHZ

UNDEFINED

Document #: 001-00350 Rev. *A Page 20 of 23

[+] Feedback

CY7C1292DV18
CY7C1294DV18

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

Speed

(MHz) Ordering Code

167 CY7C1292DV18-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1294DV18-167BZC
CY7C1292DV18-167BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1294DV18-167BZXC
CY7C1292DV18-167BZI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial
CY7C1294DV18-167BZI
CY7C1292DV18-167BZXI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1294DV18-167BZXI

200 CY7C1292DV18-200BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1294DV18-200BZC
CY7C1292DV18-200BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1294DV18-200BZXC
CY7C1292DV18-200BZI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial
CY7C1294DV18-200BZI
CY7C1292DV18-200BZXI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1294DV18-200BZXI

250 CY7C1292DV18-250BZC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1294DV18-250BZC
CY7C1292DV18-250BZXC 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1294DV18-250BZXC
CY7C1292DV18-250BZI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial
CY7C1294DV18-250BZI
CY7C1292DV18-250BZXI 51-85180 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1294DV18-250BZXI

visit www.cypress.com for actual products offered.

Package
Diagram Package Type

Operating

Range

Document #: 001-00350 Rev. *A Page 21 of 23

[+] Feedback

Package Diagram

PIN 1 CORNER

A

A

B

B

C

C

D

D

E

E

F

F

G

G

H

H

15.00±0.10

A

0.53±0.05

0.25 C

0.36

B

J

K

L

M

N

P

R

B

0.53±0.05

C

0.36

J

K

L

M

N

P

R

SEATING PLANE

15.00±0.10

A

0.25 C

PIN 1 CORNER

SEATING PLANE

C

TOP VIEW

13.00±0.10

165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D

165-ball FBGA (13 x 15 x 1.4 mm) (51-85180)

TOP VIEW

1110986754321

1110986754321

14.00

15.00±0.10

15.00±0.10

A

A

13.00±0.10

1.40 MAX.

0.35±0.06

0.15 C

1.40 MAX.

0.35±0.06

0.15(4X)

0.15 C

CY7C1292DV18
CY7C1294DV18

BOTTOM VIEW

11

11

1.00

1.00

14.00

7.00

7.00

5.00

5.00

10.00

B

B

0.15(4X)

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

13.00±0.10

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g

PACKAGE CODE : BB0AC

BOTTOM VIEW

Ø0.05 M C

Ø0.05 M C

Ø0.25MCAB

-0.06

Ø0.25 M C A B

Ø0.50 (165X)

+0.14

Ø0.50 (165X)

10.00

13.00±0.10

51-85180-*A

PIN1CORNER

-0.06

2345678910

+0.14

1.00

1.00

PIN 1 CORNER

1

2345678910

51-85180-*A

1

A

A

B

B

C

C

D

D

E

E

F

F

G

G

H

H

J

J

K

K

L

L

M

M

N

N

P

P

R

R

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, NEC, and
Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 001-00350 Rev. *A Page 22 of 23

© Cypress Semiconductor Corporation, 2006. The information contained herein i s su bj ect to ch an ge wi t hout notice. Cypress Semiconductor Corporation assumes no responsib ility for th e u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypre ss does not auth orize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

[+] Feedback

CY7C1292DV18
CY7C1294DV18

Document History Page

Document Title: CY7C1292DV18/CY7C1294DV18 9-Mbit QDR- II™ SRAM 2-Word Burst Architecture
Document Number: 001-00350

REV. ECN No. Issue Date

** 380737 See ECN SYT New data sheet

*A 485631 See ECN NXR Converted from Preliminary to Final

Orig. of
Change Description of Change

Removed 300MHz Speed Bin.
Changed address of Cypress Semiconductor Corporation on Page# 1 from

“3901 North First Street” to “198 Champion Court”
Changed C/C

Pin Description in the features section and Pin Description.
Modified the ZQ Definition from Alternately, this pin can be connected directly
to V

to Alternately, this pin can be connected directly to V

DD

Changed t

, t

t

TDIH

AC Switching Characteristics table

and t

TH

from 10 ns to 5 ns and changed t

CH

from 40 ns to 20 ns, changed t

TL

TDOV

Added power-up sequence details and waveforms.
Added foot notes #15 and 16 on page# 18.
Included Maximum Ratings for Supply Voltage on V
Changed the Maximum rating of Ambient Temperature with Power Applied
from –10°C to +85°C to –55°C to +125°C
Changed the Maximum Ratings for DC Input Voltage from V
Changed the description of IX from Input Load Current to Input Leakage
Current on page# 13.
Modified the IDD and ISB values
Modified test condition in Footnote #20 on page# 19 from V

< V

V

DDQ

Changed the Min. Value of t

0.6ns to 0.4ns for 200 MHz speed bins.
Changed the description of t
Changed the description of t
Rise.

DD.

and tHC from 0.5ns to 0.35ns for 250 MHz and

SC

from K Clock Rise to Clock (K/K) Rise.

SA

SC

and t

from Clock (K and K) Rise to K Clock

HC

Replaced Package Name column with Package Diagram in the Ordering
Information table.
Updated the Ordering Information Table.

TMSS

from 20 ns to 10 ns in TAP

DDQ

DDQ.

, t

, tCS, t

TDIS

TMSH

Relative to GND

to V

DDQ

DDQ

DD.

< VDD to

,

Document #: 001-00350 Rev. *A Page 23 of 23

[+] Feedback