Cypress CY7C1270V18, CY7C1266V18, CY7C1268V18, CY7C1277V18 User Manual

CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18

36-Mbit DDR-II+ SRAM 2-Word

Burst Architecture (2.5 Cycle Read Latency)

Features

Note

1. The QDR consortium specification for V

DDQ

is 1.5V + 0.1V . The Cypress QDR devices exceed the QDR consort ium specification and are cap able of supporting

DDQ

= 1.4V to VDD.

Functional Description

■ 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)

■ 300 MHz to 400 MHz clock for high bandwidth

■ 2-Word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 800 MHz) at 400 MHz

■ Read latency of 2.5 clock cycles

■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ Core V

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both in Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

= 1.8V ± 0.1V; IO V

= 1.4V to V

DDQ

[1]

Configurations

The CY7C1266V18, CY7C1277V18, CY7C1268V18, and CY7C1270V18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II+ architecture. The DDR-II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K of both K and K

. Read data is driven on the rising edges

. Each address location is associated with two 8-bit words (CY7C1266V18), 9-bit words (CY7C1277V18), 18-bit words (CY7C1268V18), or 36-bit words (CY7C1270V18), that burst sequentially into or out of the device.

Asynchronous inputs include output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs, D) are tightly matched to the two output echo clocks CQ/CQ

, eliminating the need to capture data separately from each individual DDR SRAM in the system design.

All synchronous inputs pass through input registers controlled by the K or K registers controlled by the K or K

input clocks. All data outputs pass through output

input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

With Read Cycle Latency of 2.5 cycles:

CY7C1266V18 – 4M x 8 CY7C1277V18 – 4M x 9 CY7C1268V18 – 2M x 18 CY7C1270V18 – 1M x 36

Selection Guide

Description 400 MHz 375 MHz 333 MHz 300 MHz Unit

Maximum Operating Frequency 400 375 333 300 MHz Maximum Operating Current 1280 1210 1080 1000 mA

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-06347 Rev. *D Revised March 11, 2008

[+] Feedback [+] Feedback

CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18

Logic Block Diagram (CY7C1266V18)

CLK

(20:0)

Gen.

Control

Logic

Address Register

Read Add. Decode

Read Data Reg.

R/W

[7:0]

Output

Logic

Reg.

NWS

[1:0]

REF

Write Add. Decode

Control

2M x 8 Array

Write Reg

CQ CQ

R/W

DOFF

QVLD

CLK

(20:0)

Gen.

Control

Logic

Address Register

Read Add. Decode

Read Data Reg.

R/W

[8:0]

Output

Logic

Reg.

BWS

[0]

REF

Write Add. Decode

Control

2M x 9 Array

Write Reg

CQ CQ

R/W

DOFF

QVLD

Logic Block Diagram (CY7C1277V18)

Document Number: 001-06347 Rev. *D Page 2 of 27

[+] Feedback [+] Feedback

CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18

Logic Block Diagram (CY7C1268V18)

CLK

(19:0)

Gen.

Control

Logic

Address Register

Read Add. Decode

Read Data Reg.

R/W

[17:0]

Output

Logic

Reg.

BWS

[1:0]

REF

Write Add. Decode

Control

1M x 18 Array

Write Reg

CQ CQ

R/W

DOFF

QVLD

CLK

(18:0)

Gen.

Control

Logic

Address Register

Read Add. Decode

Read Data Reg.

R/W

[35:0]

Output

Logic

Reg.

BWS

[3:0]

REF

Write Add. Decode

Control

512K x 36 Array

Write Reg

CQ CQ

R/W

DOFF

QVLD

Logic Block Diagram (CY7C1270V18)

Document Number: 001-06347 Rev. *D Page 3 of 27

[+] Feedback [+] Feedback

CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18

Pin Configurations

CY7C1266V18 (4M x 8)

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

2345671

A B C

D E F G

J K L M N P

CQ NC NC NC

DOFF

NC/72M A

NWS

KR/W

NC/144M

TDO

TCK

A NC/288M

NWS

AAA

NC V

DQ4

DDQ

NC NC

DQ7

DDQ

DQ5 V

DDQ

ANC

NC V

REF

QVLD

DQ6

891011

A NC

DQ3

NC NC NC NC

DQ2

REF

DDQ

NC NC

DDQ

NCV

DDQ

DQ1

DDQ

NC NC NC

TDITMS

DQ0

CY7C1277V18 (4M x 9)

2345671

CQ NC

NC NC

DOFF

NC/72M A NC

R/W

NC/144M

TDO

TCK

A NC/288M

BWS

AAA

NC V

DQ4

DDQ

NC NC

DQ7

DDQ

DQ5 V

DDQ

NC V

REF

QVLD

DQ6

891011

DQ8

A NC

DQ3

NC NC NC NC

DQ2

REF

DDQ

NC NC

DDQ

NCV

DDQ

DQ1

DDQ

NC NC NC

TDITMS

DQ0

Document Number: 001-06347 Rev. *D Page 4 of 27

[+] Feedback [+] Feedback

CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18

Pin Configurations (continued)

CY7C1268V18 (2M x 18)

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

2345671

A B C

D E

F G H

J K

L M

N P

CQ NC

NC NC

DOFF

NC/72M A

BWS

KR/W

NC/144M

DQ9

TDO

TCK

A NC/288M

BWS

ANCA

DQ10 V

DQ11

DDQ

DQ14

NC DQ16 DQ17

DDQ

DQ13 V

DDQ

NC V

DQ12

REF

QVLD

DQ15

891011

DQ0

A NC

DQ8

NC DQ7 NC NC

DQ6

REF

DQ3

DDQ

NC DQ5

DDQ

NCV

DDQ

DQ4

DDQ

NC NC NC

TDITMS

DQ2

DQ1

CY7C1270V18 (1M x 36)

2345671 A B C D E F G H

J K L M N P

CQ NC

NC NC

DOFF

NC/144M A

BWS

KR/W

BWS

DQ27

DQ18

TDO

DQ31

TCK

DQ28

BWS

ANCA

DQ19 V

DQ20 DQ21

DDQ

DQ32 DQ23

DQ34 DQ25 DQ26

DDQ

DQ22 V

DDQ

DQ29 V

NC V

DQ30

REF

QVLD

DQ33

DQ35

DQ24

891011

DQ0

A NC/72M

A NC

DQ8

NC DQ17 DQ7 NC

DQ6

DQ14

REF

DQ3

DDQ

NC DQ5

DDQ

DQ4V

DDQ

DQ13

DDQ

NC DQ1 NC

TDITMS

DQ16

DQ15

DQ12

DQ2

DQ10

DQ11

DQ9

Document Number: 001-06347 Rev. *D Page 5 of 27

[+] Feedback [+] Feedback

CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18

Pin Definitions

Pin Name IO Pin Description

[x:0]

Input/OutputSynchronous

LD Input-

Synchronous

NWS0, NWS

BWS

, BWS

1 3

Input-

Synchronous

Input-

Synchronous

Data Input/Output Signals. Inputs are sampled on the rising edge of K and K

clocks during valid write operations. These pins drive out the requested data during a read operation. Valid data is driven out on the rising edge of both the K and K read access is deselected, Q CY7C1266V18 – DQ CY7C1277V18 – DQ CY7C1268V18 – DQ CY7C1270V18 – DQ

[7:0] [8:0] [17:0] [35:0]

are automatically tri-stated.

[x:0]

clocks during read operations. When

Synchronous Load. Sampled on the rising edge of the K clock. This input is brought LOW when a bus cycle sequence is to be defined. This definition includes address and read/write direction. All transactions operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.

Nibble Write Select 0, 1, Active LOW (CY7C1266V18 only). Sampled on the rising edge of the K and K

clocks during write operations. Used to select which nibble is written into the device

during the current portion of the write operations. Nibbles not written remain unaltered. NWS

controls D

and NWS1 controls D

[3:0]

[7:4]

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select ignores the corresponding nibble of data and not written into the device.

Byte Write Select 0, 1, 2, and 3, Active LOW. Sampled on the rising edge of the K and K clocks during write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1277V18 − BWS CY7C1268V18 − BWS0 controls D CY7C1270V18 − BWS0 controls D controls D

[35:27]

controls D

[8:0]

and BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

[17:9].

, BWS2 controls D

[17:9]

[26:18]

and BWS3

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select ignores the corresponding byte of data and not written into the device.

A Input-

Synchronous

Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These address inputs are multiplexed for both read and write operations. Internally, the device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C1266V18, 4M x 9 (2 arrays each of 2M x 9) for CY7C1277V18, 2M x 18 (2 arrays each of 1M x 18) for CY7C1268V18, and 1M x 36 (2 arrays each of 512K x 36) for CY7C1270V18.

R/W

Input-

Synchronous

Synchronous Read/Write Input. When LD is LOW, this input designates the access type (Read when R/W

is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the setup and

hold times around edge of K.

QVLD Valid Output

Indicator

K Input-

Clock

InputClock

Valid Output Ind icator . The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q on the rising edge of K.

when in single clock mode. All accesses are initiated

[x:0]

Negative Input Clock Input. K is used to capture synchronous data being presented to the device and to drive out data through Q

when in single clock mode.

[x:0]

CQ Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the

input clock (K) of the DDR-II+. The timing for the echo clocks is shown in “Switching Character-

istics” on page 22.

Clock Output

Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock (K) of the DDR-II+. The timing for the echo clocks is shown in “Switching Character-

istics” on page 22.

Document Number: 001-06347 Rev. *D Page 6 of 27

[+] Feedback [+] Feedback

CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18

Pin Definitions (continued)

Pin Name IO Pin Description

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system

data bus impedance. CQ, CQ resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to V

, which enables the minimum impedance mode. This pin cannot be connected directly to

DDQ

GND or left unconnected.

, and Q

output impedance are set to 0.2 x RQ, where RQ is a

[x:0]

DOFF

TDO Output TDO for JTAG. TCK Input TCK Pin for JTAG. TDI Input TDI Pin for JTAG. TMS Input TMS Pin for JTAG. NC N/A Not Connected to the Die. Can be tied to any voltage level. NC/72M N/A Not Connected to the Die. Can be tied to any voltage level. NC/144M N/A Not Connected to the Die. Can be tied to any voltage level. NC/288M N/A Not Connected to the Die. Can be tied to any voltage level. V

REF

DDQ

Input DLL Turn Off, Active LOW. Connecting this pin to ground turns off the DLL inside the device.

Input-

Reference

Power Supply Power Supply Inputs to the Core of the Device.

Ground Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

The timing in the DLL turned off operation is different from that listed in this data sheet. For normal operation, this pin can be connected to a pull up through a 10 Kohm or less pull up resistor. The device behaves in DDR-I mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with DDR-I timing.

Reference Volt age Input. S tatic input used to set the reference level for HSTL inputs, outputs, and AC measurement points.

Document Number: 001-06347 Rev. *D Page 7 of 27

[+] Feedback [+] Feedback

CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18

Functional Overview

The CY7C1266V18, CY7C1277V18, CY7C1268V18, and CY7C1270V18 are synchronous pipelined Burst SRAMs equipped with a DDR interface.

Accesses for both ports are initiated on the Positive Input Clock (K). All synchronous input and output timing refer to the ri sing edge of the input clocks (K and K).

All synchronous data inputs (D controlled by the rising edge of the input clocks (K and K synchronous data outputs (Q controlled by the rising edge of the input clocks (K and K

All synchronous control (R/W, LD, BWS input registers controlled by the rising edge of the input clock (K\K).

CY7C1268V18 is described in the following sections. The same basic descriptions apply to CY7C1266V18, CY7C1277V18, and CY7C1270V18.

Read Operations

The CY7C1268V18 is organized internally as a singl e array of 2M x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting R/W

HIGH and LD LOW at the rising edge of the positive input clock (K). Following the next two K sponding 18-bit word of data from this address location is driven onto the Q subsequent rising edge of K the next 18-bit data word is driven onto the Q rising edge of the Input clock (K and K

, using K as the output timing reference. On the

[17:0]

. The requested data is valid 0.45 ns from the

[17:0]

logic, each read access must be allowed to complete. Read accesses can be initiated on every rising edge of the positive input clock (K).

When read access is deselected, the CY7C1268V18 completes the pending Read transactions. Synchronous internal circuitry automatically tri-states the outputs following the next rising edge of the negative input clock (K transition between devices without the insertion of wait states in a depth expanded memory.

Write Operations

Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock (K). The address presented to Address inputs is stored in the Write Address register. On the following K clock rise, the data presented to D Data register provided BWS subsequent rising edge of the Negative Input Clock (K mation presented to D register provided BWS of data are then written into the memory array at the specified location. Write accesses can be initiated on every rising edge of the positive input clock (K). Doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K

When write access is deselected, the device ignores all inputs after the pending write operations have been completed.

is latched and stored into the 18-bit Write

[17:0]

are both asserted active. The 36 bits

[1:0]

) pass through input registers

[x:0]

) pass through output registers

[x:0]

) inputs pass through

[0:X]

). All

clock rising edges, the corre-

). To maintain the internal

). This enables a seamless

are both asserted active. On the

[1:0]

), the infor-

is also stored into the Write Data

Byte Write Operations

Byte write operations are supported by the CY7C1268V18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS BWS

, which are sampled with each set of 18-bit data words.

Asserting the appropriate Byte Write Select input during the data

and

portion of a write latches the data being presented and written into the device. Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device to that byte to remain unaltered. This feature can be used to simplify read/modify/write operations to a byte write operation.

Double Data Rate Operation

The CY7C1268V18 enables high-performance operation through high clock frequencies (achieved through pipelining) and DDR mode of operation. The CY7C1268V18 requires three No Operation (NOP) cycles when transitioning from a read to a write cycle.

If a read occurs after a write cycle, address and data for the write are stored in registers. The write information must be stored because the SRAM cannot perform the last word write to the array without conflicting with the read. The data stays in this register until the next write cycle occurs. On the first write cycle after the read(s), the stored data from the earlier write is written into the SRAM array. This is called a Posted Write.

If a read is performed on the same address on which a write is performed in the previous cycle, the SRAM reads out the most current data. The SRAM does this by bypassing the memory array and reading the data from the registers.

Depth Expansion

Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15%, is between 175Ω and 350Ω output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature.

to enable the SRAM to adjust its output

, with V

=1.5V. The

DDQ

Echo Clocks

Echo clocks are provided on the DDR-II+ to simplify data capture on high speed systems. Two echo clocks are generated by the DDR-II+. CQ is referenced with respect to K and CQ enced with respect to K

. These are free running clocks and are

is refer-

synchronized to the input clock of the DDR-II+. The timing for the echo clocks is shown in “Switching Characteristics” on page 22.

Valid Data Indicator (QVLD)

QVLD is provided on the DDR-II+ to simplify data capture on high speed systems. The QVLD is generated by the DDR-II+ device along with data output. This signal is also edge aligned with the echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives.

Document Number: 001-06347 Rev. *D Page 8 of 27

[+] Feedback [+] Feedback

CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18

Delay Lock Loop (DLL)

Notes

2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑

represents rising edge.

3. Device powers up deselected with the outputs in a tri-state condition.

4. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst.

5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second, and third clock cycles succeeding the “t ” clo ck cycle.

6. Data inputs are registered at K and K

rising edges. Data outputs are delivered on K and K rising edges.

7. Cypress recommends that K = K

= HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission li ne charging

symmetrically.

These chips use a DLL that is designed to function between 120 MHz and the specified maximum clock frequency. The DLL may be disabled by applying ground to the DOFF

pin. When the DLL is turned off, the device behaves in DDR-I mode (with 1.0 cycle latency and a longer access time). For more information, refer to

Application Example

Figure 1 shows two DDR-II+ used in an application.

Figure 1. Application Example

the application note, DLL Considerations in QDRII/DDRII/QDRII+/DDRII+. The DLL can also be reset by

slowing or stopping the input clocks K and K

for a minimum of 30 ns. However, it is not necessary for the DLL to be reset to lock to the frequency you want. During power up, when the DOFF is tied HIGH, the DLL is locked after 2048 cycles of stable clock.

CQ/CQ

R = 250ohms

DQ A

SRAM#2

LD R/W

BUS

MASTER

(CPU or ASIC)

Echo Clock1/Echo Clock1 Echo Clock2/Echo Clock2

Addresses

Cycle Start

R/W Source CLK Source CLK

DQ A

SRAM#1

LD R/W

Truth Table

The truth table for CY7C1266V18, CY7C1277V18, CY7C1268V18, and CY7C1270V18 follows.

Operation K LD R/W DQ DQ

Write Cycle: Load address; wait one cycle; input write data on consecutive K and K

rising edges.

Read Cycle: (2.5 cycle Latency) Load address; wait two and half cycle; read data on consecutive K

and K rising edges.

L-H L L D(A) at K(t + 1) ↑ D(A + 1) at K(t + 1) ↑

L-H L H Q(A) at K

CQ/CQ

[2, 3, 4, 5, 6, 7]

R = 250ohms

(t + 2) ↑ Q(A + 1) at K(t + 3) ↑

NOP: No Operation L-H H X High-Z High-Z Standby: Clock Stopped Stopped X X Previous State Previous State

Document Number: 001-06347 Rev. *D Page 9 of 27

[+] Feedback [+] Feedback

+ 18 hidden pages

Cypress CY7C1270V18, CY7C1266V18, CY7C1268V18, CY7C1277V18 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Functional Description

Configurations

Selection Guide

Logic Block Diagram (CY7C1266V18)

Logic Block Diagram (CY7C1277V18)

Logic Block Diagram (CY7C1268V18)

Logic Block Diagram (CY7C1270V18)

Pin Configurations

Pin Definitions

Functional Overview

Read Operations

Write Operations

Byte Write Operations

Double Data Rate Operation

Depth Expansion

Programmable Impedance

Echo Clocks

Valid Data Indicator (QVLD)

Delay Lock Loop (DLL)

Application Example

Truth Table