Cypress CY7C1270V18, CY7C1266V18, CY7C1268V18, CY7C1277V18 User Manual

CY7C1266V18, CY7C1277V18
CY7C1268V18, CY7C1270V18

36-Mbit DDR-II+ SRAM 2-Word

Burst Architecture (2.5 Cycle Read Latency)

Features

Note

1. The QDR consortium specification for V

DDQ

is 1.5V + 0.1V . The Cypress QDR devices exceed the QDR consort ium specification and are cap able of supporting

V

DDQ

= 1.4V to VDD.

Functional Description

■ 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)

■ 300 MHz to 400 MHz clock for high bandwidth

■ 2-Word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 800 MHz) at 400 MHz

■ Read latency of 2.5 clock cycles

■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ Core V

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both in Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

= 1.8V ± 0.1V; IO V

DD

= 1.4V to V

DDQ

DD

[1]

Configurations

The CY7C1266V18, CY7C1277V18, CY7C1268V18, and
CY7C1270V18 are 1.8V Synchronous Pipelined SRAMs
equipped with DDR-II+ architecture. The DDR-II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K
of both K and K

. Read data is driven on the rising edges

. Each address location is associated with two
8-bit words (CY7C1266V18), 9-bit words (CY7C1277V18),
18-bit words (CY7C1268V18), or 36-bit words (CY7C1270V18),
that burst sequentially into or out of the device.

Asynchronous inputs include output impedance matching input
(ZQ). Synchronous data outputs (Q, sharing the same physical
pins as the data inputs, D) are tightly matched to the two output
echo clocks CQ/CQ

, eliminating the need to capture data
separately from each individual DDR SRAM in the system
design.

All synchronous inputs pass through input registers controlled by
the K or K
registers controlled by the K or K

input clocks. All data outputs pass through output

input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

With Read Cycle Latency of 2.5 cycles:

CY7C1266V18 – 4M x 8
CY7C1277V18 – 4M x 9
CY7C1268V18 – 2M x 18
CY7C1270V18 – 1M x 36

Selection Guide

Description 400 MHz 375 MHz 333 MHz 300 MHz Unit

Maximum Operating Frequency 400 375 333 300 MHz
Maximum Operating Current 1280 1210 1080 1000 mA

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-06347 Rev. *D Revised March 11, 2008

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CY7C1266V18, CY7C1277V18
CY7C1268V18, CY7C1270V18

Logic Block Diagram (CY7C1266V18)

CLK

A

(20:0)

Gen.

K

K

Control

Logic

Address
Register

Read Add. Decode

Read Data Reg.

R/W

DQ

[7:0]

Output

Logic

Reg.

Reg.

Reg.

8

8

16

8

NWS

[1:0]

V

REF

Write Add. Decode

8

8

LD

Control

21

2M x 8 Array

2M x 8 Array

Write
Reg

Write
Reg

CQ
CQ

R/W

DOFF

QVLD

8

CLK

A

(20:0)

Gen.

K

K

Control

Logic

Address
Register

Read Add. Decode

Read Data Reg.

R/W

DQ

[8:0]

Output

Logic

Reg.

Reg.

Reg.

9

9

18

9

BWS

[0]

V

REF

Write Add. Decode

9

9

LD

Control

21

2M x 9 Array

2M x 9 Array

Write
Reg

Write
Reg

CQ
CQ

R/W

DOFF

QVLD

9

Logic Block Diagram (CY7C1277V18)

Document Number: 001-06347 Rev. *D Page 2 of 27

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CY7C1266V18, CY7C1277V18
CY7C1268V18, CY7C1270V18

Logic Block Diagram (CY7C1268V18)

CLK

A

(19:0)

Gen.

K

K

Control

Logic

Address
Register

Read Add. Decode

Read Data Reg.

R/W

DQ

[17:0]

Output

Logic

Reg.

Reg.

Reg.

18

18

36

18

BWS

[1:0]

V

REF

Write Add. Decode

18

18

LD

Control

20

1M x 18 Array

1M x 18 Array

Write
Reg

Write
Reg

CQ
CQ

R/W

DOFF

QVLD

18

CLK

A

(18:0)

Gen.

K

K

Control

Logic

Address
Register

Read Add. Decode

Read Data Reg.

R/W

DQ

[35:0]

Output

Logic

Reg.

Reg.

Reg.

36

36

72

36

BWS

[3:0]

V

REF

Write Add. Decode

36

36

LD

Control

19

512K x 36 Array

512K x 36 Array

Write
Reg

Write
Reg

CQ
CQ

R/W

DOFF

QVLD

36

Logic Block Diagram (CY7C1270V18)

Document Number: 001-06347 Rev. *D Page 3 of 27

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CY7C1266V18, CY7C1277V18
CY7C1268V18, CY7C1270V18

Pin Configurations

CY7C1266V18 (4M x 8)

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

2345671

A
B
C

D
E
F
G

H

J
K
L
M
N
P

R

A

CQ
NC
NC
NC

NC

DOFF

NC

NC/72M A

NWS

1

KR/W

NC/144M

NC

NC

NC

NC

NC

TDO

NC

NC

NC

NC

NC

NC

TCK

NC

NC

A NC/288M

K

NWS

0

V

SS

AAA

NC V

SS

V

SS

V

SS

V

SS

V

DD

A

V

SS

V

SS

V

SS

V

DD

DQ4

NC

V

DDQ

NC
NC

NC
NC

DQ7

A

V

DDQ

V

SS

V

DDQ

V

DD

V

DD

DQ5 V

DDQ

V

DD

V

DDQ

V

DD

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

V

DDQ

V

SS

V

SS

V

SS

V

SS

A

ANC

V

SS

A

A

A

NC V

SS

NC V

SS

NC

NC

V

REF

V

SS

V

DD

V

SS

V

SS

A

V

SS

QVLD

NC

DQ6

NC

NC

NC

V

DD

A

891011

NC

AA

LD

CQ

A NC

NC

DQ3

V

SS

NC NC NC
NC

V

SS

NC

DQ2

NC

NC

NC

V

REF

NC

NC

V

DDQ

NC

V

DDQ

NC NC

V

DDQ

V

DDQ

V

DDQ

NCV

DDQ

NC

DQ1

NC

V

DDQ

V

DDQ

NC

V

SS

NC NC
NC

TDITMS

V

SS

A

NC

A

NC

NC

NC

ZQ

NC

DQ0

NC

NC

NC

NC

A

CY7C1277V18 (4M x 9)

2345671

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

A

CQ
NC

NC
NC

NC

DOFF

NC

NC/72M A NC

K

R/W

NC/144M

NC

NC

NC

NC

NC

TDO

NC

NC

NC

NC

NC

NC

TCK

NC

NC

A NC/288M

K

BWS

0

V

SS

AAA

NC V

SS

V

SS

V

SS

V

SS

V

DD

A

V

SS

V

SS

V

SS

V

DD

DQ4

NC

V

DDQ

NC
NC

NC
NC

DQ7

A

V

DDQ

V

SS

V

DDQ

V

DD

V

DD

DQ5 V

DDQ

V

DD

V

DDQ

V

DD

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

V

DDQ

V

SS

V

SS

V

SS

V

SS

A

A

NC

V

SS

A

A

A

NC V

SS

NC V

SS

NC

NC

V

REF

V

SS

V

DD

V

SS

V

SS

A

V

SS

QVLD

NC

DQ6

NC

NC

NC

V

DD

A

891011

DQ8

AA

LD

CQ

A NC

NC

DQ3

V

SS

NC NC NC
NC

V

SS

NC

DQ2

NC

NC

NC

V

REF

NC

NC

V

DDQ

NC

V

DDQ

NC NC

V

DDQ

V

DDQ

V

DDQ

NCV

DDQ

NC

DQ1

NC

V

DDQ

V

DDQ

NC

V

SS

NC NC
NC

TDITMS

V

SS

A

NC

A

NC

NC

NC

ZQ

NC

DQ0

NC

NC

NC

NC

A

Document Number: 001-06347 Rev. *D Page 4 of 27

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CY7C1266V18, CY7C1277V18
CY7C1268V18, CY7C1270V18

Pin Configurations (continued)

CY7C1268V18 (2M x 18)

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

2345671

A
B
C

D
E

F
G
H

J
K

L
M

N
P

R

A

CQ
NC

NC
NC

NC

DOFF

NC

NC/72M A

BWS

1

KR/W

NC/144M

DQ9

NC

NC

NC

NC

TDO

NC

NC

NC

NC

NC

NC

TCK

NC

NC

A NC/288M

K

BWS

0

V

SS

ANCA

DQ10 V

SS

V

SS

V

SS

V

SS

V

DD

A

V

SS

V

SS

V

SS

V

DD

DQ11

NC

V

DDQ

NC

DQ14

NC
DQ16
DQ17

A

V

DDQ

V

SS

V

DDQ

V

DD

V

DD

DQ13 V

DDQ

V

DD

V

DDQ

V

DD

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

V

DDQ

V

SS

V

SS

V

SS

V

SS

A

A

NC

V

SS

A

A

A

NC V

SS

NC V

SS

DQ12

NC

V

REF

V

SS

V

DD

V

SS

V

SS

A

V

SS

QVLD

NC

DQ15

NC

NC

NC

V

DD

A

891011

DQ0

AA

LD

CQ

A NC

NC

DQ8

V

SS

NC DQ7 NC
NC

V

SS

NC

DQ6

NC

NC

NC

V

REF

NC

DQ3

V

DDQ

NC

V

DDQ

NC DQ5

V

DDQ

V

DDQ

V

DDQ

NCV

DDQ

NC

DQ4

NC

V

DDQ

V

DDQ

NC

V

SS

NC NC
NC

TDITMS

V

SS

A

NC

A

NC

NC

NC

ZQ

NC

DQ2

NC

DQ1

NC

NC

A

CY7C1270V18 (1M x 36)

2345671
A
B
C
D
E
F
G
H

J
K
L
M
N
P

R

A

CQ
NC

NC
NC

NC

DOFF

NC

NC/144M A

BWS

2

KR/W

BWS

1

DQ27

DQ18

NC

NC

NC

TDO

NC

NC

DQ31

NC

NC

NC

TCK

NC

DQ28

A

BWS

3

K

BWS

0

V

SS

ANCA

DQ19 V

SS

V

SS

V

SS

V

SS

V

DD

A

V

SS

V

SS

V

SS

V

DD

DQ20
DQ21

V

DDQ

DQ32
DQ23

DQ34
DQ25
DQ26

A

V

DDQ

V

SS

V

DDQ

V

DD

V

DD

DQ22 V

DDQ

V

DD

V

DDQ

V

DD

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

V

DDQ

V

SS

V

SS

V

SS

V

SS

A

A

NC

V

SS

A

A

A

DQ29 V

SS

NC V

SS

DQ30

NC

V

REF

V

SS

V

DD

V

SS

V

SS

A

V

SS

QVLD

NC

DQ33

NC

DQ35

DQ24

V

DD

A

891011

DQ0

A NC/72M

LD

CQ

A NC

NC

DQ8

V

SS

NC DQ17 DQ7
NC

V

SS

NC

DQ6

DQ14

NC

NC

V

REF

NC

DQ3

V

DDQ

NC

V

DDQ

NC DQ5

V

DDQ

V

DDQ

V

DDQ

DQ4V

DDQ

NC

DQ13

NC

V

DDQ

V

DDQ

NC

V

SS

NC DQ1
NC

TDITMS

V

SS

A

NC

A

DQ16

DQ15

NC

ZQ

DQ12

DQ2

DQ10

DQ11

DQ9

NC

A

Document Number: 001-06347 Rev. *D Page 5 of 27

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CY7C1266V18, CY7C1277V18
CY7C1268V18, CY7C1270V18

Pin Definitions

Pin Name IO Pin Description

DQ

[x:0]

Input/Output­Synchronous

LD Input-

Synchronous

NWS0, NWS

BWS

BWS

,

0

BWS

, BWS

2

1

1
3

Input-

Synchronous

Input-

,

Synchronous

Data Input/Output Signals. Inputs are sampled on the rising edge of K and K

clocks during
valid write operations. These pins drive out the requested data during a read operation. Valid
data is driven out on the rising edge of both the K and K
read access is deselected, Q
CY7C1266V18 – DQ
CY7C1277V18 – DQ
CY7C1268V18 – DQ
CY7C1270V18 – DQ

[7:0]
[8:0]
[17:0]
[35:0]

are automatically tri-stated.

[x:0]

clocks during read operations. When

Synchronous Load. Sampled on the rising edge of the K clock. This input is brought LOW when
a bus cycle sequence is to be defined. This definition includes address and read/write direction.
All transactions operate on a burst of 2 data. LD must meet the setup and hold times around
edge of K.

Nibble Write Select 0, 1, Active LOW (CY7C1266V18 only). Sampled on the rising edge of
the K and K

clocks during write operations. Used to select which nibble is written into the device

during the current portion of the write operations. Nibbles not written remain unaltered.
NWS

controls D

0

and NWS1 controls D

[3:0]

[7:4]

.

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble
Write Select ignores the corresponding nibble of data and not written into the device.

Byte Write Select 0, 1, 2, and 3, Active LOW. Sampled on the rising edge of the K and K clocks
during write operations. Used to select which byte is written into the device during the current
portion of the write operations. Bytes not written remain unaltered.
CY7C1277V18 − BWS
CY7C1268V18 − BWS0 controls D
CY7C1270V18 − BWS0 controls D
controls D

[35:27]

.

controls D

0

[8:0]

and BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

[17:9].

, BWS2 controls D

[17:9]

[26:18]

and BWS3

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select ignores the corresponding byte of data and not written into the device.

A Input-

Synchronous

Address Inputs. Sampled on the rising edge of the K clock during active read and write opera­tions. These address inputs are multiplexed for both read and write operations. Internally, the
device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C1266V18, 4M x 9 (2 arrays
each of 2M x 9) for CY7C1277V18, 2M x 18 (2 arrays each of 1M x 18) for CY7C1268V18, and
1M x 36 (2 arrays each of 512K x 36) for CY7C1270V18.

R/W

Input-

Synchronous

Synchronous Read/Write Input. When LD is LOW, this input designates the access type (Read
when R/W

is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the setup and

hold times around edge of K.

QVLD Valid Output

Indicator

K Input-

Clock

K

Input­Clock

Valid Output Ind icator . The Q Valid indicates valid output data. QVLD is edge aligned with CQ
and CQ

.

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q
on the rising edge of K.

when in single clock mode. All accesses are initiated

[x:0]

Negative Input Clock Input. K is used to capture synchronous data being presented to the
device and to drive out data through Q

when in single clock mode.

[x:0]

CQ Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the

input clock (K) of the DDR-II+. The timing for the echo clocks is shown in “Switching Character-

istics” on page 22.

CQ

Clock Output

Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the
input clock (K) of the DDR-II+. The timing for the echo clocks is shown in “Switching Character-

istics” on page 22.

Document Number: 001-06347 Rev. *D Page 6 of 27

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CY7C1266V18, CY7C1277V18
CY7C1268V18, CY7C1270V18

Pin Definitions (continued)

Pin Name IO Pin Description

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system

data bus impedance. CQ, CQ
resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to
V

, which enables the minimum impedance mode. This pin cannot be connected directly to

DDQ

GND or left unconnected.

, and Q

output impedance are set to 0.2 x RQ, where RQ is a

[x:0]

DOFF

TDO Output TDO for JTAG.
TCK Input TCK Pin for JTAG.
TDI Input TDI Pin for JTAG.
TMS Input TMS Pin for JTAG.
NC N/A Not Connected to the Die. Can be tied to any voltage level.
NC/72M N/A Not Connected to the Die. Can be tied to any voltage level.
NC/144M N/A Not Connected to the Die. Can be tied to any voltage level.
NC/288M N/A Not Connected to the Die. Can be tied to any voltage level.
V

REF

V

DD

V

SS

V

DDQ

Input DLL Turn Off, Active LOW. Connecting this pin to ground turns off the DLL inside the device.

Input-

Reference

Power Supply Power Supply Inputs to the Core of the Device.

Ground Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

The timing in the DLL turned off operation is different from that listed in this data sheet. For
normal operation, this pin can be connected to a pull up through a 10 Kohm or less pull up
resistor. The device behaves in DDR-I mode when the DLL is turned off. In this mode, the device
can be operated at a frequency of up to 167 MHz with DDR-I timing.

Reference Volt age Input. S tatic input used to set the reference level for HSTL inputs, outputs,
and AC measurement points.

Document Number: 001-06347 Rev. *D Page 7 of 27

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CY7C1266V18, CY7C1277V18
CY7C1268V18, CY7C1270V18

Functional Overview

The CY7C1266V18, CY7C1277V18, CY7C1268V18, and
CY7C1270V18 are synchronous pipelined Burst SRAMs
equipped with a DDR interface.

Accesses for both ports are initiated on the Positive Input Clock
(K). All synchronous input and output timing refer to the ri sing
edge of the input clocks (K and K).

All synchronous data inputs (D
controlled by the rising edge of the input clocks (K and K
synchronous data outputs (Q
controlled by the rising edge of the input clocks (K and K

All synchronous control (R/W, LD, BWS
input registers controlled by the rising edge of the input clock
(K\K).

CY7C1268V18 is described in the following sections. The same
basic descriptions apply to CY7C1266V18, CY7C1277V18, and
CY7C1270V18.

Read Operations

The CY7C1268V18 is organized internally as a singl e array of
2M x 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
R/W

HIGH and LD LOW at the rising edge of the positive input
clock (K). Following the next two K
sponding 18-bit word of data from this address location is driven
onto the Q
subsequent rising edge of K the next 18-bit data word is driven
onto the Q
rising edge of the Input clock (K and K

, using K as the output timing reference. On the

[17:0]

. The requested data is valid 0.45 ns from the

[17:0]

logic, each read access must be allowed to complete. Read
accesses can be initiated on every rising edge of the positive
input clock (K).

When read access is deselected, the CY7C1268V18 completes
the pending Read transactions. Synchronous internal circuitry
automatically tri-states the outputs following the next rising edge
of the negative input clock (K
transition between devices without the insertion of wait states in
a depth expanded memory.

Write Operations

Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to Address inputs is stored in the Write
Address register. On the following K clock rise, the data
presented to D
Data register provided BWS
subsequent rising edge of the Negative Input Clock (K
mation presented to D
register provided BWS
of data are then written into the memory array at the specified
location. Write accesses can be initiated on every rising edge of
the positive input clock (K). Doing so pipelines the data flow such
that 18 bits of data can be transferred into the device on every
rising edge of the input clocks (K and K

When write access is deselected, the device ignores all inputs
after the pending write operations have been completed.

is latched and stored into the 18-bit Write

[17:0]

[17:0]

are both asserted active. The 36 bits

[1:0]

) pass through input registers

[x:0]

) pass through output registers

[x:0]

) inputs pass through

[0:X]

). All

).

clock rising edges, the corre-

). To maintain the internal

). This enables a seamless

are both asserted active. On the

[1:0]

), the infor-

is also stored into the Write Data

).

Byte Write Operations

Byte write operations are supported by the CY7C1268V18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS
BWS

, which are sampled with each set of 18-bit data words.

1

Asserting the appropriate Byte Write Select input during the data

and

0

portion of a write latches the data being presented and written
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
to that byte to remain unaltered. This feature can be used to
simplify read/modify/write operations to a byte write operation.

Double Data Rate Operation

The CY7C1268V18 enables high-performance operation
through high clock frequencies (achieved through pipelining) and
DDR mode of operation. The CY7C1268V18 requires three No
Operation (NOP) cycles when transitioning from a read to a write
cycle.

If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information must be stored
because the SRAM cannot perform the last word write to the
array without conflicting with the read. The data stays in this
register until the next write cycle occurs. On the first write cycle
after the read(s), the stored data from the earlier write is written
into the SRAM array. This is called a Posted Write.

If a read is performed on the same address on which a write is
performed in the previous cycle, the SRAM reads out the most
current data. The SRAM does this by bypassing the memory
array and reading the data from the registers.

Depth Expansion

Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15%, is between 175Ω and 350Ω
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.

to enable the SRAM to adjust its output

SS

, with V

=1.5V. The

DDQ

Echo Clocks

Echo clocks are provided on the DDR-II+ to simplify data capture
on high speed systems. Two echo clocks are generated by the
DDR-II+. CQ is referenced with respect to K and CQ
enced with respect to K

. These are free running clocks and are

is refer-

synchronized to the input clock of the DDR-II+. The timing for the
echo clocks is shown in “Switching Characteristics” on page 22.

Valid Data Indicator (QVLD)

QVLD is provided on the DDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the DDR-II+ device
along with data output. This signal is also edge aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.

Document Number: 001-06347 Rev. *D Page 8 of 27

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CY7C1268V18, CY7C1270V18

Delay Lock Loop (DLL)

Notes

2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑

represents rising edge.

3. Device powers up deselected with the outputs in a tri-state condition.

4. “A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst.

5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second, and third clock cycles succeeding the “t ” clo ck cycle.

6. Data inputs are registered at K and K

rising edges. Data outputs are delivered on K and K rising edges.

7. Cypress recommends that K = K

= HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission li ne charging

symmetrically.

These chips use a DLL that is designed to function between 120
MHz and the specified maximum clock frequency. The DLL may
be disabled by applying ground to the DOFF

pin. When the DLL
is turned off, the device behaves in DDR-I mode (with 1.0 cycle
latency and a longer access time). For more information, refer to

Application Example

Figure 1 shows two DDR-II+ used in an application.

Figure 1. Application Example

the application note, DLL Considerations in
QDRII/DDRII/QDRII+/DDRII+. The DLL can also be reset by

slowing or stopping the input clocks K and K

for a minimum of 30
ns. However, it is not necessary for the DLL to be reset to lock to
the frequency you want. During power up, when the DOFF is tied
HIGH, the DLL is locked after 2048 cycles of stable clock.

ZQ

CQ/CQ

K

K

R = 250ohms

DQ
A

SRAM#2

LD R/W

BUS

MASTER

(CPU or ASIC)

Echo Clock1/Echo Clock1
Echo Clock2/Echo Clock2

Addresses

Cycle Start

R/W
Source CLK
Source CLK

DQ

DQ
A

SRAM#1

LD R/W

Truth Table

The truth table for CY7C1266V18, CY7C1277V18, CY7C1268V18, and CY7C1270V18 follows.

Operation K LD R/W DQ DQ

Write Cycle:
Load address; wait one cycle; input write data on consecutive
K and K

rising edges.

Read Cycle: (2.5 cycle Latency)
Load address; wait two and half cycle; read data on consec­utive K

and K rising edges.

L-H L L D(A) at K(t + 1) ↑ D(A + 1) at K(t + 1) ↑

L-H L H Q(A) at K

ZQ

CQ/CQ

K

K

[2, 3, 4, 5, 6, 7]

R = 250ohms

(t + 2) ↑ Q(A + 1) at K(t + 3) ↑

NOP: No Operation L-H H X High-Z High-Z
Standby: Clock Stopped Stopped X X Previous State Previous State

Document Number: 001-06347 Rev. *D Page 9 of 27

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CY7C1268V18, CY7C1270V18

Write Cycle Descriptions

Note

8. Assumes a write cycle was initiated per the Write Cycle Descriptions tables. NWS

0

, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions

of a write cycle, as long as the setup and hold requirements are met.

The write cycle description table for CY7C1266V18 and CY7C1268V18 follows.

[2, 8]

BWS0/

NWS

0

BWS1/

NWS

K

1

K

Comments

L L L–H – During the data portion of a write sequence:

CY7C1266V18 − both nibbles (D
CY7C1268V18 − both bytes (D

) are written into the device.

[7:0]

) are written into the device.

[17:0]

L L – L-H During the data portion of a write sequence:

CY7C1266V18 − both nibbles (D
CY7C1268V18 − both bytes (D

) are written into the device.

[7:0]

) are written into the device.

[17:0]

L H L–H – During the data portion of a write sequence:

CY7C1266V18 − only the lower nibble (D
CY7C1268V18 − only the lower byte (D

) is written into the device, D

[3:0]

) is written into the device, D

[8:0]

L H – L–H During the data portion of a write sequence:

CY7C1266V18 − only the lower nibble (D
CY7C1268V18 − only the lower byte (D

) is written into the device, D

[3:0]

) is written into the device, D

[8:0]

H L L–H – During the data portion of a write sequence:

CY7C1266V18 − only the upper nibble (D
CY7C1268V18 − only the upper byte (D

) is written into the device, D

[7:4]

) is written into the device, D

[17:9]

H L – L–H During the data portion of a write sequence:

CY7C1266V18 − only the upper nibble (D
CY7C1268V18 − only the upper byte (D

) is written into the device, D

[7:4]

) is written into the device, D

[17:9]

H H L–H – No data is written into the devices during this portion of a write operation.
H H – L–H No data is written into the devices during this portion of a write operation.

remains unaltered.

[7:4]

remains unaltered.

[17:9]

remains unaltered.

[7:4]

remains unaltered.

[17:9]

remains unaltered.

[3:0]

remains unaltered.

[8:0]

remains unaltered.

[3:0]

remains unaltered.

[8:0]

Write Cycle Descriptions

The write cycle description table for CY7C1277V18 follows.

BWS

L L-H – During the data portion of a write sequence, the single byte (D
L – L-H During the data portion of a write sequence, the single byte (D

K K Comments

0

[2, 8]

[8:0]
[8:0]

H L-H – No data is written into the device during this portion of a write operation.
H – L-H No data is written into the device during this portion of a write operation.

) is written into the device.
) is written into the device.

Document Number: 001-06347 Rev. *D Page 10 of 27

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CY7C1268V18, CY7C1270V18

Write Cycle Descriptions

The write cycle description table for CY7C1270V18 follows.

[2, 8]

BWS0BWS1BWS2BWS3K K Comments

LLLLL-H–During the data portion of a write sequence, all four bytes (D

into the device.

LLLL–L-HDuring the data portion of a write sequence, all four bytes (D

into the device.

L H H H L-H – During the data portion of a write sequence, only the lower byte (D

written into the device. D

remains unaltered.

[35:9]

L H H H – L-H During the data portion of a write sequence, only the lower byte (D

written into the device. D

remains unaltered.

[35:9]

H L H H L-H – During the data portion of a write sequence, only the byte (D

into the device. D

[8:0]

and D

remain unaltered.

[35:18]

H L H H – L-H During the data portion of a write sequence, only the byte (D

into the device. D

[8:0]

and D

remain unaltered.

[35:18]

H H L H L-H – During the data portion of a write sequence, only the byte (D

into the device. D

[17:0]

and D

remain unaltered.

[35:27]

H H L H – L-H During the data portion of a write sequence, only the byte (D

into the device. D

[17:0]

and D

remain unaltered.

[35:27]

H H H L L-H – During the data portion of a write sequence, only the byte (D

into the device. D

remains unaltered.

[26:0]

H H H L – L-H During the data portion of a write sequence, only the byte (D

into the device. D

remains unaltered.

[26:0]

) are written

[35:0]

) are written

[35:0]

) is written

[17:9]

) is written

[17:9]

[26:18]

[26:18]

[35:27]

[35:27]

) is

[8:0]

) is

[8:0]

) is written

) is written

) is written

) is written

HHHHL-H–No data is written into the device during this portion of a write operation.
HHHH–L-HNo data is written into the device during this portion of a write operation.

Document Number: 001-06347 Rev. *D Page 11 of 27

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CY7C1268V18, CY7C1270V18

IEEE 1149.1 Serial Boundary Scan (JTAG)

These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA p ackage. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8V IO logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (V
prevent device clocking. TDI and TMS are internally pulled up
and may be unconnected. They may alternatively be connected
to V

through a pull up resistor. TDO must be left unconnected.

DD

Upon power up, the device comes up in a reset state, which does
not interfere with the operation of the device.

Test Access Port – Test Clock

The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.

Test Mode Select

The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. You can leave this pin
unconnected if the TAP is not used. The pin is pulled up inter­nally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the i nstructio n that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the “TAP Controller State

Diagram” on page 14. TDI is internally pulled up and can be

unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.

Test Data-Out (TDO)

The TDO output pin is used to serially clock data-out from the
registers. Whether the output is active depends on the current
state of the TAP state machine (see “Instruction Codes” on

page 17). The output changes on the falling edge of TCK. TDO

is connected to the least significant bit (LSB) of any register.

Performing a TAP Reset

A reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO pins and
scans data into and out of the SRAM test circuitry. Only one
register can be selected at a time through the instruction
registers. Data is serially loaded into the TDI pin on the rising
edge of TCK. Data is output on the TDO pin on the falling edge
of TCK.

SS

) to

Instruction Register

Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins as shown in “TAP Controller Block Diagram” on

page 15. Upon power up, the instruction register is loaded with

the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.

When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to enable fault
isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This shifts data through the SRAM with minimal
delay. The bypass register is set LOW (V
instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are also
included in the scan register to reserve pins for higher de nsity
devices.

The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.

“Boundary Scan Order” on page 18 shows the order in which the

bits are connected. Each bit corresponds to one of the bumps on
the SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in “Identification Register Definitions” on

page 17.

) when the BYPASS

SS

TAP Instruction Set

Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in “Instruction

Codes” on page 17. Three of these instructions are listed as

RESERVED and must not be used. The other five instructions
are described in this section in detail.

Instructions are loaded into the TAP controller during the Shif t-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI a nd TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.

Document Number: 001-06347 Rev. *D Page 12 of 27

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CY7C1268V18, CY7C1270V18

IDCODE

The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register upon
power up or whenever the TAP controller is in a Test-Logic-Reset
state.

SAMPLE Z

The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High-Z state until the next command is issued during the
Update-IR state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.

Be aware that the TAP controller clock can only operate at a
frequency up to 20 MHz, although the SRAM clock operates
more than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output may undergo a transition.
The TAP may then try to capture a signal while in transition
(metastable state). This does not harm the device, but there is
no guarantee as to the value that is captured. Repeatable results
may not be possible.

To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (t
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK

After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.

and tCH). The SRAM clock input might not be captured

CS

captured in the boundary scan register.

PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required — that is, while data captured
is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.

EXTEST

The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.

EXTEST Output Bus Tri-State

IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.

Reserved

These instructions are not implemented but are reserved for
future use. Do not use these instructions.

Document Number: 001-06347 Rev. *D Page 13 of 27

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CY7C1268V18, CY7C1270V18

TAP Controller State Diagram

TEST-LOGIC
RESET

TEST-LOGIC/
IDLE

SELECT
DR-SCAN

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

EXIT2-DR

UPDATE-DR

SELECT
IR-SCAN

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDATE-IR

1

0

1

1

0

1

0

1

0

0

0

1

1

1

0

1

0

1

0

0

0

1

0

1

1

0

1

0

0

1

1

0

Note

9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

The state diagram for the TAP controller follows.

[9]

Document Number: 001-06347 Rev. *D Page 14 of 27

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CY7C1268V18, CY7C1270V18

TAP Controller Block Diagram

0

012..

29

3031

Boundary Scan Register

Identification Register

012..

.

.

108

012

Instruction Register

Bypass Register

Selection
Circuitry

Selection
Circuitry

TAP Controller

TDI

TDO

TCK
TMS

Notes

10.These characteristics apply to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in “Electrical Characteristics” on page 20.

11.Overshoot: V

IH

(AC) < V

DDQ

+ 0.3V (pulse width less than t

CYC

/2). Undershoot: VIL(AC) > − 0.3V (pulse width less than t

CYC

/2).

12.All voltage refers to ground.

TAP Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions Min Max Unit

V
V
V
V
V
V
I

OH1
OH2
OL1
OL2
IH
IL

X

Output HIGH Voltage I
Output HIGH Voltage I
Output LOW Voltage IOL = 2.0 mA 0.4 V
Output LOW Voltage IOL = 100 μA0.2V
Input HIGH Voltage 0.65VDDV
Input LOW Voltage –0.3 0.35V
Input and OutputLoad Current GND ≤ VI ≤ V

[10, 11, 12]

= −2.0 mA 1.4 V

OH

= −100 μA1.6 V

OH

DD

+ 0.3 V

DD

DD

−55μA

V

Document Number: 001-06347 Rev. *D Page 15 of 27

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TAP AC Switching Characteristics

t

TL

t

TH

(a)

TDO

C

L

= 20 pF

Z

0

= 50Ω

GND

0.9V

50Ω

1.8V

0V

ALL INPUT PULSES

0.9V

Test Clock

Test Mode Select

TCK

TMS

Test Data In
TDI

Test Data Out

t

TCYC

t

TMSH

t

TMSS

t

TDIS

t

TDIH

t

TDOV

t

TDOX

TDO

Notes

13.t

CS

and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

14.Test conditions are specified using the load in TAP AC Test Conditions. t

R/tF

= 1 ns.

Over the Operating Range

Parameter Description Min Max Unit

t

TCYC

t

TF

t

TH

t

TL

TCK Clock Cycle Time 50 ns
TCK Clock Frequency 20 MHz
TCK Clock HIGH 20 ns
TCK Clock LOW 20 ns

Setup Times

t

TMSS

t

TDIS

t

CS

TMS Setup to TCK Clock Rise 5 ns
TDI Setup to TCK Clock Rise 5 ns
Capture Setup to TCK Rise 5 ns

Hold Times

t

TMSH

t

TDIH

t

CH

TMS Hold after TCK Clock Rise 5 ns
TDI Hold after Clock Rise 5 ns
Capture Hold after Clock Rise 5 ns

Output Times

t

TDOV

t

TDOX

TCK Clock LOW to TDO Valid 10 ns
TCK Clock LOW to TDO Invalid 0 ns

[13, 14]

TAP Timing and Test Conditions

Figure 2 shows the TAP timing and test conditions.

Figure 2. TAP Timing and Test Conditions

[14]

Document Number: 001-06347 Rev. *D Page 16 of 27

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Identification Register Definitions

Instruction

Field

Revision
Number (31:29)

Cypress Device
ID (28:12)

Cypress JEDEC
ID (11:1)

ID Register
Presence (0)

CY7C1266V18 CY7C1277V18 CY7C1268V18 CY7C1270V18

000 000 000 000 Version number.

11010111000000111 11010111000001111 11010111000010111 1101011 1000100111 Defines the type

00000110100 00000110100 00000110100 00000110100 Enables unique

1 1 1 1 Indicates the

Value

Scan Register Sizes

Register Name Bit Size

Instruction 3
Bypass 1
ID 32
Boundary Scan 109

Description

of SRAM.

identification of
SRAM vendor.

presence of an
ID register.

Instruction Codes

Instruction Code Description

EXTEST 000 Captures the input/output ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between

SAMPLE Z 010 Captures the input/output contents. Places the boundary scan register between

RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the input/output ring contents. Places the boundary scan register

RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 1 1 1 Places the bypass register between TDI and TDO. This operation does not affect

TDI and TDO. This operation does not affect SRAM operation.

TDI and TDO. Forces all SRAM output drivers to a High-Z state.

between TDI and TDO. Does not affect the SRAM operation.

SRAM operation.

Document Number: 001-06347 Rev. *D Page 17 of 27

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CY7C1268V18, CY7C1270V18

Boundary Scan Order

Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID

0 6R 28 10G 56 6A 84 1J
16P299G575B852J
2 6N 30 11F 58 5A 86 3K
3 7P 31 11G 59 4A 87 3J
47N329F605C882K
5 7R 33 10F 61 4B 89 1K
6 8R 34 11E 62 3A 90 2L
7 8P 35 10E 63 2A 91 3L
8 9R 36 10D 64 1A 92 1M

9 11P 37 9E 65 2B 93 1L
10 10P 38 10C 66 3B 94 3N
11 10N 39 11D 67 1C 95 3M
12 9P 40 9C 68 1B 96 1N
13 10M 41 9D 69 3D 97 2M
14 11N 42 11B 70 3C 98 3P
15 9M 43 11C 71 1D 99 2N
16 9N 44 9B 72 2C 100 2P
17 11L 45 10B 73 3E 101 1P
18 11M 46 11A 74 2D 102 3R
19 9L 47 10A 75 2E 103 4R
20 10L 48 9A 76 1E 104 4P
21 11K 49 8B 77 2F 105 5P
22 10K 50 7C 78 3F 106 5N
23 9J 51 6C 79 1G 107 5R
24 9K 52 8A 80 1F 108 Internal
25 10J 53 7A 81 3G
26 11J 54 7B 82 2G
27 11H 55 6B 83 1H

Document Number: 001-06347 Rev. *D Page 18 of 27

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CY7C1268V18, CY7C1270V18

Power Up Sequence in DDR-II+ SRAM

K

K

Fix HIGH (tie to V

DDQ

)

VDD/V

DDQ

DOFF

Clock Start (Clock Starts after VDD/V

DDQ

is Stable)

Unstable Clock > 2048 Stable Clock

Start Normal
Operation

~

~

~

VDD/V

DDQ

Stable (< + 0.1V DC per 50 ns)

DDR-II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations. During
power up, when the DOFF is tied HIGH, the DLL gets locked after
2048 cycles of stable clock.

Power Up Sequence

■ Apply power with DOFF tied HIGH (all other inputs can be HIGH

or LOW)

❐ Apply V
❐ Apply V

■ Provide stable power and clock (K, K) for 2048 cycles to lock

the DLL

before V

DD

before V

DDQ

DDQ

or at the same time as V

REF

REF

Power Up Waveforms

Figure 3. Power Up Waveforms

DLL Constraints

■ DLL uses K clock as its synchronizing input. The input must

have low phase jitter, which is specified as t

■ The DLL functions at frequencies down to 120 MHz.

■ If the input clock is unstable and the D LL is enabl ed, the n the

DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. T o avoid this, provide 2048 cycles stable clock
to relock to the desired clock frequency.

KC Var

.

Document Number: 001-06347 Rev. *D Page 19 of 27

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CY7C1268V18, CY7C1270V18

Maximum Ratings

Notes

15.Power up: assumes a linear ramp from 0V to V

DD

(min) within 200 ms. During this time V

IH

< V

DD

and V

DDQ

< VDD.

16.Outputs are impedance controlled. I

OH

= –(V

DDQ

/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

17.Outputs are impedance controlled. I

OL

= (V

DDQ

/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

18.V

REF

(min) = 0.68V or 0.46V

DDQ

, whichever is larger, V

REF

(max) = 0.95V or 0.54V

DDQ

, whichever is smaller.

19.The operation current is calculated with 50% read cycle and 50% write cycle.

Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.

Storage Temperature ................................–65°C to + 150°C

Ambient Temperature with Powe r Applied. –55°C to + 125°C

Supply Voltage on VDD Relative to GND.......–0.5V to + 2.9V

Supply Voltage on V

DC Applied to Outputs in High-Z .........–0.5V to V

DC Input Voltage

Relative to GND..... –0.5V to + V

DDQ

[11]

...............................–0.5V to VDD + 0.3V

DDQ

DD

+ 0.3V

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V

Latch up Current..................................................... >200 mA

Operating Range

Range

T emperature V

Com’l 0°C to +70°C 1.8 ± 0.1V 1.4V to V
Ind’l –40°C to +85°C

Ambient

DD

[15]

V

DDQ

[15]

DD

Electrical Characteristics

Over the Operating Range

DC Electrical Characteristics

Parameter Description Test Conditions Min Typ Max Unit

V

DD

V

DDQ

V

OH

V

OL

V

OH(LOW)

V

OL(LOW)

V

IH

V

IL

I

X

I

OZ

V

REF

[19]

I

DD

I

SB1

Power Supply Voltage 1.7 1.8 1.9 V
IO Supply Voltage 1.4 1.5 V
Output HIGH Voltage Note 16 V
Output LOW Voltage Note 17 V
Output HIGH Voltage IOH = –0.1 mA, Nominal Impedance V
Output LOW Voltage IOL = 0.1 mA, Nominal Impedance V
Input HIGH Voltage V
Input LOW Voltage –0.15 V
Input Leakage Current GND ≤ VI ≤ V
Output Leakage Current GND ≤ VI ≤ V
Input Reference Voltage
VDD Operating Supply V

Automatic Power Down
Current

[12]

DD

/2 – 0.12 V

DDQ

/2 – 0.12 V

DDQ

– 0.2 V

DDQ

SS

+ 0.1 V

REF

DDQ

Output Disabled – 2 2 μA

= 1/t

DDQ,

OUT

CYC

= 0 mA,

300 MHz 1000 mA
333 MHz 1080 mA

[18]

Typical Value = 0.75V 0.68 0.75 0.95 V

= Max., I

DD

f = f

MAX

–2 2 μA

/2 + 0.12 V

DDQ

/2 + 0.12 V

DDQ

DDQ

0.2 V
+ 0.15 V

DDQ

REF

375 MHz 1210 mA
400 MHz 1280 mA

Max. VDD,
Both Ports Deselected,

≥ VIH or VIN ≤ VIL

V

IN

f = f
Inputs Static

MAX

= 1/t

CYC

,

300 MHz 290 mA
333 MHz 300 mA
375 MHz 320 mA
400 MHz 340 mA

– 0.1 V

V

V

AC Input Requirements

Over the Operating Range

Parameter Description Test Conditions Min Typ Max Unit

V

IH

V

IL

Document Number: 001-06347 Rev. *D Page 20 of 27

Input HIGH Voltage V
Input LOW Voltage –0.24 – V

[11]

+ 0.2 – V

REF

DDQ

REF

+ 0.24 V
– 0.2 V

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CY7C1266V18, CY7C1277V18
CY7C1268V18, CY7C1270V18

Capacitance

1.25V

0.25V

R = 50Ω

5pF

INCLUDING

JIG AND

SCOPE

ALL INPUT PULSES

Device

R

L

= 50Ω

Z

0

= 50Ω

V

REF

= 0.75V

V

REF

= 0.75V

[21]

0.75V

Under
Test

0.75V

Device
Under
Test

OUTPUT

0.75V

V

REF

V

REF

OUTPUT

ZQ

ZQ

(a)

Slew Rate = 2 V/ns

RQ =
250

Ω

(b)

RQ =
250

Ω

Notes

20.Tested initially and after any design or process change th at may affect these parameters.

21.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, V

REF

= 0.75V , RQ = 250Ω, V

DDQ

= 1.5V, input

pulse levels of 0.25V to 1.25V, and output loading of the specified I

OL/IOH

and load capacitance shown in (a) of AC Test Loads and Waveforms.

[20]

Parameter Description Test Conditions Max Unit

Input Capacitance TA = 25°C, f = 1 MHz,

C

IN

C

CLK

C

O

Clock Input Capacitance 4 pF
Output Capacitance 5 pF

V
V

DD
DDQ

= 1.8V

= 1.5V

5pF

Thermal Resistance

[20]

Parameter Description Test Conditions

Θ

JA

Θ

JC

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.

AC Test Loads and Waveforms

Figure 4. AC Test Loads and Waveforms

165 FBGA

Package

16.25 °C/W

2.91 °C/W

Unit

Document Number: 001-06347 Rev. *D Page 21 of 27

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Switching Characteristics

Notes

22.When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency , it requires the input timing of the freque ncy range in which it is being
operated and outputs data with the output timing of that frequency range.

23.This part has an internal voltage regulator; t

POWER

is the time that the power must be supplied above V

DD

minimum initially before a read or write operation is initiated.

24.These parameters are extrapolated from the input timing parameters (t

KHKH

– 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t

KC Var

) is already

included in the t

KHKH

). These parameters are only guaranteed by design and are not tested in production.

25.t

CHZ

, t

CLZ

, are specified with a load capacitance of 5 pF as in (b) of“AC Test Loads and Waveforms” on page 21. Transition is measured ±100 mV from steady-state

voltage.

26.At any voltage and temperature t

CHZ

is less than t

CLZ

and t

CHZ

less than tCO.

27.t

QVLD

spec is applicable for both rising and falling edges of QVLD signal.

28.Hold to >V

IH

or <VIL.

Over the Operating Range

Cypress

Parameter

t

POWER

t

CYC

t

KH

t

KL

t

KHKH

Consortium

Parameter

t

KHKH

t

KHKL

t

KLKH

t

KHKH

Setup Times

t

SA

t

SC

t

SCDDR

t

SD

t

AVKH

t

IVKH

t

IVKH

t

DVKH

Hold Times

t

HA

t

HC

t

HCDDR

t

HD

t

KHAX

t

KHIX

t

KHIX

t

KHDX

Output Times

t

CO

t

DOH

t

CCQO

t

CQOH

t

CQD

t

CQDOHtCQHQX

t

CQH

t

CQHCQHtCQHCQH

t

CHZ

t

CLZ

t

QVLD

t

CHQV

t

CHQX

t

CHCQV

t

CHCQX

t

CQHQV

t

CQHCQL

t

CHQZ

t

CHQX1

t

CQHQVLD

DLL Timing

t

KC Var

t

KC lock

t

KC ResettKC Reset

t

KC Var

t

KC lock

[21, 22]

VDD(Typical) to the first Access
K Clock Cycle Time 2.50 8.4 2.66 8.4 3.0 8.4 3.3 8.4 ns
Input Clock (K/K) HIGH 0.4 – 0.4 – 0.4 – 0.4 – t
Input Clock (K/K) LOW 0.4 – 0.4 – 0.4 – 0.4 – t
K Clock Rise to K Clock Rise

(rising edge to rising edge)

Address Setup to K Clock Rise 0.4 – 0.4 – 0.4 – 0.4 – ns
Control Setup to K Clock Rise (LD, R/W) 0.4 – 0.4 – 0.4 – 0.4 – ns
Double Data Rate Control Setup to Clock

(K, K

) Rise (BWS0, BWS1, BWS2, BWS3)

D

Setup to Clock (K/K) Rise 0.28 – 0.28 – 0.28 – 0.28 – ns

[X:0]

Address Hold after K Clock Rise
Control Hold after K Clock Rise (LD, R/W)
Double Data Rate Control Hold after Clock

(K/K

) Rise (BWS0, BWS1, BWS2, BWS3)

D

Hold after Clock (K/K) Rise 0.28 – 0.28 – 0.28 – 0.28 – ns

[X:0]

K/K Clock Rise to Data Valid – 0.45 – 0.45 – 0.45 – 0.45 ns
Data Output Hold after K/K Clock Rise (Active

to Active)
K/K Clock Rise to Echo Clock Valid – 0.45 – 0.45 – 0.45 – 0.45 ns
Echo Clock Hold after K/K Clock Rise –0.45 – –0.45 – –0.45 – –0.45 – ns
Echo Clock High to Data Valid – 0.2 0.2 0.2 0.2 ns
Echo Clock High to Data Invalid –0.2 – –0.2 – –0.2 – –0.2 – ns
Output Clock (CQ/CQ) HIGH
CQ Clock Rise to CQ Clock Rise

(rising edge to rising edge)
Clock (K/K) Rise to High-Z

(Active to High-Z)
Clock (K/K) Rise to Low-Z
Echo Clock High to QVLD Valid

Clock Phase Jitter – 0.20 – 0.20 – 0.20 – 0.20 ns
DLL Lock Time (K) 2048 – 2048 – 2048 – 2048 – Cycles
K Static to DLL Reset

Description

[25, 26]

[25, 26]

[28]

[24]

[23]

[27]

[24]

400 MHz 375 MHz 333 MHz 300 MHz

Min Max Min Max Min Max Min Max

Unit

1–1–1–1–ms

CYC
CYC

1.06–1.13–1.28–1.40– ns

0.28–0.28–0.28–0.28– ns

0.4 – 0.4 – 0.4 – 0.4 – ns

0.4 – 0.4 – 0.4 – 0.4 – ns

0.28–0.28–0.28–0.28– ns

–0.45 – –0.45 – –0.45 – –0.45 – ns

0.81–0.88–1.03–1.15– ns

0.81–0.88–1.03–1.15– ns

–0.45–0.45–0.45–0.45ns

–0.45 – –0.45 – –0.45 – –0.45 – ns
–0.20 0.20 –0.20 0.20 –0.20 0.20 –0.20 0.20 ns

30–30–30–30– ns

Document Number: 001-06347 Rev. *D Page 22 of 27

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CY7C1268V18, CY7C1270V18

Switching Waveforms

Notes

29.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

30.Outputs are disabled (High-Z) one clock cycle after a NOP.

Read/Write/Deselect Sequence

[29, 30]

Figure 5. Waveform for 2.5 Cycle Read Latency

K

K

LD

R/W

A

QVLD

DQ

NOP

1

t

KH

READ

2

SC

SA

A0

t

HC

t

HA

t

CYC

t

KL

t

t

(Read Latency = 2.5 Cycles)

READ

3

A1

t

KHKH

t

QVLD

NOP

4

t

CLZ

t

t

t

CO

CCQO

CQOH

NOP WRITEWRITE

5

Q00

t

QVLD

Q01

Q10

t

DOH

NOP

6

Q11

t

CQD

t

CQDOH

A2

t

CHZ

t

QVLD

NOP

11

12

Q40

READ

7

89

A3

t

HD

D20

t

SD

D21

t

SD

A4

D30 D31

t

NOP

10

HD

CQ

CQ

t

CQOH

t

CCQO

t

CQH

Document Number: 001-06347 Rev. *D Page 23 of 27

t

CQHCQH

DON’T CARE

UNDEFINED

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CY7C1268V18, CY7C1270V18

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit

www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code

400 CY7C1266V18-400BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1277V18-400BZC
CY7C1268V18-400BZC
CY7C1270V18-400BZC
CY7C1266V18-400BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1277V18-400BZXC
CY7C1268V18-400BZXC
CY7C1270V18-400BZXC
CY7C1266V18-400BZI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial
CY7C1277V18-400BZI
CY7C1268V18-400BZI
CY7C1270V18-400BZI
CY7C1266V18-400BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1277V18-400BZXI
CY7C1268V18-400BZXI
CY7C1270V18-400BZXI

375 CY7C1266V18-375BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1277V18-375BZC
CY7C1268V18-375BZC
CY7C1270V18-375BZC
CY7C1266V18-375BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1277V18-375BZXC
CY7C1268V18-375BZXC
CY7C1270V18-375BZXC
CY7C1266V18-375BZI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial
CY7C1277V18-375BZI
CY7C1268V18-375BZI
CY7C1270V18-375BZI
CY7C1266V18-375BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1277V18-375BZXI
CY7C1268V18-375BZXI
CY7C1270V18-375BZXI

Package
Diagram Package Type

Operating

Range

Document Number: 001-06347 Rev. *D Page 24 of 27

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CY7C1268V18, CY7C1270V18

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit

www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code

333 CY7C1266V18-333BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1277V18-333BZC
CY7C1268V18-333BZC
CY7C1270V18-333BZC
CY7C1266V18-333BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1277V18-333BZXC
CY7C1268V18-333BZXC
CY7C1270V18-333BZXC
CY7C1266V18-333BZI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial
CY7C1277V18-333BZI
CY7C1268V18-333BZI
CY7C1270V18-333BZI
CY7C1266V18-333BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1277V18-333BZXI
CY7C1268V18-333BZXI
CY7C1270V18-333BZXI

300 CY7C1266V18-300BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1277V18-300BZC
CY7C1268V18-300BZC
CY7C1270V18-300BZC
CY7C1266V18-300BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1277V18-300BZXC
CY7C1268V18-300BZXC
CY7C1270V18-300BZXC
CY7C1266V18-300BZI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial
CY7C1277V18-300BZI
CY7C1268V18-300BZI
CY7C1270V18-300BZI
CY7C1266V18-300BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1277V18-300BZXI
CY7C1268V18-300BZXI
CY7C1270V18-300BZXI

Package
Diagram Package Type

Operating

Range

Document Number: 001-06347 Rev. *D Page 25 of 27

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Package Diagram

!

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51-85195-*A

Figure 6. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195

Document Number: 001-06347 Rev. *D Page 26 of 27

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Document History Page

Document Title: CY7C1266V18/CY7C1277V18/CY7C1268V18/CY7C1270V18, 36-Mbit DDR-II+ SRAM 2-Word
Burst Architecture (2.5 Cycle Read Latency)

Document Number: 001-06347

REV. ECN No. Issue Date

** 425689 See ECN NXR New Data Sheet

*A 461639 See ECN NXR Revised the MPN’s from

*B 497628 See ECN NXR Changed the V

*C 1093183 See ECN VKN Converted from preliminary to final

*D 2198506 See ECN VKN/AESA Added footnote# 19 related to I

Orig. of
Change

Description of Change

CY7C1277AV18 to CY7C1277V18
CY7C1268AV18 to CY7C1268V18
CY7C1270AV18 to CY7C1270V18
Changed t
t

, t

TDIH

AC Switching Characteristics table

and t

TH

from 10 ns to 5 ns and changed t

CH

from 40 ns to 20 ns, changed t

TL

, t

TMSS

from 20 ns to 10 ns in TAP

TDOV

TDIS

Modified Power-Up waveform

operating voltage to 1.4V to VDD in the Features section,

in Operating Range table and in the DC Electrical Characteristics table

DDQ

Added foot note in page# 1
Changed the Maximum rating of Ambient T emperature with Power Applied
from –10°C to +85°C to –55°C to +125°C
Changed V
Characteristics table and in the note below the table

(Max.) spec from 0.85V to 0.95V in the DC Electrical

REF

Updated foot note# 17 to specify Overshoot and Undershoot Spec
Updated Θ
Removed x9 part and its related information

JA

and Θ

JC

values

Updated footnote #24

Added x8 and x9 parts
Updated logic block diagram for x18 and x36 parts
Changed I
1210 mA for 375 MHz, 880 mA to 1080 mA for 333 MHz, 830 mA to 1000

values from 1080 mA to 1280 mA for 400 MHz, 980 mA to

DD

mA for 300 MHz
Changed I
mA for 333 MHz, 250 mA to 290 mA for 300 MHz

values from 300 mA to 320 mA for 375 MHz, 275 mA to 300

SB

Changed ΘJA value from 12.43 °C/W to 16.25 °C/W
Changed t
Updated Ordering Information table

max spec to 8.4 ns for all speed bins

CYC

DD

, tCS, t

TMSH

,

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