CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
36-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.0 Cycle Read Latency)
Features
Note
1. The QDR consortium specification for V
DDQ
is 1.5V + 0.1V . The Cypress QDR devices exceed the QDR consort ium specification and are cap able of supporting
V
DDQ
= 1.4V to VDD.
Configurations
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 300 MHz to 375 MHz clock for high bandwidth
■ 4-Word Burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 750 MHz) at 375 MHz
■ Read latency of 2.0 clock cycles
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate Port Selects for depth expansion
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ Available in x8, x9, x18, and x36 configurations
■ Full data coherency providing most current data
■ Core V
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
= 1.8V ± 0.1V; IO V
DD
= 1.4V to V
DDQ
DD
[1]
With Read Cycle Latency of 2.0 cycles:
CY7C1241V18 – 4M x 8
CY7C1256V18 – 4M x 9
CY7C1243V18 – 2M x 18
CY7C1245V18 – 1M x 36
Functional Description
The CY7C1241V18, CY7C1256V18, CY7C1243V18, and
CY7C1245V18 are 1.8V Synchronous Pipelined SRAMs,
equipped with Quad Data Rate-II+ (QDR-II+) architecture.
QDR-II+ architecture consists of two separate ports to access
the memory array. The read port has dedicated data outputs to
support read operations and the write port has dedicated data
inputs to support write operations. QDR-II+ architecture has
separate data inputs and data outputs to completely eliminate
the need to “turn around” the data bus required with common IO
devices. Each port can be accessed through a common address
bus. Read and write addresses are latched on alterna te rising
edges of the input (K) clock. Accesses to the QDR-II+ read and
write ports are completely independent of one another. To
maximize data throughput, both read and write ports are
equipped with Double Data Rate (DDR) interfaces. Each
address location is associated with four 8-bit words
(CY7C1241V18), 9-bit words (CY7C1256V18), 18-bit words
(CY7C1243V18), or 36-bit words (CY7C1245V18), that burst
sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input
clocks (K and K
fying system design by eliminating bus “turn-arounds”.
Depth expansion is accomplished with Port Selects for each port.
Port selects enable each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K
registers controlled by the K or K
conducted with on-chip synchronous self-timed write circuitry.
), memory bandwidth is maximized while simpli-
input clocks. All data outputs pass through output
input clocks. Writes are
Selection Guide
Maximum Operating Frequency 375 333 300 MHz
Maximum Operating Current 1240 1120 1040 mA
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-06365 Rev. *D Revised March 12, 2008
Description 375 MHz 333 MHz 300 MHz Unit
[+] Feedback [+] Feedback
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Logic Block Diagram (CY7C1241V18)
1M x 8 Array
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
D
[7:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q
[7:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
16
20
8
32
8
NWS
[1:0]
V
REF
Write Add. Decode
Write
Reg
16
A
(19:0)
20
1M x 8 Array
1M x 8 Array
1M x 8 Array
Write
Reg
Write
Reg
Write
Reg
8
CQ
CQ
DOFF
QVLD
1M x 9 Array
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
D
[8:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q
[8:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
20
9
36
9
BWS
[0]
V
REF
Write Add. Decode
Write
Reg
18
A
(19:0)
20
1M x 9 Array
1M x 9 Array
1M x 9 Array
Write
Reg
Write
Reg
Write
Reg
9
CQ
CQ
DOFF
QVLD
Logic Block Diagram (CY7C1256V18)
Document Number: 001-06365 Rev. *D Page 2 of 28
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CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Logic Block Diagram (CY7C1243V18)
512K x 18 Array
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q
[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
19
18
72
18
BWS
[1:0]
V
REF
Write Add. Decode
Write
Reg
36
A
(18:0)
19
512K x 18 Array
512K x 18 Array
512K x 18 Array
Write
Reg
Write
Reg
Write
Reg
18
CQ
CQ
DOFF
QVLD
256K x 36 Array
CLK
A
(17:0)
Gen.
K
K
Control
Logic
Address
Register
D
[35:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q
[35:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
72
18
36
144
36
BWS
[3:0]
V
REF
Write Add. Decode
Write
Reg
72
A
(17:0)
18
256K x 36 Array
256K x 36 Array
256K x 36 Array
Write
Reg
Write
Reg
Write
Reg
36
CQ
CQ
DOFF
QVLD
Logic Block Diagram (CY7C1245V18)
Document Number: 001-06365 Rev. *D Page 3 of 28
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CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Pin Configurations
CY7C1241V18 (4M x 8)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
23
4
5
6
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
NC/72M A
NWS
1
KWPS
NC/144M
NC NC
NC
NC
NC
TDO
NC
NC
D5
NC
NC
NC
TCK
NC
NC
A NC/288M K NWS
0
V
SS
ANCA
NC V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
Q4
NC
V
DDQ
NC
NC
NC
NC
Q7
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
Q5 V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
A
NC
V
SS
A
A
A
D4 V
SS
NC V
SS
NC
NC
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
QVLD
NC
Q6
NC
D7
D6
V
DD
A
8
91011
NC
AA
RPS
CQ
A NC NC Q3
V
SS
NC NC D3
NC
V
SS
NC
Q2
NC
NC
NC
V
REF
NC
NC
V
DDQ
NC
V
DDQ
NC NC
V
DDQ
V
DDQ
V
DDQ
D1V
DDQ
NC
Q1
NC
V
DDQ
V
DDQ
NC
V
SS
NC D0
NC
TDITMS
V
SS
A
NC
A
NC
D2
NC
ZQ
NC
Q0
NC
NC
NC
NC
A
NC/144M
CY7C1256V18 (4M x 9)
23
4
5
6
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
NC/72M A NC K
WPS NC/144M
NC NC
NC
NC
NC
TDO
NC
NC
D6
NC
NC
NC
TCK
NC
NC
A NC/288M K BWS
0
V
SS
ANCA
NC V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
Q5
NC
V
DDQ
NC
NC
NC
NC
Q8
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
Q6 V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
A
NC
V
SS
A
A
A
D5 V
SS
NC V
SS
NC
NC
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
QVLD
NC
Q7
NC
D8
D7
V
DD
A
8
91011
Q0
AARPS
CQ
A
NC
NC Q4
V
SS
NC NC D4
NC
V
SS
NC
Q3
NC
NC
NC
V
REF
NC
NC
V
DDQ
NC
V
DDQ
NC NC
V
DDQ
V
DDQ
V
DDQ
D2V
DDQ
NC
Q2
NC
V
DDQ
V
DDQ
NC
V
SS
NC D1
NC
TDITMS
V
SS
A
NC
A
NC
D3
NC
ZQ
NC
Q1
NC
NC
D0
NC
A
NC
NC
Document Number: 001-06365 Rev. *D Page 4 of 28
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CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Pin Configurations (continued)
CY7C1243V18 (2M x 18)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
23
4
567
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
NC/144M A
BWS
1
KWPS
NC/288M
Q9 D9
NC
NC
NC
TDO
NC
NC
D13
NC
NC
NC
TCK
NC
D10
A NC K
BWS
0
V
SS
ANCA
Q10 V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
Q11
D12
V
DDQ
D14
Q14
D16
Q16
Q17
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
Q13 V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
A
V
SS
A
A
A
D11 V
SS
NC V
SS
Q12
NC
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
QVLD
NC
Q15
NC
D17
D15
V
DD
A
8
91011
Q0
A NC/72M
RPS
CQ
A NC NC Q8
V
SS
NC Q7 D8
NC
V
SS
NC
Q6
D5
NC
NC
V
REF
NC
Q3
V
DDQ
NC
V
DDQ
NC Q5
V
DDQ
V
DDQ
V
DDQ
D4V
DDQ
NC
Q4
NC
V
DDQ
V
DDQ
NC
V
SS
NC D2
NC
TDITMS
V
SS
A
NC
A
D7
D6
NC
ZQ
D3
Q2
D1
Q1
D0
NC
A
NC
CY7C1245V18 (1M x 36)
23
456
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
Q27
D27
D28
D34
DOFF
Q33
NC/288M NC/72M
BWS
2
K
WPS BWS
1
Q18
D18
Q30
D31
D33
TDO
Q28
D29
D22
D32
Q34
Q31
TCK
D35
D19
A
BWS
3
K
BWS
0
V
SS
ANCA
Q19 V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
Q20
D21
V
DDQ
D23
Q23
D25
Q25
Q26
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
Q22 V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
A
NC
V
SS
A
A
A
D20 V
SS
Q29 V
SS
Q21
D30
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
QVLD
Q32
Q24
Q35
D26
D24
V
DD
A
891011
Q0
A
NC/144M
RPS
CQ
A D17
Q17
Q8
V
SS
D16 Q7 D8
Q16
V
SS
D15
Q6
D5
D9
Q14
V
REF
Q11
Q3
V
DDQ
Q15
V
DDQ
D14 Q5
V
DDQ
V
DDQ
V
DDQ
D4V
DDQ
D12
Q4
Q12
V
DDQ
V
DDQ
D11
V
SS
D10 D2
Q10
TDITMS
V
SS
A
Q9
A
D7
D6
D13
ZQ
D3
Q2
D1
Q1
D0
Q13
A
Document Number: 001-06365 Rev. *D Page 5 of 28
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CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Pin Definitions
Pin Name IO Pin Description
D
[x:0]
Input-
Synchronous
WPS Input-
Synchronous
NWS
BWS
BWS
,
NWS
0
, BWS1,
0
, BWS
2
3
,
1
Synchronous
Synchronous
Input-
Input-
A Input-
Synchronous
Q
[x:0]
Outputs-
Synchronous
RPS Input-
Synchronous
QVLD Valid output
indicator
K Input-
Clock
K
Input-
Clock
Data Input Signals. Sampled on the rising edge of K and K
CY7C1241V18 − D
CY7C1256V18 − D
CY7C1243V18 − D
CY7C1245V18 − D
[7:0]
[8:0]
[17:0]
[35:0]
Write Port Select, Active LOW. Sampled on the rising edge of the K clock. When asserted
active, a Write operation is initiated. Deasserting deselects the write port. Deselecting the write
port causes D
to be ignored.
[x:0]
Nibble Write Select 0, 1, Active LOW (CY7C1241V18 Only). Sampled on the rising edge of
the K and K clocks when write operations are active. Used to select which nibble is written into
the device during the current portion of the write operations. NWS
controls D
[7:4]
.
All the nibble Write Selects are sampled on the same edge as the data. The corresponding nibble
of data is ignored by deselecting a nibble write se lect and is not written into the device.
Byte Write Select 0, 1, 2, and 3, Active LOW. Sampled on the rising edge of the K and K
during write operations. Selects which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C1256V18 − BWS
CY7C1243V18 − BWS0 controls D
CY7C1245V18 − BWS0 controls D
controls D
[35:27].
controls D
0
[8:0]
and BWS1 controls D
[8:0]
, BWS1 controls D
[8:0]
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select ignores the corresponding byte of data and not written into the device.
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These address inputs are multiplexed for both read and write operations. Internally, the
device is organized as 4M x 8 (4 arrays each of 1M x 8) for CY7C1241V18, 4M x 9 (4 arrays
each of 1M x 9) for CY7C1256V18, 2M x 18 (4 arrays each of 512K x 18) for CY7C1243V18
and 1M x 36 (4 arrays each of 256K x 36) for CY7C1245V18. Therefore, only 20 address inputs
are needed to access the entire memory array of CY7C1241V18 and CY7C1256V18, 19 address
inputs for CY7C1243V18, and 18 address inputs for CY7C1245V18. These inputs are ignored
when the appropriate port is deselected.
Data Output Signals. These pins drive out the requested data during a read operation. Valid
data is driven out on the rising edge of both the K and K
the read port is deselected, Q
CY7C1241V18 − Q
CY7C1256V18 − Q
CY7C1243V18 − Q
CY7C1245V18 − Q
[7:0]
[8:0]
[17:0]
[35:0]
are automatically tri-stated.
[x:0]
Read Port Select, Active LOW. Sampled on the rising edge of Positive Input Clock (K). When
active, a read operation is initiated. Deasserting causes the read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
tri-stated following the next rising edge of the K clock. Each read access consists of a burst of
four sequential transfers.
Valid Output Ind icator . The Q Valid indicates valid output data. QVLD is edge aligned with CQ
and CQ
.
Positive Input Clock Input. The rising edge of K captures synchronous inputs to the device
and drives out data through Q
rising edge of K.
when in single clock mode. All accesses are initiated on the
[x:0]
Negative Input Clock Input. K captures synchronous inputs being presented to the device and
drives out data through Q
when in single clock mode.
[x:0]
clocks during valid write operations.
controls D
0
and NWS1
[3:0]
clocks
[17:9].
, BWS2 controls D
[17:9]
[26:18]
, and BWS3
clocks during read operations. When
Document Number: 001-06365 Rev. *D Page 6 of 28
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CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Pin Definitions (continued)
Pin Name IO Pin Description
CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the
input clock (K) of the QDR-II+. The timing for the echo clocks is shown in “Switching Character-
istics” on page 23.
CQ
ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system
DOFF
TDO Output TDO for JTAG.
TCK Input TCK Pin for JTAG.
TDI Input TDI Pin for JTAG.
TMS Input TMS Pin for JTAG.
NC N/A Not Connected to the Die. Can be tied to any voltage level.
NC/72M N/A Not Connected to the Die. Can be tied to any voltage level.
NC/144M N/A Not Connected to the Die. Can be tied to any voltage level.
NC/288M N/A Not Connected to the Die. Can be tied to any voltage level.
V
REF
V
DD
V
SS
V
DDQ
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the
Input DLL Turn Off, Active LOW. Connecting this pin to ground turns off the DLL inside the device.
Input-
Reference
Power Supply Power Supply Inputs to the Core of the Device.
Ground Ground for the Device.
Power Supply Power Supply Inputs for the Outputs of the Device.
input clock (K
istics” on page 23.
data bus impedance. CQ, CQ, and Q
resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to
V
, which enables the minimum impedance mode. This pin cannot be connected directly to
DDQ
GND or left unconnected.
The timing in the DLL turned off operation is different from that listed in this data sheet. For
normal operation, this pin can be connected to a pull up through a 10 Kohm or less pull up
resistor. The device behaves in QDR-I mode when the DLL is turned off. In this mode, the device
can be operated at a frequency of up to 167 MHz with QDR-I timing.
Reference Volt age Input. S tatic input used to set the reference level for HSTL inputs, outputs,
and AC measurement points.
) of the QDR-II+. The timing for the echo clocks is shown in “Switching Character-
output impedance are set to 0.2 x RQ, where RQ is a
[x:0]
Document Number: 001-06365 Rev. *D Page 7 of 28
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CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Functional Overview
The CY7C1241V18, CY7C1256V18, CY7C1243V18, and
CY7C1245V18 are synchronous pipelined Burst SRAMs
equipped with a read and a write port. The read port is dedicated
to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and out
through the read port. These devices multiplex the address
inputs to minimize the number of address pins required. By
having separate read and write ports, the QDR-II+ completely
eliminates the need to “turn around” the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of four 8-bit data transfers in the case of
CY7C1241V18, four 9-bit data transfers in the case of
CY7C1256V18, four 18-bit data transfers in the case of
CY7C1243V18, and four 36-bit data transfers in the case of
CY7C1245V18, in two clock cycles.
Accesses for both ports are initiated on the Positive Input Clock
(K). All synchronous input and output timing refer to the ri sing
edge of the input clocks (K/K
All synchronous data inputs (D
registers controlled by the input clocks (K and K
synchronous data outputs (Q
registers controlled by the rising edge of the Input clocks (K and
K).
All synchronous control (RPS
through input registers controlled by the rising edge of the input
clocks (K/K
).
CY7C1243V18 is described in the following sections. The same
basic descriptions apply to CY7C1241V18, CY7C1256V18, and
CY7C1245V18.
Read Operations
The CY7C1243V18 is organized internally as 4 arrays of 512K x
18. Accesses are completed in a burst of four sequential 18-bit
data words. Read operations are initiated by asserting RPS
active at the rising edge of the Positive Input Clock (K). The
addresses presented to Address inputs are stored in the Read
address register. Following the next two K clock rising edges, the
corresponding lowest order 18-bit word of data is driven onto the
Q
using K as the output timing reference. On the subse-
[17:0]
quent rising edge of K
the Q
have been driven out onto Q
0.45 ns from the rising edge of the input clock (K or K
maintain the internal logic, each read access must be allowed to
complete. Each read access consists of four 18-bit data words
and takes two clock cycles to complete. Therefore, read
accesses to the device cannot be initiated on two consecutive K
clock rises. The internal logic of the device ignores the second
read request. Read accesses can be initiated on every other K
clock rise. Doing so pipelines the data flow such that data is
transferred out of the device on every rising edge of the input
clocks (K and K
When the read port is deselected, the CY7C1243V18 first
completes the pending Read transactions. Synchronous internal
circuitry automatically tri-states the outputs following the next
rising edge of the Positive Input Clock (K). This enables a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
. This process continues until all four 18-bit data words
[17:0]
).
).
) inputs pass through input
[x:0]
) outputs pass through output
[x:0]
, WPS, BWS
) inputs pass
[x:0]
). All
the next 18-bit data word is driven onto
. The requested data is valid
[17:0]
). To
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the Positive Input Clock (K). On the following K
clock rise, the data presented to D
the lower 18-bit Write Data register, provided BWS
asserted active. On the subsequent rising edge of the Negative
Input Clock (K), the information presented to D
into the Write Data register, provided BWS
active. This process continues for one more cycle until four 18-bit
is latched and stored into
[17:0]
[1:0]
[1:0]
is also stored
[17:0]
are both asserted
are both
words (a total of 72 bits) of data are stored in the SRAM. The 72
bits of data are then written into the memory array at the specified
location. Therefore, write accesses to the device cannot be
initiated on two consecutive K clock rises. The inte rnal logic of
the device ignores the second write request. Write accesses can
be initiated on every other rising edge of the Positive Input Clock
(K). Doing so pipelines the data flow such that 18 bits of data can
be transferred into the device on every rising edge of the input
clocks (K and K
).
When deselected, the write port ignores all inputs after the
pending write operations have been completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1243V18. A
Write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS
, which are sampled with each set of 18-bit data words.
1
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and written
into the device. Deasserting the Byte Write Select input during
the data portion of a write allows the data stored in the device for
that byte to remain unaltered. This feature can be used to
simplify read/modify/write operations to a Byte Write operation.
Concurrent Transactions
The read and write ports on the CY7C1243V18 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, you can read
or write to any location, regardless of the transaction on the other
port. If the ports access the same location when a read follows a
write in successive clock cycles, the SRAM delivers the most
recent information associated with the specified address
location. This includes forwarding data from a write cycle that
was initiated on the previous K clock rise.
Read accesses and write access must be scheduled such that
one transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on the
previous state of the SRAM. If both ports were deselected, the
read port takes priority. If a read was initiated on the previous
cycle, the write port assumes priority (because read operations
cannot be initiated on consecutive cycles). If a write was initiated
on the previous cycle, the Read port assumes priority (because
write operations cannot be initiated on consecutive cycles).
Therefore, asserting both port selects active from a deselected
state results in alternating read/write operations being initiated,
with the first access being a read.
Document Number: 001-06365 Rev. *D Page 8 of 28
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CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Depth Expansion
The CY7C1243V18 has a Port Select input for each port. This
enables easy depth expansion. Both Port Selects are sampled
on the rising edge of the Positive Input Clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed before the device is deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V
driver impedance. The value of RQ must be 5X the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
to enable the SRAM to adjust its output
SS
, with V
=1.5V. The
DDQ
Echo Clocks
Echo clocks are provided on the QDR-II+ to simplify data capture
on high speed systems. Two echo clocks are generated by the
QDR-II+. CQ is referenced with respect to K and CQ is referenced with respect to K
synchronized to the input clock of the QDR-II+. The timing f or the
echo clocks is shown in “Switching Characteristics” on page 23.
. These are free running clocks and are
Valid Data Indicator (QVLD)
QVLD is provided on the QDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the QDR-II+ device
along with data output. This signal is also edge-aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
Delay Lock Loop (DLL)
These chips use a DLL that is designed to function between 120
MHz and the specified maximum clock frequency. The DLL may
be disabled by applying ground to the DOFF pin. When the DLL
is turned off, the device behaves in QDR-I mode (with 1.0 cycle
latency and a longer access time). For more information, refer to
the application note, DLL Considerations in
QDRII/DDRII/QDRII+/DDRII+. The DLL can also be reset by
slowing or stopping the input clocks K and K
ns. However, it is not necessary for the DLL to be reset to lock to
the desired frequency. During power up, when the DOFF
HIGH, the DLL is locked after 2048 cycles of stable clock.
for a minimum of 30
is tied
Document Number: 001-06365 Rev. *D Page 9 of 28
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CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Application Example
BUS MASTER
(CPU or ASIC)
DATA IN
DATA OUT
Address
Source K
Source K
Vt
Vt
Vt
R
R
CLKIN/CLKIN
D
A
K
SRAM #4
RQ = 250ohms
ZQ
CQ/CQ
Q
K
RPS
WPS
BWS
D
A
K
SRAM #1
RQ = 250ohms
ZQ
CQ/CQ
Q
K
RPS
WPS
BWS
RPS
WPS
BWS
R = 50ohms, Vt = V /2
DDQ
R
Notes
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
↑ represents rising edge.
3. Device powers up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.
5. “t” represents the cycle at which a Read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the
“t” clock cycle.
6. Data inputs are registered at K and K
rising edges. Data outputs are delivered on K and K rising edges.
7. It is recommended that K = K
= HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operat ions on consecutive K clock rises is not permitted. The de vice igno res
the second Read or Write request.
Figure 1 shows the use of 4 QDR-II+ SRAMs in an application.
Figure 1. Application Example
Truth Table
[2, 3, 4, 5, 6, 7]
The truth table for the CY7C1241V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 fo llows.
Operation K RPS WPS DQ DQ DQ DQ
Write Cycle:
L-H H
[8]L[9]
D(A) at K(t + 1) ↑ D(A + 1) at K(t +1) ↑ D(A + 2) at K(t + 2) ↑ D(A + 3) at K(t + 2) ↑
Load address on the
rising edge of K; input
write data on two
consecutive K and K
rising edges.
Read Cycle:
L-H L
[9]
X Q(A) at K(t + 2) ↑ Q(A + 1) at K(t + 2) ↑ Q(A + 2) at K(t + 3) ↑ Q(A + 3) at K(t + 3) ↑
(2.0 cycle Latency)
Load address on the
rising edge of K; wait
two cycle; read data
on two consecutive K
and K
rising edges.
NOP: No Operation L-H H H D = X
Q = High-Z
Standby: Clock
Stopped X X Previous State Previous State Previous State Previous State
D = X
Q = High-Z
D = X
Q = High-Z
Stopped
D = X
Q = High-Z
Document Number: 001-06365 Rev. *D Page 10 of 28
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CY7C1243V18, CY7C1245V18
Write Cycle Descriptions
Note
10.Assumes a write cycle was initiated per the Write Cycle Description Table. NWS
0
, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered in different portions of
a write cycle, as long as the setup and hold requirements are met.
The write cycle description table for CY7C1241V18 and CY7C1243V18 follows.
[2, 10]
BWS0/
NWS
0
BWS1/
NWS
K
1
K
Comments
L L L–H – During the data portion of a write sequence:
CY7C1241V18 − both nibbles (D
CY7C1243V18 − both bytes (D
) are written into the device.
[7:0]
) are written into the device.
[17:0]
L L – L-H During the data portion of a write sequence:
CY7C1241V18 − both nibbles (D
CY7C1243V18 − both bytes (D
) are written into the device.
[7:0]
) are written into the device.
[17:0]
L H L–H – During the data portion of a write sequence:
CY7C1241V18 − only the lower nibble (D
CY7C1243V18 − only the lower byte (D
) is written into the device, D
[3:0]
) is written into the device, D
[8:0]
L H – L–H During the data portion of a write sequence:
CY7C1241V18 − only the lower nibble (D
CY7C1243V18 − only the lower byte (D
) is written into the device, D
[3:0]
) is written into the device, D
[8:0]
H L L–H – During the data portion of a write sequence:
CY7C1241V18 − only the upper nibble (D
CY7C1243V18 − only the upper byte (D
) is written into the device, D
[7:4]
) is written into the device, D
[17:9]
H L – L–H During the data portion of a write sequence:
CY7C1241V18 − only the upper nibble (D
CY7C1243V18 − only the upper byte (D
) is written into the device, D
[7:4]
) is written into the device, D
[17:9]
H H L–H – No data is written into the devices during this portion of a write operation.
H H – L–H No data is written into the devices during this portion of a write operation.
remains unaltered.
[7:4]
remains unaltered.
[17:9]
remains unaltered.
[7:4]
remains unaltered.
[17:9]
remains unaltered.
[3:0]
remains unaltered.
[8:0]
remains unaltered.
[3:0]
remains unaltered.
[8:0]
Write Cycle Descriptions
The write cycle description table for CY7C1256V18 follows.
BWS
L L–H – During the data portion of a write sequence, the single byte (D
L – L–H During the data portion of a write sequence, the single byte (D
K K Comments
0
[2, 10]
[8:0]
[8:0]
H L–H – No data is written into the device during this portion of a write operation.
H – L–H No data is written into the device during this portion of a write operation.
) is written into the device.
) is written into the device.
Document Number: 001-06365 Rev. *D Page 11 of 28
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CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
Write Cycle Descriptions
The write cycle description table for CY7C1245V18 follows.
BWS0BWS1BWS2BWS3K K Comments
LLLLL–H–During the data portion of a write sequence, all four bytes (D
into the device.
LLLL–L–HDuring the data portion of a write sequence, all four bytes (D
into the device.
L H H H L–H – During the data portion of a write sequence, only the lower byte (D
written into the device. D
L H H H – L–H During the data portion of a write sequence, only the lower byte (D
written into the device. D
H L H H L–H – During the data portion of a write sequence, only the byte (D
into the device. D
H L H H – L–H During the data portion of a write sequence, only the byte (D
into the device. D
H H L H L–H – During the data portion of a write sequence, only the byte (D
into the device. D
H H L H – L–H During the data portion of a write sequence, only the byte (D
into the device. D
H H H L L–H – During the data portion of a write sequence, only the byte (D
into the device. D
H H H L – L–H During the data portion of a write sequence, only the byte (D
into the device. D
HHHHL–H–No data is written into the device during this portion of a write operation.
HHHH–L–HNo data is written into the device during this portion of a write operation.
[2, 10]
remains unaltered.
[35:9]
remains unaltered.
[35:9]
and D
[8:0]
[8:0]
[17:0]
[17:0]
[26:0]
[26:0]
[35:18]
and D
[35:18]
and D
[35:27]
and D
[35:27]
remains unaltered.
remains unaltered.
remain unaltered.
remain unaltered.
remain unaltered.
remain unaltered.
[35:0]
[35:0]
[17:9]
[17:9]
[26:18]
[26:18]
[35:27]
[35:27]
) are written
) are written
) is
[8:0]
) is
[8:0]
) is written
) is written
) is written
) is written
) is written
) is written
Document Number: 001-06365 Rev. *D Page 12 of 28
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CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA p ackage. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8V IO logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (V
prevent device clocking. TDI and TMS are internally pulled up
and may be unconnected. They may alternatively be connected
to V
through a pull up resistor. TDO must be left unconnected.
DD
Upon power up, the device comes up in a reset state which does
not interfere with the operation of the device.
Test Access Port – Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this pin unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the i nstructio n that
is loaded into the TAP instruction register. For in formation on
loading the instruction register, see the “TAP Controller State
Diagram” on page 15. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. Whether the output is active depends upon the current
state of the TAP state machine (see “Instruction Codes” on
page 18). The output changes on the falling edge of TCK. TDO
is connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
scan data into and out of the SRAM test circuitry. Only one
register can be selected at a time through the instruction
registers. Data is serially loaded into the TDI pin on the rising
edge of TCK. Data is output on the TDO pin on the falling edge
of TCK.
SS
) to
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins as shown in “TAP Controller Block Diagram” on
page 16. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture IR state, the two least
significant bits are loaded with a binary ‘01’ pattern to enable fault
isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This shifts data through the SRAM with minimal
delay. The bypass register is set LOW (V
instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are also
included in the scan register to reserve pins for higher de nsity
devices.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
“Boundary Scan Order” on page 19 shows the order in which the
bits are connected. Each bit corresponds to one of the bumps on
the SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in “Identification Register Definitions” on
page 18.
) when the BYPASS
SS
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in “Instruction
Codes” on page 18. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
Instructions are loaded into the TAP controller during the Shif t-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI a nd TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
Document Number: 001-06365 Rev. *D Page 13 of 28
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CY7C1243V18, CY7C1245V18
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register upon
power up or whenever the TAP controller is in a Test-Logic-Reset
state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High-Z state until the next command is issued during the
Update-IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.
Be aware that the TAP controller clock can only operate at a
frequency up to 20 MHz, although the SRAM clock operates
more than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output may undergo a transition.
The TAP may then try to capture a signal while in transition
(metastable state). This does not harm the device, but there is
no guarantee as to the value that is captured. Repeatable results
may not be possible.
To guarantee that the boundary sc an register captures the correct value of a signal, the SRAM signal must be stabilized long
enough to meet the TAP controller's capture setup plus hold
times (t
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
and tCH). The SRAM clock input might not be captured
CS
captured in the boundary scan register.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required — that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-06365 Rev. *D Page 14 of 28
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CY7C1243V18, CY7C1245V18
TAP Controller State Diagram
TEST-LOGIC
RESET
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
SELECT
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
1
0
1
1
0
1
0
1
0
0
0
1
1
1
0
1
0
1
0
0
0
1
0
1
1
0
1
0
0
1
1
0
Note
11.The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
The state diagram for the CY7C1241V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 follows.
[11]
Document Number: 001-06365 Rev. *D Page 15 of 28
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CY7C1243V18, CY7C1245V18
TAP Controller Block Diagram
0
012..
29
3031
Boundary Scan Register
Identification Register
012..
.
.108
012
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TCK
TMS
Notes
12.These characteristics apply to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in “Electrical Characteristics” on page 21.
13.Overshoot: V
IH
(AC) < V
DDQ
+ 0.3V (pulse width less than t
CYC
/2). Undershoot: VIL(AC) > − 0.3V (pulse width less than t
CYC
/2).
14.All voltage refers to Ground.
TAP Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions Min Max Unit
V
V
V
V
V
V
I
OH1
OH2
OL1
OL2
IH
IL
X
Output HIGH Voltage I
Output HIGH Voltage I
Output LOW Voltage IOL = 2.0 mA 0.4 V
Output LOW Voltage IOL = 100 μA0.2V
Input HIGH Voltage 0.65VDDV
Input LOW Voltage –0.3 0.35V
Input and Output Load Current GND ≤ VI ≤ V
[12, 13, 14]
= −2.0 mA 1.4 V
OH
= −100 μA1.6 V
OH
+ 0.3 V
DD
DD
DD
–5 5 μA
V
Document Number: 001-06365 Rev. *D Page 16 of 28
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TAP AC Switching Characteristics
t
TL
t
TH
(a)
TDO
C
L
= 20 pF
Z
0
= 50Ω
GND
0.9V
50Ω
1.8V
0V
ALL INPUT PULSES
0.9V
Test Clock
Test Mode Select
TCK
TMS
Test Data In
TDI
Test Data Out
t
TCYC
t
TMSH
t
TMSS
t
TDIS
t
TDIH
t
TDOV
t
TDOX
TDO
Notes
15.t
CS
and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
16.Test conditions are specified using the load in TAP AC test conditions. t
R/tF
= 1 ns.
Over the Operating Range
Parameter Description Min Max Unit
t
TCYC
t
TF
t
TH
t
TL
TCK Clock Cycle Time 50 ns
TCK Clock Frequency 20 MHz
TCK Clock HIGH 20 ns
TCK Clock LOW 20 ns
Setup Times
t
TMSS
t
TDIS
t
CS
TMS Setup to TCK Clock Rise 5 ns
TDI Setup to TCK Clock Rise 5 ns
Capture Setup to TCK Rise 5 ns
Hold Times
t
TMSH
t
TDIH
t
CH
TMS Hold after TCK Clock Rise 5 ns
TDI Hold after Clock Rise 5 ns
Capture Hold after Clock Rise 5 ns
Output Times
t
TDOV
t
TDOX
TCK Clock LOW to TDO Valid 10 ns
TCK Clock LOW to TDO Invalid 0 ns
[15, 16]
TAP Timing and Test Conditions
[16]
Document Number: 001-06365 Rev. *D Page 17 of 28
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Identification Register Definitions
Instruction
Field
Revision
Number (31:29)
Cypress Device
ID (28:12)
Cypress JEDEC
ID (11:1)
ID Register
Presence (0)
CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18
000 000 000 000 Version number.
11 010010101000111 11010010101001111 11010010101010111 11010010101100111 Defines the type
00000110100 00000110100 00000110100 000 00110100 E nables unique
1111Indicates the
Value
Description
of SRAM.
identification of
SRAM vendor.
presence of an
ID register.
Scan Register Sizes
Register Name Bit Size
Instruction 3
Bypass 1
ID 32
Boundary Scan 109
Instruction Codes
Instruction Code Description
EXTEST 000 Captures the input/output ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between
SAMPLE Z 010 Captures the input/output contents. Places the boundary scan register between
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the input/output ring contents. Places the boundary scan register
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 1 1 1 Places the bypass register between TDI and TDO. This operation does not affect
TDI and TDO. This operation does not affect SRAM operation.
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
between TDI and TDO. Does not affect the SRAM operation.
SRAM operation.
Document Number: 001-06365 Rev. *D Page 18 of 28
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Boundary Scan Order
Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID
0 6R 28 10G 56 6A 84 1J
16P299G575B852J
2 6N 30 11F 58 5A 86 3K
3 7P 31 11G 59 4A 87 3J
47N329F605C882K
5 7R 33 10F 61 4B 89 1K
6 8R 34 11E 62 3A 90 2L
7 8P 35 10E 63 2A 91 3L
8 9R 36 10D 64 1A 92 1M
9 11P 37 9E 65 2B 93 1L
10 10P 38 10C 66 3B 94 3N
11 10N 39 11D 67 1C 95 3M
12 9P 40 9C 68 1B 96 1N
13 10M 41 9D 69 3D 97 2M
14 11N 42 11B 70 3C 98 3P
15 9M 43 11C 71 1D 99 2N
16 9N 44 9B 72 2C 100 2P
17 11L 45 10B 73 3E 101 1P
18 11M 46 11A 74 2D 102 3R
19 9L 47 10A 75 2E 103 4R
20 10L 48 9A 76 1E 104 4P
21 11K 49 8B 77 2F 105 5P
22 10K 50 7C 78 3F 106 5N
23 9J 51 6C 79 1G 107 5R
24 9K 52 8A 80 1F 108 Internal
25 10J 53 7A 81 3G
26 11J 54 7B 82 2G
27 11H 55 6B 83 1H
Document Number: 001-06365 Rev. *D Page 19 of 28
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Power Up Sequence in QDR-II+ SRAM
K
K
Fix HIGH (tie to V
DDQ
)
VDD/V
DDQ
DOFF
Clock Start (Clock Starts after VDD/V
DDQ
is Stable)
Unstable Clock > 2048 Stable Clock
Start Normal
Operation
~
~
VDD/V
DDQ
Stable (< + 0.1V DC per 50 ns)
QDR-II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations. During
power up, when the DOFF is tied HIGH, the DLL is locked after
2048 cycles of stable clock.
Power Up Sequence
■ Apply power with DOFF tied HIGH (All other inputs can be
HIGH or LOW)
❐ Apply V
❐ Apply V
■ Provide stable power and clock (K, K) for 2048 cycles to lock
the DLL.
before V
DD
before V
DDQ
DDQ
or at the same time as V
REF
REF
Power Up Waveforms
Figure 2. Power Up Waveforms
DLL Constraints
■ DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as t
■ The DLL functions at frequencies down to 120 MHz.
■ If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. T o avoid this, provide 2048 cycles stable clock
to relock to the clock frequency you want.
KC Var
.
Document Number: 001-06365 Rev. *D Page 20 of 28
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Maximum Ratings
Notes
17.Power up: Assumes a linear ramp from 0V to V
DD
(min) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD.
18.Outputs are impedance controlled. IOH = −(V
DDQ
/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ωs.
19.Outputs are impedance controlled. I
OL
= (V
DDQ
/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ωs.
20.V
REF
(min) = 0.68V or 0.46V
DDQ
, whichever is larger; V
REF
(max) = 0.95V or 0.54V
DDQ
, whichever is smaller.
21.The operation current is calculated with 50% read cycle and 50% write cycle.
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested .
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Powe r Applied.. –55°C to +125°C
Supply Voltage on VDD Relative to GND........–0.5V to +2.9V
Supply Voltage on V
DC Applied to Outputs in High-Z ........–0.5V to V
DC Input Voltage
Electrical Characteristics
Over the Operating Range
Relative to GND..... –0.5V to + V
DDQ
[13]
...............................–0.5V to VDD + 0.3V
[14]
DDQ
DD
+ 0.3V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V
Latch Up Current.................................................... >200 mA
Operating Range
Range
Temperature (TA) V
Com’l 0°C to +70°C 1.8 ± 0.1V 1.4V to V
Ind’l –40°C to +85°C
Ambient
DD
[17]
V
DDQ
DC Electrical Characteristics
Parameter Description Test Conditions Min Typ Max Unit
V
DD
V
DDQ
V
OH
V
OL
V
OH(LOW)
V
OL(LOW)
V
IH
V
IL
I
X
I
OZ
V
REF
[21]
I
DD
I
SB1
Power Supply Voltage 1.7 1.8 1.9 V
IO Supply Voltage 1.4 1.5 V
Output HIGH Voltage Note 18 V
Output LOW Voltage Note 19 V
Output HIGH Voltage I
= −0.1 mA, Nominal Impedance V
OH
Output LOW Voltage IOL = 0.1 mA, Nominal Impedance V
Input HIGH Voltage V
/2 – 0.12 V
DDQ
/2 – 0.12 V
DDQ
– 0.2 V
DDQ
SS
+ 0.1 V
REF
Input LOW Voltage –0.15 V
Input Leakage Current GND ≤ VI ≤ V
Output Leakage Current GND ≤ VI ≤ V
Input Reference Voltage
VDD Operating Supply V
[20]
Typical Value = 0.75V 0.68 0.75 0.95 V
= Max., I
DD
MAX
= 1/t
f = f
DDQ
Output Disabled −22μA
DDQ,
OUT
CYC
= 0mA,
300 MHz 1040 mA
333 MHz 1120 mA
−22μA
DD
/2 + 0.12 V
DDQ
/2 + 0.12 V
DDQ
DDQ
0.2 V
+ 0.15 V
DDQ
– 0.1 V
REF
375 MHz 1240 mA
Automatic Power down
Current
Max. VDD, Both Ports
Deselected, V
V
≤ VIL, f = f
IN
Inputs Static
≥ VIH or
IN
= 1/t
MAX
300 MHz 280 mA
333 MHz 300 mA
CYC,
375 MHz 310 mA
[17]
DD
V
V
AC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions Min Typ Max Unit
V
IH
V
IL
Document Number: 001-06365 Rev. *D Page 21 of 28
Input HIGH Voltage V
Input LOW Voltage –0.24 – V
[13]
+ 0.2 – V
REF
+ 0.24 V
DDQ
– 0.2 V
REF
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CY7C1243V18, CY7C1245V18
Capacitance
1.25V
0.25V
R = 50Ω
5pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
Device
R
L
= 50Ω
Z
0
= 50Ω
V
REF
= 0.75V
V
REF
= 0.75V
[22]
0.75V
Under
Test
0.75V
Device
Under
Test
OUTPUT
0.75V
V
REF
V
REF
OUTPUT
ZQ
ZQ
(a)
Slew Rate = 2 V/ns
RQ =
250
Ω
(b)
RQ =
250
Ω
Note
22.Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75V, V
REF
= 0.75V, RQ = 250Ω, V
DDQ
= 1.5V , inp ut
pulse levels of 0.25V to 1.25V, and output loading of the specified I
OL/IOH
and load capacitance shown in (a) of AC Test Loads and Waveforms.
Tested initially and after any design or process change that may affect these parameters.
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
V
= 1.8V
C
CLK
C
O
Clock Input Capacitance 4 pF
Output Capacitance 5 pF
V
DD
DDQ
= 1.5V
5pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter Description Test Conditions
Θ
Θ
Thermal Resistance
JA
(Junction to Ambient)
Thermal Resistance
JC
(Junction to Case)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
165 FBGA
Package
16.25 °C/W
2.91 °C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
Unit
Document Number: 001-06365 Rev. *D Page 22 of 28
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Switching Characteristics
Notes
23.When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the i nput t imings of the frequen cy range in which i t is
being operated and outputs data with the output timing of that frequency range.
24.This part has an internal voltage regulator; t
POWER
is the time that the power must be supplied above V
DD
minimum initially before a read or write operation can
be initiated.
25.These parameters are extrapolated from the input timing parameters (t
KHKH
– 250 ps, where 250 ps is the internal jitter . An input jitter of 200 p s (t
KC Var
) is already
included in the t
KHKH
). These parameters are only guaranteed by design and are not tested in production.
26.t
CHZ
, t
CLZ
are specified with a load capacitance of 5 pF as in part (b) of “AC Test Loads and Waveforms” on page22. Transition is measured ±100 mV from
steady-state voltage.
27.At any voltage and temperature t
CHZ
is less than t
CLZ
and t
CHZ
less than tCO.
28.t
QVLD
spec is applicable for both rising and falling edges of QVLD signal.
29.Hold to >V
IH
or <VIL.
Over the Operating Range
Cypress
Parameter
t
POWER
t
CYC
t
KH
t
KL
t
KHKH
Consortium
Parameter
t
KHKH
t
KHKL
t
KLKH
t
KHKH
Set-up Times
t
SA
t
SC
t
SCDDRtIVKH
t
SD
t
AVKH
t
IVKH
t
DVKH
Hold Times
t
HA
t
HC
t
HCDDRtKHIX
t
HD
t
KHAX
t
KHIX
t
KHDX
Output Times
t
CO
t
DOH
t
CCQO
t
CQOH
t
CQD
t
CQDOHtCQHQX
t
CQH
t
CQHCQHtCQHCQH
t
CHZ
t
CLZ
t
QVLD
t
CHQV
t
CHQX
t
CHCQV
t
CHCQX
t
CQHQV
t
CQHCQL
t
CHQZ
t
CHQX1
t
CQHQVLD
DLL Timing
t
KC Var
t
KC lock
t
KC ResettKC Reset
t
KC Var
t
KC lock
[22, 23]
VDD(Typical) to the First Access
K Clock Cycle Time 2.66 8.4 3.0 8.4 3.3 8.4 ns
Input Clock (K/K) HIGH 0.4 – 0.4 – 0.4 – t
Input Clock (K/K) LOW 0.4–0.4–0.4–t
K Clock Rise to K Clock Rise (rising edge to rising edge) 1.13 – 1.28 – 1.40 – ns
Address Set-up to K Clock Rise 0.4 – 0.4 – 0.4 – ns
Control Set-up to K Clock Rise (RPS, WPS) 0.4–0.4–0.4– ns
Double Data Rate Control Set-up to Clock (K, K) Rise
, BWS
(BWS
0
D
Set-up to Clock (K/K) Rise 0.28 – 0.28 – 0.28 – ns
[X:0]
Address Hold after K Clock Rise 0.4 – 0.4 – 0.4 – ns
Control Hold after K Clock Rise (RPS, WPS) 0.4–0.4–0.4– ns
Double Data Rate Control Hold after Clock (K/K) Rise
(BWS
, BWS
0
D
Hold after Clock (K/K) Rise 0.28 – 0.28 – 0.28 – ns
[X:0]
K/K Clock Rise to Data Valid – 0.45 – 0.45 – 0.45 ns
Data Output Hold after Output K/K Clock Rise
(Active to Active)
K/K Clock Rise to Echo Clock Valid – 0.45 – 0.45 – 0.45 ns
Echo Clock Hold after K/K Clock Rise –0.45 – –0.45 – –0.45 – ns
Echo Clock High to Data Valid 0.2 0.2 0.2 ns
Echo Clock High to Data Invalid –0.2 – –0.2 – –0.2 – ns
Output Clock (CQ/CQ) HIGH
CQ Clock Rise to CQ Clock Rise
(rising edge to rising edge)
Clock (K/K) Rise to High-Z (Active to High-Z)
Clock (K/K) Rise to Low-Z
Echo Clock High to QVLD Valid
Clock Phase Jitter – 0.20 – 0.20 – 0.20 ns
DLL Lock Time (K) 2048 – 2048 – 2048 – Cycles
K Static to DLL Reset
Description
BWS2, BWS3)
1,
BWS2, BWS3)
1,
[29]
[25]
[26, 27]
[24]
[28]
[25]
[26, 27]
375 MHz 333 MHz 300 MHz
Min Max Min Max Min Max
Unit
1–1–1–ms
CYC
CYC
0.28 – 0.28 – 0.28 – ns
0.28 – 0.28 – 0.28 – ns
–0.45 – –0.45 – –0.45 – ns
0.88 – 1.03 – 1.15 – ns
0.88 – 1.03 – 1.15 – ns
–0.45–0.45–0.45ns
–0.45 – –0.45 – –0.45 – ns
–0.20 0.20 –0.20 0.20 –0.20 0.20 ns
30–30–30– ns
Document Number: 001-06365 Rev. *D Page 23 of 28
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Switching Waveforms
Notes
30.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.
31.Outputs are disabled (High-Z) one clock cycle after a NOP.
32.In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole
diagram.
Figure 4. Read/Write/Deselect Sequence waveform for 2.0 Cycle Read Latency
[30, 31, 32]
RPS
WPS
QVLD
K
K
A
D
NOP
1
t
KHtKL
WRITE READ
WRITE
NOPREAD
23 4 5 6
t
SC
t
SA
A0
t
t
HC
HA
t
CYC
A1
t
KHKH
t
QVLD
t
t
SC HC
A2
t
HD
t
SD
t
t
CLZ
CO
A3
t
SD
D11D10
D12 D13 D30 D31
t
DOH
t
CQD
t
HD
7
D32 D33
t
CQDOH
8
t
QVLD
t
CHZ
Q
CQ
CQ
(Read Latency = 2.0 Cycles)
t
CQH
t
CQHCQH
t
CQOH
Q00
t
CQOH
Q01
t
CCQO
Q02
t
CCQO
Q03
Q22
Q20
Q21
DON’T CARE UNDEFINED
Q23
Document Number: 001-06365 Rev. *D Page 24 of 28
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Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz) Ordering Code
375 CY7C1241V18-375BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial
CY7C1256V18-375BZC
CY7C1243V18-375BZC
CY7C1245V18-375BZC
CY7C1241V18-375BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1256V18-375BZXC
CY7C1243V18-375BZXC
CY7C1245V18-375BZXC
CY7C1241V18-375BZI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial
CY7C1256V18-375BZI
CY7C1243V18-375BZI
CY7C1245V18-375BZI
CY7C1241V18-375BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1256V18-375BZXI
CY7C1243V18-375BZXI
CY7C1245V18-375BZXI
333 CY7C1241V18-333BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial
CY7C1256V18-333BZC
CY7C1243V18-333BZC
CY7C1245V18-333BZC
CY7C1241V18-333BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1256V18-333BZXC
CY7C1243V18-333BZXC
CY7C1245V18-333BZXC
CY7C1241V18-333BZI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial
CY7C1256V18-333BZI
CY7C1243V18-333BZI
CY7C1245V18-333BZI
CY7C1241V18-333BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1256V18-333BZXI
CY7C1243V18-333BZXI
CY7C1245V18-333BZXI
Package
Diagram Package Type
Operating
Range
Document Number: 001-06365 Rev. *D Page 25 of 28
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Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit
www.cypress.com for actual products offered.
Speed
(MHz) Ordering Code
300 CY7C1241V18-300BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial
CY7C1256V18-300BZC
CY7C1243V18-300BZC
CY7C1245V18-300BZC
CY7C1241V18-300BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1256V18-300BZXC
CY7C1243V18-300BZXC
CY7C1245V18-300BZXC
CY7C1241V18-300BZI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial
CY7C1256V18-300BZI
CY7C1243V18-300BZI
CY7C1245V18-300BZI
CY7C1241V18-300BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1256V18-300BZXI
CY7C1243V18-300BZXI
CY7C1245V18-300BZXI
Package
Diagram Package Type
Operating
Range
Document Number: 001-06365 Rev. *D Page 26 of 28
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CY7C1243V18, CY7C1245V18
Package Diagram
!
0).#/2.%2
¼
¼
8
-#!"
-#
"
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8
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3%!4).'0,!.%
¼
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"/44/-6)%7
"
#
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%
&
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*
+
,
-
.
0
2
0
2
+
-
.
,
*
(
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%
$
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Figure 5. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195
Document Number: 001-06365 Rev. *D Page 27 of 28
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Document History Page
Document Title: CY7C1241V18/CY7C1256V18/CY7C1243V18/CY7C1245V18, 36-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.0 Cycle Read Latency)
Document Number: 001-06365
REV. ECN NO.
ISSUE
DATE
** 425689 See ECN NXR New Data Sheet
*A 461639 See ECN NXR Revised the MPNs from
*B 497628 See ECN NXR Chang ed the V
*C 1072841 See ECN VKN/KKVTMP Converted from preliminary to final
*D 2198506 See ECN VKN/AESA Added footnote# 21related to I
ORIG. OF
CHANGE
DESCRIPTION OF CHANGE
CY7C1256AV18 to CY7C1256V18
CY7C1243AV18 to CY7C1243V18
CY7C1245AV18 to CY7C1245V18
Changed t
t
, t
TMSH
ns in TAP AC Switching Characteristics table
TDIH
and t
TH
, t
from 40 ns to 20 ns, changed t
TL
from 10 ns to 5 ns and changed t
CH
, t
TMSS
from 20 ns to 10
TDOV
TDIS
, tCS,
Modified Power-Up waveform
operating voltage to 1.4V to VDD in the Features
section, in Operating Range table and in the DC Electrical Characteristics
DDQ
table
Added foot note in page# 1
Changed the Maximum rating of Ambient Temp erature with Power
Applied from –10°C to +85°C to –55°C to +125°C
Changed V
Characteristics table and in the note below the table
(Max.) spec from 0.85V to 0.95V in the DC Electrical
REF
Updated footnote #20 to specify Overshoot and Undershoot Spec
Updated Θ
Removed x9 part and its related information
JA
and Θ
JC
values
Updated footnote #25
Added x8 and x9 parts
Changed I
1120 mA for 333 MHz, 800 mA to 1040 mA for 300 MHz
values from 950 mA to 1240 mA for 375 MHz, 850 mA to
DD
Changed ISB values from 300 mA to 310 mA for 375 MHz, 275 mA to 300
mA for 333 MHz, 250 mA to 280 mA for 300 MHz
Changed t
Changed Θ
Updated Ordering Information table
max spec to 8.4 ns for all speed bins
CYC
value from 12.43 °C/W to 16.25 °C/W
JA
DD
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