Cypress CY7C1245V18, CY7C1256V18, CY7C1241V18, CY7C1243V18 User Manual

CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18

36-Mbit QDR™-II+ SRAM 4-Word Burst

Architecture (2.0 Cycle Read Latency)

Features

Note

1. The QDR consortium specification for V

DDQ

is 1.5V + 0.1V . The Cypress QDR devices exceed the QDR consort ium specification and are cap able of supporting

DDQ

= 1.4V to VDD.

Configurations

■ Separate independent read and write data ports ❐ Supports concurrent transactions

■ 300 MHz to 375 MHz clock for high bandwidth

■ 4-Word Burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces on both read and write ports

(data transferred at 750 MHz) at 375 MHz

■ Read latency of 2.0 clock cycles

■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate Port Selects for depth expansion

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ Available in x8, x9, x18, and x36 configurations

■ Full data coherency providing most current data

■ Core V

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

= 1.8V ± 0.1V; IO V

= 1.4V to V

DDQ

[1]

With Read Cycle Latency of 2.0 cycles:

CY7C1241V18 – 4M x 8 CY7C1256V18 – 4M x 9 CY7C1243V18 – 2M x 18 CY7C1245V18 – 1M x 36

Functional Description

The CY7C1241V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 are 1.8V Synchronous Pipelined SRAMs, equipped with Quad Data Rate-II+ (QDR-II+) architecture. QDR-II+ architecture consists of two separate ports to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR-II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turn around” the data bus required with common IO devices. Each port can be accessed through a common address bus. Read and write addresses are latched on alterna te rising edges of the input (K) clock. Accesses to the QDR-II+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 8-bit words (CY7C1241V18), 9-bit words (CY7C1256V18), 18-bit words (CY7C1243V18), or 36-bit words (CY7C1245V18), that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K fying system design by eliminating bus “turn-arounds”.

Depth expansion is accomplished with Port Selects for each port. Port selects enable each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K registers controlled by the K or K conducted with on-chip synchronous self-timed write circuitry.

), memory bandwidth is maximized while simpli-

input clocks. All data outputs pass through output

input clocks. Writes are

Selection Guide

Maximum Operating Frequency 375 333 300 MHz Maximum Operating Current 1240 1120 1040 mA

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-06365 Rev. *D Revised March 12, 2008

Description 375 MHz 333 MHz 300 MHz Unit

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CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18

Logic Block Diagram (CY7C1241V18)

1M x 8 Array

CLK

(19:0)

Gen.

Control

Logic

Address Register

[7:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

[7:0]

Control

Logic

Address Register

Reg.

NWS

[1:0]

REF

Write Add. Decode

Write

Reg

(19:0)

1M x 8 Array

Write

Reg

Write

Reg

Write

Reg

DOFF

QVLD

1M x 9 Array

CLK

(19:0)

Gen.

Control

Logic

Address

[8:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

[8:0]

Control

Logic

Address

Reg.

BWS

[0]

REF

Write Add. Decode

Write

Reg

(19:0)

1M x 9 Array

Write

Reg

Write

Reg

Write

Reg

DOFF

QVLD

Logic Block Diagram (CY7C1256V18)

Document Number: 001-06365 Rev. *D Page 2 of 28

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CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18

Logic Block Diagram (CY7C1243V18)

512K x 18 Array

CLK

(18:0)

Gen.

Control

Logic

Address

[17:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

[17:0]

Control

Logic

Address

Reg.

BWS

[1:0]

REF

Write Add. Decode

Write

Reg

(18:0)

512K x 18 Array

Write

Reg

Write

Reg

Write

Reg

DOFF

QVLD

256K x 36 Array

CLK

(17:0)

Gen.

Control

Logic

Address

[35:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

[35:0]

Control

Logic

Address

Reg.

144

BWS

[3:0]

REF

Write Add. Decode

Write

Reg

(17:0)

256K x 36 Array

Write

Reg

Write

Reg

Write

Reg

DOFF

QVLD

Logic Block Diagram (CY7C1245V18)

Document Number: 001-06365 Rev. *D Page 3 of 28

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CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18

Pin Configurations

CY7C1241V18 (4M x 8)

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

A B

C D

E F G H

J K L M N P

CQ NC

NC NC

DOFF

NC/72M A

NWS

KWPS

NC/144M

NC NC

TDO

TCK

A NC/288M K NWS

ANCA

NC V

Q4 NC

DDQ

NC NC

NC NC Q7

DDQ

Q5 V

DDQ

D4 V

NC V

REF

QVLD

91011

RPS

A NC NC Q3

NC NC D3 NC

REF

DDQ

NC NC

DDQ

D1V

DDQ

NC D0 NC

TDITMS

NC/144M

CY7C1256V18 (4M x 9)

1 A B C

D E F

J K L

N P

CQ NC NC NC

DOFF

NC/72M A NC K

WPS NC/144M

NC NC

TDO

TCK

A NC/288M K BWS

ANCA

NC V

Q5 NC

DDQ

NC NC

NC NC Q8

DDQ

Q6 V

DDQ

D5 V

NC V

REF

QVLD

91011

AARPS

NC Q4

NC NC D4 NC

REF

DDQ

NC NC

DDQ

D2V

DDQ

NC D1 NC

TDITMS

Document Number: 001-06365 Rev. *D Page 4 of 28

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CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18

Pin Configurations (continued)

CY7C1243V18 (2M x 18)

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

567

1 A B C D E

F G H

J K

L M

N P

CQ NC

NC NC

DOFF

NC/144M A

BWS

KWPS

NC/288M

Q9 D9

TDO

D13

TCK

D10

A NC K

BWS

ANCA

Q10 V

Q11 D12

DDQ

D14 Q14

D16 Q16 Q17

DDQ

Q13 V

DDQ

D11 V

NC V

Q12

REF

QVLD

Q15

D17

D15

91011

A NC/72M

RPS

A NC NC Q8

NC Q7 D8 NC

REF

DDQ

NC Q5

DDQ

D4V

DDQ

NC D2 NC

TDITMS

CY7C1245V18 (1M x 36)

456

A B C

D E F

G H

J K L M N P

Q27

D27 D28

D34

DOFF

Q33

NC/288M NC/72M

BWS

WPS BWS

Q18

D18

Q30

D31

D33

TDO

Q28

D29

D22

D32

Q34

Q31

TCK

D35

D19

BWS

ANCA

Q19 V

Q20 D21

DDQ

D23 Q23

D25 Q25 Q26

DDQ

Q22 V

DDQ

D20 V

Q29 V

Q21

D30

REF

QVLD

Q32

Q24

Q35

D26

D24

891011

NC/144M

RPS

A D17

Q17

D16 Q7 D8 Q16

D15

Q14

REF

Q11

DDQ

Q15

DDQ

D14 Q5

DDQ

D4V

DDQ

D12

Q12

DDQ

D11

D10 D2 Q10

TDITMS

D13

Q13

Document Number: 001-06365 Rev. *D Page 5 of 28

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CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18

Pin Definitions

Pin Name IO Pin Description

[x:0]

Input-

Synchronous

WPS Input-

Synchronous

NWS

BWS BWS

NWS

, BWS1,

, BWS

Synchronous

Input-

A Input-

Synchronous

[x:0]

Outputs-

Synchronous

RPS Input-

Synchronous

QVLD Valid output

indicator

K Input-

Clock

Input-

Clock

Data Input Signals. Sampled on the rising edge of K and K CY7C1241V18 − D CY7C1256V18 − D CY7C1243V18 − D CY7C1245V18 − D

[7:0] [8:0] [17:0] [35:0]

Write Port Select, Active LOW. Sampled on the rising edge of the K clock. When asserted active, a Write operation is initiated. Deasserting deselects the write port. Deselecting the write port causes D

to be ignored.

[x:0]

Nibble Write Select 0, 1, Active LOW (CY7C1241V18 Only). Sampled on the rising edge of the K and K clocks when write operations are active. Used to select which nibble is written into the device during the current portion of the write operations. NWS controls D

[7:4]

All the nibble Write Selects are sampled on the same edge as the data. The corresponding nibble of data is ignored by deselecting a nibble write se lect and is not written into the device.

Byte Write Select 0, 1, 2, and 3, Active LOW. Sampled on the rising edge of the K and K during write operations. Selects which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1256V18 − BWS CY7C1243V18 − BWS0 controls D CY7C1245V18 − BWS0 controls D controls D

[35:27].

controls D

[8:0]

and BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select ignores the corresponding byte of data and not written into the device.

Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These address inputs are multiplexed for both read and write operations. Internally, the device is organized as 4M x 8 (4 arrays each of 1M x 8) for CY7C1241V18, 4M x 9 (4 arrays each of 1M x 9) for CY7C1256V18, 2M x 18 (4 arrays each of 512K x 18) for CY7C1243V18 and 1M x 36 (4 arrays each of 256K x 36) for CY7C1245V18. Therefore, only 20 address inputs are needed to access the entire memory array of CY7C1241V18 and CY7C1256V18, 19 address inputs for CY7C1243V18, and 18 address inputs for CY7C1245V18. These inputs are ignored when the appropriate port is deselected.

Data Output Signals. These pins drive out the requested data during a read operation. Valid data is driven out on the rising edge of both the K and K the read port is deselected, Q CY7C1241V18 − Q CY7C1256V18 − Q CY7C1243V18 − Q CY7C1245V18 − Q

[7:0] [8:0] [17:0] [35:0]

are automatically tri-stated.

[x:0]

Read Port Select, Active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a read operation is initiated. Deasserting causes the read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the K clock. Each read access consists of a burst of four sequential transfers.

Valid Output Ind icator . The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ

Positive Input Clock Input. The rising edge of K captures synchronous inputs to the device and drives out data through Q rising edge of K.

when in single clock mode. All accesses are initiated on the

[x:0]

Negative Input Clock Input. K captures synchronous inputs being presented to the device and drives out data through Q

when in single clock mode.

[x:0]

clocks during valid write operations.

controls D

and NWS1

[3:0]

clocks

[17:9].

, BWS2 controls D

[17:9]

[26:18]

, and BWS3

clocks during read operations. When

Document Number: 001-06365 Rev. *D Page 6 of 28

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CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18

Pin Definitions (continued)

Pin Name IO Pin Description

CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the

input clock (K) of the QDR-II+. The timing for the echo clocks is shown in “Switching Character-

istics” on page 23.

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system

DOFF

TDO Output TDO for JTAG. TCK Input TCK Pin for JTAG. TDI Input TDI Pin for JTAG. TMS Input TMS Pin for JTAG. NC N/A Not Connected to the Die. Can be tied to any voltage level. NC/72M N/A Not Connected to the Die. Can be tied to any voltage level.

NC/144M N/A Not Connected to the Die. Can be tied to any voltage level. NC/288M N/A Not Connected to the Die. Can be tied to any voltage level.

REF

DDQ

Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the

Input DLL Turn Off, Active LOW. Connecting this pin to ground turns off the DLL inside the device.

Input-

Reference

Power Supply Power Supply Inputs to the Core of the Device.

Ground Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

input clock (K

istics” on page 23.

data bus impedance. CQ, CQ, and Q resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to V

, which enables the minimum impedance mode. This pin cannot be connected directly to

DDQ

GND or left unconnected.

The timing in the DLL turned off operation is different from that listed in this data sheet. For normal operation, this pin can be connected to a pull up through a 10 Kohm or less pull up resistor. The device behaves in QDR-I mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with QDR-I timing.

Reference Volt age Input. S tatic input used to set the reference level for HSTL inputs, outputs, and AC measurement points.

) of the QDR-II+. The timing for the echo clocks is shown in “Switching Character-

output impedance are set to 0.2 x RQ, where RQ is a

[x:0]

Document Number: 001-06365 Rev. *D Page 7 of 28

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CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18

Functional Overview

The CY7C1241V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 are synchronous pipelined Burst SRAMs equipped with a read and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and out through the read port. These devices multiplex the address inputs to minimize the number of address pins required. By having separate read and write ports, the QDR-II+ completely eliminates the need to “turn around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of four 8-bit data transfers in the case of CY7C1241V18, four 9-bit data transfers in the case of CY7C1256V18, four 18-bit data transfers in the case of CY7C1243V18, and four 36-bit data transfers in the case of CY7C1245V18, in two clock cycles.

Accesses for both ports are initiated on the Positive Input Clock (K). All synchronous input and output timing refer to the ri sing edge of the input clocks (K/K

All synchronous data inputs (D registers controlled by the input clocks (K and K synchronous data outputs (Q registers controlled by the rising edge of the Input clocks (K and K).

All synchronous control (RPS through input registers controlled by the rising edge of the input clocks (K/K

CY7C1243V18 is described in the following sections. The same basic descriptions apply to CY7C1241V18, CY7C1256V18, and CY7C1245V18.

Read Operations

The CY7C1243V18 is organized internally as 4 arrays of 512K x

18. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the Positive Input Clock (K). The addresses presented to Address inputs are stored in the Read address register. Following the next two K clock rising edges, the corresponding lowest order 18-bit word of data is driven onto the Q

using K as the output timing reference. On the subse-

[17:0]

quent rising edge of K the Q have been driven out onto Q

0.45 ns from the rising edge of the input clock (K or K maintain the internal logic, each read access must be allowed to complete. Each read access consists of four 18-bit data words and takes two clock cycles to complete. Therefore, read accesses to the device cannot be initiated on two consecutive K clock rises. The internal logic of the device ignores the second read request. Read accesses can be initiated on every other K clock rise. Doing so pipelines the data flow such that data is transferred out of the device on every rising edge of the input clocks (K and K

When the read port is deselected, the CY7C1243V18 first completes the pending Read transactions. Synchronous internal circuitry automatically tri-states the outputs following the next rising edge of the Positive Input Clock (K). This enables a seamless transition between devices without the insertion of wait states in a depth expanded memory.

. This process continues until all four 18-bit data words

[17:0]

) inputs pass through input

[x:0]

) outputs pass through output

[x:0]

, WPS, BWS

) inputs pass

[x:0]

). All

the next 18-bit data word is driven onto

. The requested data is valid

[17:0]

). To

Write Operations

Write operations are initiated by asserting WPS active at the rising edge of the Positive Input Clock (K). On the following K clock rise, the data presented to D the lower 18-bit Write Data register, provided BWS asserted active. On the subsequent rising edge of the Negative Input Clock (K), the information presented to D into the Write Data register, provided BWS active. This process continues for one more cycle until four 18-bit

is latched and stored into

[17:0]

[1:0]

is also stored

[17:0]

are both asserted

are both

words (a total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, write accesses to the device cannot be initiated on two consecutive K clock rises. The inte rnal logic of the device ignores the second write request. Write accesses can be initiated on every other rising edge of the Positive Input Clock (K). Doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K

When deselected, the write port ignores all inputs after the pending write operations have been completed.

Byte Write Operations

Byte Write operations are supported by the CY7C1243V18. A Write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS0 and BWS

, which are sampled with each set of 18-bit data words.

Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and written into the device. Deasserting the Byte Write Select input during the data portion of a write allows the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read/modify/write operations to a Byte Write operation.

Concurrent Transactions

The read and write ports on the CY7C1243V18 operate completely independently of one another. Since each port latches the address inputs on different clock edges, you can read or write to any location, regardless of the transaction on the other port. If the ports access the same location when a read follows a write in successive clock cycles, the SRAM delivers the most recent information associated with the specified address location. This includes forwarding data from a write cycle that was initiated on the previous K clock rise.

Read accesses and write access must be scheduled such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports were deselected, the read port takes priority. If a read was initiated on the previous cycle, the write port assumes priority (because read operations cannot be initiated on consecutive cycles). If a write was initiated on the previous cycle, the Read port assumes priority (because write operations cannot be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state results in alternating read/write operations being initiated, with the first access being a read.

Document Number: 001-06365 Rev. *D Page 8 of 28

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CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18

Depth Expansion

The CY7C1243V18 has a Port Select input for each port. This enables easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). Each port select input can deselect the specified port. Deselecting a port does not affect the other port. All pending transactions (read and write) are completed before the device is deselected.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature.

to enable the SRAM to adjust its output

, with V

=1.5V. The

DDQ

Echo Clocks

Echo clocks are provided on the QDR-II+ to simplify data capture on high speed systems. Two echo clocks are generated by the QDR-II+. CQ is referenced with respect to K and CQ is referenced with respect to K synchronized to the input clock of the QDR-II+. The timing f or the echo clocks is shown in “Switching Characteristics” on page 23.

. These are free running clocks and are

Valid Data Indicator (QVLD)

QVLD is provided on the QDR-II+ to simplify data capture on high speed systems. The QVLD is generated by the QDR-II+ device along with data output. This signal is also edge-aligned with the echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives.

Delay Lock Loop (DLL)

These chips use a DLL that is designed to function between 120 MHz and the specified maximum clock frequency. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in QDR-I mode (with 1.0 cycle latency and a longer access time). For more information, refer to the application note, DLL Considerations in QDRII/DDRII/QDRII+/DDRII+. The DLL can also be reset by slowing or stopping the input clocks K and K ns. However, it is not necessary for the DLL to be reset to lock to the desired frequency. During power up, when the DOFF HIGH, the DLL is locked after 2048 cycles of stable clock.

for a minimum of 30

is tied

Document Number: 001-06365 Rev. *D Page 9 of 28

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Cypress CY7C1245V18, CY7C1256V18, CY7C1241V18, CY7C1243V18 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Configurations

Functional Description

Selection Guide

Logic Block Diagram (CY7C1241V18)

Logic Block Diagram (CY7C1256V18)

Logic Block Diagram (CY7C1243V18)

Logic Block Diagram (CY7C1245V18)

Pin Configurations

Pin Definitions

Functional Overview

Read Operations

Write Operations

Byte Write Operations

Concurrent Transactions

Depth Expansion

Programmable Impedance

Echo Clocks

Valid Data Indicator (QVLD)

Delay Lock Loop (DLL)