Cypress CY7C1231H User Manual

A
B

CY7C1231H

2-Mbit (128K x 18) Flow-Through SRAM

with NoBL™ Architecture

Features

• Can support up to 133-MHz bus operations with ze ro
wait states

— Data is transferred on every clock

• Pin compatible and functionally equivalent to ZBT™
devices

• Internally self-timed output buffer control to eliminate
the need to use OE

• Registered inputs for flow-through operation

• Byte Write capability

• 128K x 18 common I/O architecture

• 3.3V core power supply

• 3.3V/2.5V I/O operation

• Fast clock-to-output times
— 6.5 ns (133-MHz device)

• Clock Enable (CEN

• Synchronous self-timed write

• Asynchronous Output Enable

• Offered in JEDEC-standard lead-free 100-pin TQFP
package

• Burst Capability—linear or interleaved burst order

• Low standby powe r

) pin to suspend operation

Functional Description

[1]

The CY7C1231H is a 3.3V/2.5V, 128K x 18 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1231H is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified b y
the Clock Enable (CEN

) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).

Write operations are controlled by the two Byte Write Select
(BW
conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE
asynchronous Output Enable (OE

) and a Write Enable (WE) input. All writes are

[A:B]

, CE2, CE3) and an

1

) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.

Logic Block Diagram

A0, A1, A

MODE

CLK
CEN

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

C

ADV/LD

BW
BW

WE

ZZ

CE
CE
CE

A

B

OE

CE

1
2
3

ADDRESS
REGISTER

ADV/LD

C

WRITE ADDRESS

REGISTER

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

READ LOGIC

SLEEP

CONTROL

A1

D1

A0

D0

BURST
LOGIC

A1'

Q1

A0'

Q0

S
E

N

INPUT

S

E
A

M

P

S

E

WRITE

DRIVERS

MEMORY

ARRAY

REGISTER

O
U

T
P

D

U

A

T

T
A

B
U

S

F

T

F

E

E

E

R

R

S

I
N
G

E

DQs
DQP
DQP

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-00207 Rev. *B Revised April 26, 2006

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CY7C1231H

Selection Guide

133 MHz Unit

Maximum Access Time 6.5 ns
Maximum Operating Current 225 mA
Maximum CMOS Standby Current 40 mA

Pin Configuration

100-pin TQFP Pinout

BYTE B

V

DDQ

V

DQ
DQ

V

V

DDQ

DQ
DQ

V

V
DQ
DQ

V

DDQ

V
DQ
DQ

DQP

V

V

DDQ

NC
NC
NC

SS

NC
NC

SS

NC

DD

NC

SS

SS

NC

SS

NC
NC
NC

1CE2

A

A

CE

100

9998979695

1
2
3
4
5
6
7
8

B

9

B

10
11
12

B

13

B

14
15
16
17
18

B

19

B

20
21
22

B

23

B

24

B

25
26
27
28
29
30

BBWA

NC

NC

BW

9493929190898887868584

CE3VDDV

SS

CLKWECEN

CY7C1231H

OE

ADV/LD

NC(9M)

NC(18M)

838281

A

A

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

A
NC
NC
V

DDQ

V

SS

NC
DQP
DQ
DQ
V

SS

V

DDQ

DQ
DQ
V

SS

NC
V

DD

ZZ
DQ

DQ
V

DDQ

V

SS

DQ
DQ
NC
NC
V

SS

V

DDQ

NC
NC
NC

A
A
A

A
A

BYTE A

A
A

A
A

313233

MODE

34

3536373839

A

A

A

A

A1

A0

4041424344454647484950

A

A

NC/288M

SS

V

NC/144M

DD

V

NC(72M)

A

NC(36M)

A

A

A

NC/4M

Document #: 001-00207 Rev. *B Page 2 of 12

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CY7C1231H

Pin Definitions

Name I/O Description

A0, A1, A Input-

Synchronous

BW

[A:B]

Input-

Synchronous

WE Input-

Synchronous

ADV/LD Input-

Synchronous

CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK

CE

CE

CE

1

2

3

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

OE Input-

Asynchronous

CEN Input-

Synchronous

ZZ Input-

Asynchronous

DQ

DQP

s

[A:B]

I/O-

Synchronous

I/O-

Synchronous

Mode Input

Strap Pin
V
V

V

DD
DDQ

SS

Power Supply Power supply inputs to the core of the device.

I/O Power

Supply

Ground Ground for the device.

NC – No Connects. Not Internally connected to the die. 4M, 9M, 18M, 36M, 72M, 144M, 288M, 576M, and

Address Inputs used to select one of the 128K address locations. Sampled at the rising edge of
the CLK. A

are fed to the two-bit burst counter.

[1:0]

Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the
rising edge of CLK.

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.

Advance/Load Input. Used to advance the on-chip address counter or load a new address. When
HIGH (and CEN
can be loaded into the device for an access. After being deselected, ADV/LD

is asserted LOW) the internal burst counter is advanced. When LOW, a new address

should be driven LOW

in order to load a new address.

is only recognized if CEN

is active LOW.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE

, and CE3 to select/deselect the device.

2

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

and CE3 to select/deselect the device.

CE

1

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE

and CE2 to select/deselect the device.

1

Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block
inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave
as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE

is masked
during the data portion of a write sequence, during the first clock when emerging from a deselected
state, when the device has been deselected.

Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM.
When deasserted HIGH the Clock signal is masked. Since deasserting CEN
device, CEN

can be used to extend the previous cycle when required.

does not deselect the

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin has
an internal pull-down.

Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by address during the clock rise of the read cycle. The direction of the pins is controlled by OE and
the internal control logic. When OE

and DQP

DQ

s

the data portion of a write sequence, during the first clock when emerging from a deselected state,

are placed in a tri-state condition. The outputs are automatically tri-stated during

[A:B]

and when the device is deselected, regardless of the state of OE

is asserted LOW, the pins can behave as outputs. When HIGH,

.

Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write
sequences, DQP

is controlled by BW

[A:B]

correspondingly.

x

Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When
tied to V

or left floating selects interleaved burst sequence.

DD

Power supply for the I/O circuitry.

1G are address expansion pins and are not internally connected to the die.

Document #: 001-00207 Rev. *B Page 3 of 12

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CY7C1231H

Functional Overview

The CY7C1231H is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN

). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
rise (t

Accesses can be initiated by asserting all three Chip Enables
(CE
Enable (CEN
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE
conduct Byte Write operations.

Write operations are qualified by the Write Enable (WE
writes are simplified with on-chip synchronous self-timed write
circuitry.

Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.

Single Read Accesses

A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be tri-stated
immediately.

Burst Read Accesses

The CY7C1231H has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new addre ss into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD
the state of Chip Enable inputs or WE
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.

) is 6.5 ns (133-MHz device).

CDV

, CE2, CE3) active at the rising edge of the clock. If Clock

1

) is active LOW and ADV/LD is asserted LOW,

). BW

can be used to

[A:B]

). All

, CE2, CE3) and an

1

) simplify depth expansion.

is asserted LOW, (2) CE1, CE2,

are ALL asserted active, (3) the Write Enable input

3

is deasserted HIGH, and 4) ADV/LD is asserted

is active LOW. After the first

will increment the internal burst counter regardless of

. WE is latched at the

Single Write Accesses

Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented to the address bus

are ALL asserted active, and (3) the Write signal WE

3

is asserted LOW, (2) CE1, CE2,

is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically tri-stated regardless of the state of the OE

input
signal. This allows the external logic to present the data on
DQs and DQP

On the next clock rise the data presented to DQs and DQP
(or a subset for Byte Write operations, see Truth Table for

[A:B]

.

[A:B]

details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.

The data written during the Write operation is controlled by
BW

signals. The CY7C1231H provides Byte Write

[A:B]

capability that is described in the Truth Table. Asserting the
Write Enable input (WE) with the selected Byte Write Select
input will selectively write to only the desired bytes. Bytes not
selected during a Byte Write operation will remain unaltered.
A synchronous self-timed write mechanism has bee n provided
to simplify the Write operations. Byte Write capability has been
included in order to greatly simplify Read/Modify/Write
sequences, which can be reduced to simple byte write opera­tions.

Because the CY7C1231H is a common I/O device, data
should not be driven into the device while the outputs are
active. The Output Enable (OE
before presenting data to the DQs and DQP
so will tri-state the output drivers. As a safety precaution, DQs
and DQP
portion of a write cycle, regardless of the state of OE

.are automatically tri-stated during the data

[A:B]

) can be deasserted HIGH

inputs. Doing

[A:B]

.

Burst Write Accesses

The CY7C1231H has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD

must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD
rise, the Chip Enables (CE
ignored and the burst counter is incremented. The correct
BW

inputs must be driven in each cycle of the burst write,

[A:B]

in order to write the correct bytes of data.

is driven HIGH on the subsequent clock

, CE2, and CE3) and WE inputs are

1

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
the duration of t

1, CE2, and CE3, must remain inactive for

after the ZZ input returns LOW.

ZZREC

Document #: 001-00207 Rev. *B Page 4 of 12

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