Cypress CY7C1218H User Manual

CY7C1218H

A

1-Mbit (32K x36) Pipelined Sync SRAM

Features

• Registered inputs and outputs for pipelined operation

• 32K × 36 common I/O architecture

• 3.3V core power supply (V

• 2.5V/3.3V I/O power supply (V

• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• Available in JEDEC-standard lead-free 100-Pin TQFP
package

• “ZZ” Sleep Mode Option

DD

)

DDQ

)

®

Functional Description

[1]

The CY7C1218H SRAM integrates 32K x 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE

), depth-expansion Chip Enables (CE2 and CE3), Burst

1

Control inputs (ADSC
(BW
inputs include the Output Enable (OE

, and BWE), and Global Write (GW). Asynchronous

[A:D]

, ADSP, and ADV), Write Enables

) and the ZZ pin.

Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
Address Strobe Controller (ADSC

) are active. Subsequent

) or

burst addresses can be internally generated as controlled by
the Advance pin (ADV

).

Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the Byte Write control inputs. GW

when active

LOW causes all bytes to be written.
The CY7C1218H operates from a +3.3V core power supply

while all outputs may operate either with a +2.5V or +3.3 V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.

Logic Block Diagram

0, A1, A

MODE

ADV

CLK

ADSC
ADSP

BW

D

BW

C

BW

B

BW

A

BWE

GW

CE

1

CE

2

CE

3

OE

ZZ

SLEEP

CONTROL

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

ADDRESS
REGISTER

D,DQD

DQ

BYTE

WRITE REGISTER

C

,DQPC

DQ

BYTE

WRITE REGISTER

B,

DQPB

DQ

BYTE

WRITE REGISTER

DQA ,DQP

A

BYTE

WRITE REGISTER

ENABLE

REGISTER

2

BURST

COUNTER

AND

CLR

LOGIC

PIPELINED

ENABLE

A

[1:0]

Q1

Q0

D

,DQP

D

DQ

BYTE

WRITE DRIVER

C

,DQPC

DQ

BYTE

WRITE DRIVER

B,

DQPB

DQ

BYTE

WRITE DRIVER

A,

DQP

A

DQ

BYTE

WRITE DRIVER

MEMORY

ARRAY

SENSE
AMPS

OUTPUT

REGISTERS

OUTPUT
BUFFERS

E

REGISTERS

INPUT

DQs
DQP

DQP
DQP

DQP

A
B
C
D

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05667 Rev. *B Revised July 6, 2006

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CY7C1218H

Selection Guide

166 MHz 133 MHz Unit

Maximum Access Time 3.5 4.0 ns
Maximum Operating Current 240 225 mA
Maximum CMOS Standby Current 40 40 mA

Pin Configuration

100-Pin TQFP

Top View

BYTE C

BYTE D

DQP

DQ
DQ

V

DDQ

V

SSQ

DQ
DQ
DQ
DQ

V

SSQ

V

DDQ

DQ
DQ

V

V
DQ
DQ

V

DDQ

V

SSQ

DQ
DQ
DQ
DQ

V

SSQ

V

DDQ

DQ
DQ

DQP

NC

DD

NC

SS

AACE1CE2BWDBWCBWBBWACE3VDDVSSCLKGWBWEOEADSC

100999897969594939291908988878685848382

C
C
C

1
2
3
4
5

C
C
C
C

6
7
8
9
10
11

C
C

12
13
14
15
16
17

D
D

18
19

CY7C1218H

20
21

D
D
D
D

22
23
24
25
26
27

D
D
D

28
29
30

31323334353637383940414243444546474849

ADSP

ADVAA

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

81

DQP
DQ
DQ
V

DDQ

V

SSQ

DQ
DQ
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
V

SS

NC
V

DD

ZZ
DQ
DQ
V

DDQ

V

SSQ

DQ
DQ
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
DQP

B
B
B

B

BYTE B

B
B
B

B
B

A
A

A
A

BYTE A

A
A

A
A

A

1

AAA

MODE

0

A

A

A

NC/72M

NC/36M

SS

DD

V

V

A

NC/9M

NC/18M

A

AAA

NC/2M

NC/4M

Document #: 38-05667 Rev. *B Page 2 of 16

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CY7C1218H

Pin Definitions

Name I/O Description

A

, A1, A Input-

0

BW

A, BWB

BWC, BW
GW

Synchronous

Synchronous

D

Input-

Input-

Synchronous

BWE

Input-

Synchronous

CLK Input-

Clock

CE

CE

CE

1

2

3

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

OE Input-

Asynchronous

ADV Input-

Synchronous

ADSP

Input-

Synchronous

ADSC

Input-

Synchronous

ZZ Input-

Asynchronous

DQ
DQ

DQP
DQP

V

DD

V

SS

V

DDQ

V

SSQ

A, DQB
C, DQD

A,

B

I/O-

Synchronous

Power Supply Power supply inputs to the core of the device.

Ground Ground for the core of the device.

I/O Power

Supply

I/O Ground Ground for the I/O circuitry.

MODE Input-

Static

NC No Connects. Not internally connected to the die. 2M, 4M, 9M,18M, 72M, 144M, 288M, 576M and

Address Inputs used to select one of the 32K address locations. Sampled at the rising edge
of the CLK if ADSP

or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1, A0

feed the 2-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM.

Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global

Write is conducted (ALL bytes are written, regardless of the values on BW

and BWE).

[A:D]

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a Byte Write.

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV

is asserted LOW, during a burst operation.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE

and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only

2

when a new external address is loaded.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

CE

and CE3 to select/deselect the device. CE2 is sampled only when a new external address is

1

loaded.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE

and CE2 to select/deselect the device. Not connected for BGA. Where referenced, CE3 is

1

assumed active throughout this document for BGA. CE
address is loaded.

is sampled only when a new external

3

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE

is masked during the first clock of a Read cycle when emerging from a

deselected state.
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it

automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When

asserted LOW, A is captured in the address registers. A
When

and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1

ADSP

, A0 are also loaded into the burst counter.

1

is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When

asserted LOW, A is captured in the address registers. A
When ADSP

and ADSC are both asserted, only ADSP is recognized.

, A0 are also loaded into the burst counter.

1

ZZ “Sleep” Input, active HIGH. This input, when High places the device in a non-time - critical
“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.

Bidirectional Data I/O lines. As inputs, they feed into an on-chip dat a register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by “A” during the previous clock rise of the Read cycle. The direction of the pins is controlled by
OE

. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP

placed in a tri-state condition.

[A:D]

are

Power supply for the I/O circuitry.

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V

floating selects interleaved burst sequence. This is a strap pin and should remain static during

DD

or left

device operation. Mode Pin has an internal pull-up.

1G are address expansion pins and are not internally connected to the die.

Document #: 38-05667 Rev. *B Page 3 of 16

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CY7C1218H

Functional Overview

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.

The CY7C1218H supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.

Byte Write operations are qualified with the Byte Write Enable
(BWE

) and Byte Write Select (BW
Enable (GW
all four bytes. All Writes are simplified with on-chip
synchronous self-timed Write circuitry.

Three synchronous Chip Selects (CE
asynchronous Output Enable (OE
selection and output tri-state control. ADSP
is HIGH.

Single Read Accesses

This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP
(2) CE

1

signals (GW

is HIGH. The address presented to the address inputs

if CE

1

(A) is stored into the address advancement logic and the
address register while being presented to the memory array.
The corresponding data is allowed to propagate to the input of
the output registers. At the rising edge of the next clock the
data is allowed to propagate through the outp ut register and
onto the data bus within t
exception occurs when the SRAM is emerging from a
deselected state to a selected state, its outputs are always
tri-stated during the first cycle of the access. After the first cycle
of the access, the outputs are controlled by the OE
Consecutive single Read cycles are supported. Once the
SRAM is deselected at clock rise by the chip select and either
ADSP

or ADSC signals, its output will tri-state immediately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP
(2) CE

1

presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW
ADV

inputs are ignored during this first cycle.

ADSP

-triggered Write accesses require two clock cycles to
complete. If GW
data presented to the DQ inputs is written into the corre­sponding address location in the memory array. If GW
then the Write operation is controlled by BWE

) or the Controller Address Strobe (ADSC).

) inputs. A Global Write

) overrides all Byte Write inputs and writes data to

[A:D]

, CE2, CE3) and an

1

) provide for easy bank

is ignored if CE

or ADSC is asserted LOW,

, CE2, CE3 are all asserted active, and (3) the Write

, BWE) are all deasserted HIGH. ADSP is ignored

if OE is active LOW. The only

CO

signal.

is asserted LOW, and

, CE2, CE3 are all asserted active. The address

, BWE, and BW

[A:D]

) and

is asserted LOW on the second clock rise, the

is HIGH,

and BW

[A:D]

signals. The CY7C1218H provides Byte Write capability that
is described in the Write Cycle Descriptions table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Write ( BW
bytes. Bytes not selected during a Byte Write operation will

) input, will selectively write to only the desired

[A:D]

remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.

Because the CY7C1218H is a common I/O device, the Output
Enable (OE

) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQ are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE

Single Write Accesses Initiated by ADSC

ADSC Write accesses are initiated when the following condi­tions are satisfied: (1) ADSC
deasserted HIGH, (3) CE
and (4) the appropriate combination of the Write inputs (GW
BWE

, and BW

the desired byte(s). ADSC

) are asserted active to conduct a Write to

[A:D]

is asserted LOW, (2) ADSP is

, CE2, CE3 are all asserted active,

1

-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the m emory array .
The ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to DQs is written into the corre­sponding address location in the memory core. If a Byte Write

1

is conducted, only the selected bytes are written. Bytes not
selected during a Byte Write operation will remain unaltered.
A synchronous self-timed Write mechanism has been
provided to simplify the Write operations.

Because the CY7C1218H is a common I/O device, the Output
Enable (OE

) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE

Burst Sequences

The CY7C1218H provides a two-bit wraparound counter, fed

, A0, that implements either an interleaved or linear burst

by A

1

sequence. The interleaved burst sequence is designed specif­ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user se lectable
through the MODE input.

Asserting ADV

LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
remain inactive for the duration of t
returns LOW.

, CE2, CE3, ADSP, and ADSC must

1

after the ZZ input

ZZREC

.

,

.

Document #: 38-05667 Rev. *B Page 4 of 16

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CY7C1218H

Interleaved Burst Address Table
(MODE = Floating or V

First

Address

A1, A

0

Second

Address

A1, A

)

DD

Third

Address

0

A1, A

0

00 01 10 11
01 00 11 10
10 11 00 01

Fourth

Address

A1, A

0

Linear Burst Address Table (MODE = GND)

First

Address

A1, A

0

00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10

Second

Address

A1, A

0

Third

Address

A1, A

0

Fourth

Address

A1, A

11 10 01 00

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Truth Table

Next Cycle Add. Used ZZ CE1CE2CE3ADSP ADSC ADV OE DQ Write

Unselected None L H X X X L X X Tri-State X
Unselected None L L X H L X X X Tri-State X
Unselected None L L L X L X X X Tri-S tate X
Unselected None L L X H H L X X Tri-State X
Unselected None L L L X H L X X Tri-State X
Begin Read External L L H L L X X X Tri-State X
Begin Read External L L H L H L X X Tri-State Read
Continue Read Next L X X X H H L H Tri-State Read
Continue Read Next L X X X H H L L DQ Read
Continue Read Next L H X X X H L H Tri-State Read
Continue Read Next L H X X X H L L DQ Read
Suspend Read Current L X X X H H H H Tri-State Read
Suspend Read Current L X X X H H H L DQ Read
Suspend Read Current L H X X X H H H Tri-State Read
Suspend Read Current L H X X X H H L DQ Read
Begin Write Current L X X X H H H X Tri-State Write
Begin Write Current L H X X X H H X Tri-State Write
Begin Write External L L H L H H X X Tri-State Write

Sleep mode standby current ZZ > VDD – 0.2V 40 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ Active to sleep current This parameter is sampled 2t

CYC

CYC

ZZ Inactive to exit sleep current This parameter is sampled 0 ns

[2, 3, 4, 5, 6, 7]

0

ns
ns
ns

Notes:

2. X = “Don't Care.” H = HIGH, L = LOW.

3. WRITE = L when any one or more Byte Write Enable signals (BW
(BW

,BWB,BWC,BWD), BWE, GW = H.

A

4. The DQ pins are controlled by the current cycle and the OE

, CE2, and CE3 are available only in the TQFP package.

5. CE

1

6. The SRAM always initiates a read cycle when ADSP
after the ADSP
don't care for the remainder of the Write cycle.

is asynchronous and is not sampled with the clock rise. It is masked internally during W rite cycles. During a Read cycle al l dat a bit s are tri-st ate when OE is

7. OE
inactive or when the device is deselected, and all data bits behave as output when OE

or with the assertion of ADSC. As a result, OE must b e driven HIGH prio r to th e st art of t he W r ite cycle to a llow t he outp uts to Tri-State. OE is a

is asserted, regardless of the state of GW , BWE , or BW

,BWB,BWC,BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals

A

signal. OE is asynchronous and is not sampled with the clock.

. Writes may occur only on subsequent clocks

[A:D]

is active (LOW).

Document #: 38-05667 Rev. *B Page 5 of 16

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