Cypress CY7C1217H User Manual

CY7C1217H

1-Mbit (32K x 36) Flow-Through Sync SRAM

Features

• 32K x 36 common I/O

• 3.3V core power supply (V

• 2.5V/3.3V I/O power supply (V

• Fast clock-to-output times
— 6.5 ns (for 133-MHz version )

• Provide high-performance 2-1-1-1 access rate

• User-selectable burst counter supporting Intel
Pentium

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• Available in JEDEC-standard lead-free 100-Pin TQFP
package

• “ZZ” Sleep Mode option

®

interleaved or linear burst sequences

DD

)

DDQ

)

®

Functional Description

The CY7C1217H is a 32K x 36 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati­cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-trigg ered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE

), depth-expansion Chip Enables (CE2 and CE3), Burst

1

Control inputs (ADSC
(BW
inputs include the Output Enable (OE

The CY7C1217H allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP
Address Strobe (ADSC
controlled by the Address Advancement (ADV

Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
Address Strobe Controller (ADSC
burst addresses can be internally generated as controlled by
the Advance pin (ADV).

The CY7C1217H operates from a +3.3V core power supply
while all outputs may operate either with a +2.5V or +3.3 V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.

, and BWE), and Global Write (GW). Asynchronous

[A:D]

[1]

, ADSP, and ADV), Write Enables

) and the ZZ pin.

) or the cache Controller

) inputs. Address advancement is

) input.

) or

) are active. Subsequent

Selection Guide

133 MHz 100 MHz Unit

Maximum Access Time 6.5 8.0 ns
Maximum Operating Current 225 205 mA
Maximum Standby Current 40 40 mA

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05670 Rev. *B Revised July 6, 2006

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Logic Block Diagram

s

A
B
C
D

A

CY7C1217H

0, A1, A

ADDRESS
REGISTER

A

[1:0]

MODE

ADV

CLK

CLR

ADSC
ADSP

DQ

D

,

DQP

BW

D

BW

C

BW

B

WRITE REGISTER

BW

A

BWE

GW
CE1

CE2
CE3

OE

D

BYTE

BYTE

WRITE REGISTER

WRITE REGISTER

DQ

C

,

DQP

C

BYTE

WRITE REGISTER

DQ

B

,

DQP

B

BYTE

DQ

A

,

DQP

A

BYTE

WRITE REGISTER

ENABLE

REGISTER

Q1

BURST

COUNTER

AND LOGIC

Q0

DQ

D

,

DQP

D

BYTE

WRITE REGISTER

DQ

C

,

DQP

C

BYTE

WRITE REGISTER

DQ

B

,

DQP

B

BYTE

WRITE REGISTER

DQ

A

,

DQP

A

BYTE

WRITE REGISTER

MEMORY

ARRAY

SENSE
AMPS

OUTPUT
BUFFERS

INPUT

REGISTERS

DQ
DQP
DQP
DQP
DQP

ZZ

SLEEP

CONTROL

Document #: 38-05670 Rev. *B Page 2 of 16

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Pin Configuration

100-Pin TQFP

CY7C1217H

BYTE C

BYTE D

DQP

DQ
DQ

V

DDQ

V

SSQ

DQ
DQ
DQ
DQ

V

SSQ

V

DDQ

DQ
DQ

V
NC

V
DQ
DQ

V

DDQ

V

SSQ

DQ
DQ
DQ
DQ

V

SSQ

V

DDQ

DQ
DQ

DQP

NC

DD

SS

A

100

1

C

2

C

3

C

CE

CE

99989796959493929190898887868584838281

2BWDBWC

1

A

4
5
6

C

7

C

8

C

9

C

10
11
12

C

13

C

14
15
16
17
18

D

19

D

20
21
22

D

23

D

24

D

25

D

26
27
28

D

29

D

30

D

3

A

CE

BWBBW

VDDV

CY7C1217H

SS

CLK

GW

BWE

OE

ADSC

ADSP

ADV

A

A

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DQP
DQ

B

DQ

B

V

DDQ

V

SSQ

DQ

B

DQ

B

DQ

B

DQ

B

V

SSQ

V

DDQ

DQ

B

DQ

B

V

SS

NC
V

DD

ZZ
DQ

A

DQ

A

V

DDQ

V

SSQ

DQ

A

DQ

A

DQ

A

DQ

A

V

SSQ

V

DDQ

DQ

A

DQ

A

DQPA

B

BYTE B

BYTE A

31323334353637383940414243444546474849

AAAAA1A

MODE

0

SS

DD

V

V

NC/72M

NC/36M

NC/9M

NC/18M

AAAAA

NC/2M

50

NC/4M

Document #: 38-05670 Rev. *B Page 3 of 16

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CY7C1217H

Pin Descriptions

Name I/O Description

A0, A1, A Input-

Synchronous

, BW

BW

A

BWC, BW

B
D

Input-

Synchronous

GW Input-

Synchronous

BWE Input-

Synchronous

CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment

CE

CE

CE

OE

1

2

3

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Asynchronous

ADV Input-

Synchronous

ADSP

Input-

Synchronous

ADSC

Input-

Synchronous

ZZ Input-

Asynchronous

DQs
DQP
DQP

V

DD

V

SS

V

DDQ

V

SSQ

A,

C,

DQP

DQP

B
D

I/O-

Synchronous

Power Supply Power supply inputs to the core of the device.

Ground Ground for the core of the device.

I/O Power Supply Power supply for the I/O circuitry.

I/O Ground Ground for the I/O circuitry.

MODE Input-

Static

NC No Connects. Not Internally connected to the die. 2M, 4M, 9M, 18M, 72M, 144M, 288M,

Address Inputs used to select one of the 32K address locations. Sampled at the rising
edge of the CLK if ADSP
A

feed the 2-bit counter.

[1:0]

or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active.

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the
SRAM. Sampled on the rising edge of CLK.

Global Write Enable Input, acti ve LOW . When asserted LOW on the rising edge of CLK, a
global Write is conducted (ALL bytes are written, regardless of the values on BW
BWE

).

[A:D]

and

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a Byte Write.

the burst counter when ADV

is asserted LOW, during a burst operation.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
sampled only when a new external address is loaded.

and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is

2

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
address is loaded.

and CE3 to select/deselect the device. CE

1

is sampled only when a new external

2

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
address is loaded.

and CE2 to select/deselect the device. CE3 is sampled only when a new external

1

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a Read cycle when emerging
from a deselected state.

Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.

Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A
are also loaded into the burst counter. When ADSP
is recognized. ASDP

is ignored when CE1 is deasserted HIGH

and ADSC are both asserted, only ADSP

[1:0]

Address Strobe from Controller , sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A
are also loaded into the burst counter. When ADSP

and ADSC are both asserted, only ADSP

[1:0]

is recognized.
ZZ “Sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical

“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW
or left floating. ZZ pin has an internal pull-down.

Bidirectional Data I/O lines. As input s, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the Read cycle. The
direction of the pins is controlled by OE
outputs. When HIGH, DQs and DQP

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
left floating selects interleaved burst sequence. This is a strap pin and should remain static

. When OE is asserted LOW, the pins behave as

are placed in a tri-state condition.

[A:D]

DD

during device operation. Mode Pin has an internal pull-up.

576M and 1G are address expansion pins and are not internally connected to the die.

or

Document #: 38-05670 Rev. *B Page 4 of 16

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CY7C1217H

Functional Overview

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access d elay from
the clock rise (t

The CY7C1217H supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP

). Address advancement through the burst sequence is

(ADSC
controlled by the ADV
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.

Byte write operations are qualified with the Byte Write Enable
(BWE

) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW
all four bytes. All Writes are simplified with on-chip
synchronous self-timed write circuitry.

Three synchronous Chip Selects (CE
asynchronous Output Enable (OE
selection and output tri-state control. ADSP
is HIGH.

Single Read Accesses

A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
asserted active, and (2) ADSP
the access is initiated by ADSC
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to t
rise. ADSP

is ignored if CE1 is HIGH.

Single Write Accesses Initiated by ADSP

This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, and (2) ADSP
presented are loaded into the address register and the burst
inputs (GW

, BWE, and BW[A:D]) are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
Write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte Writes are allowed.
During Byte Writes, BW
DQ

, BWC controls DQC, and BWD controls DQD. All I/Os are

B

tri-stated during a Byte Write. Since this is a common I/O
device, the asynchronous OE input signal must be deasserted
and the I/Os must be tri-stated prior to the presentation of data
to DQs. As a safety precaution, the data lines are tri -stated
once a write cycle is detected, regardless of the state of OE

Single Write Accesses Initiated by ADSC

This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, (2) ADSC

) is 6.5 ns (133-MHz device).

CDV

) or the Controller Address Strobe

input. A two-bit on-chip wraparound

) overrides all Byte Write inputs and writes data to

, CE2, CE3) and an

1

) provide for easy bank

is ignored if CE

, CE2, and CE3 are all

1

or ADSC is asserted LOW (if

, the write inputs must be

after clock

CDV

, CE2, and CE3 are all asserted

1

is asserted LOW. The addresses

controls DQA and BWB controls

A

, CE2, and CE3 are all asserted

is asserted LOW, (3) ADSP is deasserted

1

HIGH, and (4) the write input signals (GW, BWE, and BW[A:D])
indicate a write access. ADSC

is ignored if ADSP is active

LOW.
The addresses presented are loaded into the address register

and the burst counter/control logic and delivered to the
memory core. The information presented to DQ[A:D will be
written into the specified address location. Byte Writes are
allowed. During Byte Writes, BW
DQ

, BWC controls DQC, and BWD controls DQD. All I/Os are

B

tri-stated when a write is detected, even a Byte Write. Since

controls DQA, BWB controls

A

this is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a Write cycle is detected, regardless
of the state of OE

.

Burst Sequences

The CY7C1217H provides an on-chip two-bit wraparound
burst counter inside the SRAM. The burst counter is fed by
A

, and can follow either a linear or interleaved burst order.

[1:0]

The burst order is determined by the state of the MODE input.
A LOW on MODE will select a linear burst sequence. A HIGH
on MODE will select an interleaved burst order. Leaving
MODE unconnected will cause the device to default to a inter­leaved burst sequence.

Sleep Mode

1

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
inactive for the duration of t
LOW.

s, ADSP, and ADSC must remain

after the ZZ input returns

ZZREC

Interleaved Burst Address Table
(MODE = Floating or V

First

Address

A1, A0

00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

Second

Address

A1, A0

DD

)

Third

Address

A1, A0

Linear Burst Address Table (MODE = GND)

First

Address

A1, A

0

00 01 10 11

.

01 10 11 00
10 11 00 01
11 00 01 10

Second

Address

A1, A

0

Third

Address

A1, A

0

Fourth

Address

A1, A0

Fourth

Address

A1, A

0

Document #: 38-05670 Rev. *B Page 5 of 16

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