Cypress CY7C1215H User Manual

CY7C1215H

A

s

1-Mbit (32K x 32) Pipelined Sync SRAM

Features

• Registered inputs and outputs for pipelined operation

• 32K × 32 common I/O architecture

• 3.3V core power supply (V

• 2.5V/3.3V I/O power supply (V

DD

)

DDQ

)

• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel
Pentium

®

interleaved or linear burst sequences

®

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• Offered in JEDEC-standard lead-free 100-pin TQFP
package

• “ZZ” Sleep Mode Option

Logic Block Diagram

Functional Description

[1]

The CY7C1215H SRAM integrates 32K x 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE

), depth-expansion Chip Enables (CE2 and CE3), Burst

1

Control inputs (ADSC
(BW
inputs include the Output Enable (OE

, and BWE), and Global Write (GW). Asynchronous

[A:D]

, ADSP, and ADV), Write Enables

) and the ZZ pin.

Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
Address Strobe Controller (ADSC

) are active. Subsequent

) or

burst addresses can be internally generated as controlled by
the Advance pin (ADV

).

Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the Byte Write control inputs. GW

when active

LOW causes all bytes to be written.
The CY7C1215H operates from a +3.3V core power supply

while all outputs may operate either with a + 2.5V or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.

0, A1, A

MODE

ADV

CLK

ADSC
ADSP

BW

D

BW

C

BW

B

BW

A

BWE

GW

CE

1

CE

2

CE

3

OE

ZZ

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

SLEEP

CONTROL

ADDRESS
REGISTER

D

DQ

BYTE

WRITE REGISTER

C

DQ
BYTE

WRITE REGISTER

B

DQ

BYTE

WRITE REGISTER

DQA

BYTE

WRITE REGISTER

ENABLE

REGISTER

2

BURST

COUNTER

AND

CLR

LOGIC

PIPELINED

ENABLE

A

[1:0]

Q1

Q0

D

DQ

BYTE

WRITE DRIVER

C

DQ

BYTE

WRITE DRIVER

B

DQ

BYTE

WRITE DRIVER

A

DQ

BYTE

WRITE DRIVER

MEMORY

ARRAY

SENSE
AMPS

OUTPUT

REGISTERS

OUTPUT
BUFFERS

E

INPUT

REGISTERS

DQ

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05666 Rev. *B Revised July 5, 2006

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CY7C1215H

Selection Guide

166 MHz 133 MHz Unit

Maximum Access Time 3.5 4.0 ns
Maximum Operating Current 240 225 mA
Maximum CMOS Standby Current 40 40 mA

Pin Configuration

100-Pin TQFP

Top View

BYTE C

BYTE D

V

V

V

V

V

V

V

V

DQ
DQ

DDQ
SSQ

DQ
DQ
DQ
DQ

SSQ
DDQ

DQ
DQ

V

V
DQ
DQ

DDQ

SSQ

DQ
DQ
DQ
DQ

SSQ

DDQ

DQ
DQ

NC

NC

DD

NC

SS

NC

AACE1CE2BWDBWCBWBBWACE3VDDVSSCLKGWBWEOEADSC

100999897969594939291908988878685848382

1

C
C

2
3
4
5

C
C
C
C

6
7
8
9
10
11

C
C

12
13
14
15

CY7C1215H

16
17

D
D

18
19
20
21

D
D
D
D

22
23
24
25
26
27

D
D

28
29
30

ADSP

ADVAA

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

81

NC
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
V
NC
V
ZZ
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
NC

B

B
DDQ
SSQ

B

B

B

B
SSQ
DDQ

B

B
SS

DD

A

A
DDQ
SSQ

A

A

A

A
SSQ
DDQ

A

A

BYTE B

BYTE A

31323334353637383940414243444546474849

AAA

MODE

1A0

A

A

NC/72M

NC/36M

DD

SS

V

V

NC/18M

A

A

A

A

NC/9M

A

50

NC/2M

NC/4M

Document #: 38-05666 Rev. *B Page 2 of 15

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CY7C1215H

Pin Definitions

Name I/O Description

A

, A1, A Input-

0

BW

A, BWB

BWC, BW
GW

Synchronous

Synchronous

D

Input-

Input-

Synchronous

BWE

Input-

Synchronous

CLK Input-

Clock

CE

CE

CE

1

2

3

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

OE Input-

Asynchronous

ADV Input-

Synchronous

ADSP

Input-

Synchronous

ADSC

Input-

Synchronous

ZZ Input-

Asynchronous

DQs I/O-

Synchronous

V
V
V

V

DD
SS
DDQ

SSQ

Power Supply Power supply inputs to the core of the device.

Ground Ground for the core of the device.

I/O Power

Supply

I/O Ground Ground for the I/O circuitry.

MODE Input-

Static

NC No Connects. Not internally connected to the die. 2M, 4M, 9M, 18M, 72M, 144M, 288M, 576M

Address Inputs used to select one of the 32K address locations. Sampled at the rising edge
of the CLK if ADSP

or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1, A0

feed the 2-bit counter.
Byte Write Select Inputs, active LOW . Qualified with BWE to conduct Byte Writes to the SRAM.

Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global

Write is conducted (ALL bytes are written, regardless of the values on BW

and BWE).

[A:D]

Byte Write Enable Input, a ctive L OW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV

is asserted LOW, during a burst operation.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only

CE

2

when a new external address is loaded.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

CE

and CE3 to select/deselect the device. CE2 is sampled only when a new external address is

1

loaded.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE

and CE2 to select/deselect the device.

1

assumed active throughout this document for BGA.

Not connected for BGA. Where referenced, CE

CE3 is sampled only when a new external

is

3

address is loaded.
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When

LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE

is masked during the first clock of a Read cycle when emerging from a

deselected state.
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it

automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When

asserted LOW, A is captured in the address registers. A
When ADSP

and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1

, A0 are also loaded into the burst counter.

1

is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When

asserted LOW, A is captured in the address registers. A
When ADSP

and ADSC are both asserted, only ADSP is recognized.

, A0 are also loaded into the burst counter.

1

ZZ “Sleep” Input, active HIGH. This input, when HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by “A” during the previous clock rise of the Read cycle. The direction of the pins is
controlled by OE

. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ are

placed in a tri-state condition.

Power supply for the I/O circuitry.

Selects Burst Order. When tied to GND select s linear burst sequence. When tied to V

floating selects interleaved burst sequence. This is a strap pin and should remain static during

DD

or left

device operation. Mode Pin has an internal pull-up.

and 1G are address expansion pins and are not internally connected to the die.

Document #: 38-05666 Rev. *B Page 3 of 15

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CY7C1215H

Functional Overview

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.

The CY7C1215H supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.

Byte Write operations are qualified with the Byte Write Enable
(BWE

) and Byte Write Select (BW
Enable (GW
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.

Three synchronous Chip Selects (CE
asynchronous Output Enable (OE
selection and output tri-state control. ADSP
is HIGH.

Single Read Accesses

This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP
(2) CE

1

signals (GW

is HIGH. The address presented to the address inputs (A)

CE

1

is stored into the address advancement logic and the address
register while being presented to the memory array. The corre­sponding data is allowed to propagate to the input of the output
registers. At the rising edge of the next clock the data is
allowed to propagate through the output register and onto the
data bus within t
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always tri-stated during the
first cycle of the access. After the first cycle of the access, the
outputs are controlled by the OE
Read cycles are supported. Once the SRAM is deselected at
clock rise by the chip select and either ADSP
its output will tri-state immediately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP
(2) CE

1

presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW
ADV

inputs are ignored during this first cycle.

ADSP

-triggered Write accesses require two clock cycles to
complete. If GW
data presented to the DQ inputs is written into the corre­sponding address location in the memory array. If GW
then the Write operation is controlled by BWE

) or the Controller Address Strobe (ADSC).

) inputs. A Global Write

) overrides all Byte Write inputs and writes data to

[A:D]

, CE2, CE3) and an

1

) provide for easy bank

is ignored if CE

or ADSC is asserted LOW,

, CE2, CE3 are all asserted active, and (3) the Write

, BWE) are all deserted HIGH. ADSP is ignored if

if OE is active LOW. The only exception

CO

signal. Consecutive single

or ADSC signals,

is asserted LOW, and

, CE2, CE3 are all asserted active. The address

, BWE, and BW

[A:D]

) and

is asserted LOW on the second clock rise, the

is HIGH,

and BW

[A:D]

signals. The CY7C1215H provides Byte Write capability that
is described in the Write Cycle Descriptions table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Write ( BW
bytes. Bytes not selected during a Byte Write operation will

) input, will selectively write to only the desired

[A:D]

remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.

Because the CY7C1215H is a common I/O device, the Output
Enable (OE

) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE

Single Write Accesses Initiated by ADSC

ADSC Write accesses are initiated when the following condi­tions are satisfied: (1) ADSC
deserted HIGH, (3) CE
(4) the appropriate combination of the Write inputs (GW
and BW
desired byte(s). ADSC

) are asserted active to conduct a Write to the

[A:D]

is asserted LOW, (2) ADSP is

, CE2, CE3 are all asserted active, and

1

-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the m emory array .
The ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to DQ is written into the corre­sponding address location in the memory core. If a Byte Write

1

is conducted, only the selected bytes are written. Bytes not
selected during a Byte Write operation will remain unaltered.
A synchronous self-timed Write mechanism has been
provided to simplify the Write operations.

Because the CY7C1215H is a common I/O device, the Output
Enable (OE

) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQ are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE

Burst Sequences

The CY7C1215H provides a two-bit wraparound counter, fed

, A0, that implements either an interleaved or linear burst

by A

1

sequence. The interleaved burst sequence is designed specif­ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user se lectable
through the MODE input.

Asserting ADV

LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
remain inactive for the duration of t
returns LOW.

, CE2, CE3, ADSP, and ADSC must

1

after the ZZ input

ZZREC

.

, BWE,

.

Document #: 38-05666 Rev. *B Page 4 of 15

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CY7C1215H

Interleaved Burst Address Table
(MODE = Floating or V

First

Address

A1, A

0

Second

Address

A1, A

)

DD

Third

Address

0

A1, A

0

00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

Fourth

Address

A1, A

0

Linear Burst Address Table
(MODE = GND)

First

Address

A1, A

0

00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10

Second

Address

A1, A

0

Third

Address

A1, A

Fourth

Address

0

A1, A

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Truth Table

Next Cycle Add. Used ZZ CE1CE2CE3ADSP ADSC ADV OE DQ Write

Unselected None L H X X X L X X Tri-State X
Unselected None L L X H L X X X Tri-State X
Unselected None L L L X L X X X Tri-State X
Unselected None L L X H H L X X Tri-State X
Unselected None L L L X H L X X Tri-State X
Begin Read External L L H L L X X X Tri-State X
Begin Read External L L H L H L X X Tri-State Read
Continue Read Next L X X X H H L H Tri-State Read
Continue Read Next L X X X H H L L DQ Read
Continue Read Next L H X X X H L H Tri-State Read
Continue Read Next L H X X X H L L DQ Read
Suspend Read Current L X X X H H H H Tri-State Read
Suspend Read Current L X X X H H H L DQ Read
Suspend Read Current L H X X X H H H Tri-State Read
Suspend Read Current L H X X X H H L DQ Read
Begin Write Current L X X X H H H X Tri-State Write
Begin Write Current L H X X X H H X Tri-State Write
Begin Write External L L H L H H X X Tri-State Write
Continue Write Next L X X X H H H X Tri-State Write

Sleep mode standby current ZZ > VDD – 0.2V 40 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ Active to sleep current This parameter is sampled 2t

CYC

CYC

ZZ Inactive to exit sleep current This parameter is sampled 0 ns

[2, 3, 4, 5, 6]

ns
ns
ns

0

Notes:

2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

3. WRITE = L when any one or more Byte Write Enable signals (BW
(BW

,BWB,BWC,BWD), BWE, GW = H.

A

4. The DQ pins are controlled by the current cycle and the OE

5. The SRAM always initiates a Read cycle when ADSP
after the ADSP
don't care for the remainder of the Write cycle

is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE

6. OE
is inactive or when the device is deselected, and all data bits behave as output when OE

or with the assertion of ADSC. As a result, OE must b e driven HIGH prio r to th e st art of t he W r ite cycle to a llow t he outp uts to Tri-State. OE is a

is asserted, regardless of the sta te of GW, BWE, or BW

,BWB,BWC,BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals

A

signal. OE is asynchronous and is not sampled with the clock.

is active (LOW).

. Writes may occur only on subsequent clocks

[A:D]

Document #: 38-05666 Rev. *B Page 5 of 15

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CY7C1215H

Truth Table for Read/Write

Function GW BWE BW

[2, 3]

D

BW

C

BW

B

BW

A

Continue Write Next L H X X X
Suspend Write Current L X X X H
Suspend Write Current L H X X X
ZZ “Sleep” NoneHXXXX
Read HHXXXX
Read HLHHHH
Write Byte A – DQ
Write Byte B – DQ

A

B

HLHHHL

HLHHLH
Write Bytes B, A H L H H L L
Write Byte C – DQ

C

HLHLHH
Write Bytes C, A H L H L H L
Write Bytes C, B H L H L L H
Write Bytes C, B, A H L H L L L
Write Byte D – DQ

D

HLLHHH
Write Bytes D, A H L L H H L
Write Bytes D, B H L L H L H
Write Bytes D, B, A H L L H L L
Write Bytes D, C H L L L H H
Write Bytes D, C, A H L L L H L
Write Bytes D, C, B HLLLLH
Write All Bytes HLLLLL
Write All Bytes LXXXXX

Document #: 38-05666 Rev. *B Page 6 of 15

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CY7C1215H

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature ................................–65°C to + 150°C

Ambient Temperature with

Power Applied............................................–55°C to + 125°C

Supply Voltage on V
Supply Voltage on V

Relative to GND.......–0.5V to + 4.6V

DD

Relative to GND.....–0.5V to + V

DDQ

DD

DC Voltage Applied to Outputs

in Tri-State........................................ ...–0.5V to V

DDQ

+ 0.5V

Electrical Characteristics Over the Operating Range

DC Input Voltage...................................–0.5V to V

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-up Current..................................................... >200 mA

Operating Range

Range

Commercial 0°C to +70°C 3.3V
Industrial –40°C to +85°C

[7, 8]

Ambient

Temperature V

–5%/+10%

DD

+ 0.5V

DD

V

DDQ

2.5V –5%
to V

DD

Parameter Description Test Conditions Min. Max. Unit

V
V

DD
DDQ

Power Supply Voltage 3.135 3.6 V
I/O Supply Voltage for 3.3V I/O 3.135 V

DD

for 2.5V I/O 2.375 2.625 V

V

OH

V

OL

V

IH

V

IL

Output HIGH Voltage for 3.3V I/O, I

for 2.5V I/O, I

Output LOW Voltage for 3.3V I/O, I

for 2.5V I/O, I

Input HIGH Voltage

[7]

for 3.3V I/O 2.0 V
for 2.5V I/O 1.7 V

Input LOW Voltage

[7]

for 3.3V I/O –0.3 0.8 V

= –4.0 mA 2.4 V

OH

= –1.0 mA 2.0 V

OH

= 8.0 mA 0.4 V

OL

= 1.0 mA 0.4 V

OL

+ 0.3V V

DD

+ 0.3V V

DD

for 2.5V I/O –0.3 0.7

I

X

I

OZ

I

DD

I

SB1

I

SB2

I

SB3

I

SB4

Input Leakage Current

GND ≤ VI ≤ V

except ZZ and MODE
Input Current of MODE Input = V

Input = V

Input Current of ZZ Input = V

Input = V

SS
DD
SS
DD

Output Leakage Current GND ≤ VI ≤ V
VDD Operating Supply

Current
Automatic CS

Power-down
Current—TTL Inputs

Automatic CS
Power-down
Current—CMOS Inputs

Automatic CS
Power-down
Current—CMOS Inputs

Automatic CS
Power-down
Current—TTL Inputs

V

= Max., I

DD

f = f
V

V
f = f

V
V
f = 0

V
V
f = f

V
V

= 1/t

MAX

= Max, Device Deselected,

DD

≥ VIH or VIN ≤ V

IN

= 1/t

MAX

= Max, Device Deselected,

DD

≤ 0.3V or VIN > V

IN

= Max, Device Deselected, or

DD

≤ 0.3V or VIN > V

IN

= 1/t

MAX

= Max, Device Deselected,

DD

≥ VIH or VIN ≤ VIL, f = 0

IN

DDQ

–5 5 µA

–30 µA

–5 µA

Output Disabled –5 5 µA

DDQ,

OUT

CYC

= 0 mA,

6-ns cycle,166 MHz 240 mA

7.5-ns cycle, 133 MHz 225 mA
6-ns cycle,166 MHz 100 mA

IL

CYC

7.5-ns cycle, 133 MHz 90 mA
All speeds 40 mA

– 0.3V,

DDQ

6-ns cycle,166 MHz 85 mA

– 0.3V

DDQ

CYC

7.5-ns cycle, 133 MHz 75 mA
All speeds 45 mA

5 µA

30 µA

V

V

Notes:

7. Overshoot: V

8. T

Power-up

(AC) < VDD +1.5V (Pulse width less than t

IH

: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and V

/2), undershoot: VIL(AC) > –2V (Pulse width less than t

CYC

DDQ

< VDD.

CYC

/2).

Document #: 38-05666 Rev. *B Page 7 of 15

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CY7C1215H

Capacitance

[9]

Parameter Description Test Conditions

CIN Input Capacitance TA = 25°C, f = 1 MHz,

V

= 3.3V.

C

CLK

C

I/O

Thermal Resistance

Clock Input Capacitance 5 pF
Input/Output Capacitance 5 pF

[9]

V

DD

DDQ

= 2.5V

Parameter Description Test Conditions

Θ

JA

Θ

JC

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51

AC Test Loads and Waveforms

3.3V I/O Test Load

OUTPUT

Z

0

3.3V

= 50Ω

R

VT= 1.5V

(a) (b)

= 50Ω

L

OUTPUT

INCLUDING

JIG AND

SCOPE

5pF

R = 317Ω

R = 351Ω

V

DDQ

GND

≤ 1 ns

ALL INPUT PULSES

10%

90%

100 TQFP

Max. Unit

5 pF

100 TQFP

Package Unit

30.32 °C/W

6.85 °C/W

90%

10%

≤ 1 ns

(c)

2.5V I/O Test Load

OUTPUT

= 50Ω

Z

0

= 1.25V

V

T

R

= 50Ω

L

2.5V

OUTPUT

5pF

INCLUDING

JIG AND

SCOPE

R = 1667Ω

R =1538Ω

(a) (b)

Note:

9. Tested initially and after any design or process change that may affect these parameters.

V

DDQ

GND

≤ 1 ns

ALL INPUT PULSES

10%

90%

(c)

90%

10%

1 ns

≤

Document #: 38-05666 Rev. *B Page 8 of 15

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CY7C1215H

Switching Characteristics Over the Operating Range

Parameter Description

t

POWER

Clock

t

CYC

t

CH

t

CL

Output Times

t

CO

t

DOH

t

CLZ

t

CHZ

t

OEV

t

OELZ

t

OEHZ

Set-up Times

t

AS

t

ADS

t

ADVS

t

WES

t

DS

t

CES

Hold Times

t

AH

t

ADH

t

ADVH

t

WEH

t

DH

t

CEH

VDD(Typical) to the First Access

Clock Cycle Time 6.0 7.5 ns
Clock HIGH 2.5 3.0 ns
Clock LOW 2.5 3.0 ns

Data Output Valid after CLK Rise 3.5 4.0 ns
Data Output Hold after CLK Rise 1.5 1.5 ns
Clock to Low-Z
Clock to High-Z

[13, 14, 15]

[13, 14, 15]

OE LOW to Output Valid 3.5 4.5 ns
OE LOW to Output Low-Z
OE HIGH to Output High-Z

Address Set-up before CLK Rise 1.5 1.5 ns
ADSC, ADSP Set-up before CLK Rise 1.5 1.5 ns
ADV Set-up before CLK Rise 1.5 1.5 ns
GW, BWE, BW

Set-up before CLK Rise 1.5 1.5 ns

[A:D]

Data Input Set-up before CLK Rise 1.5 1.5 ns
Chip Enable Set-Up before CLK Rise 1.5 1.5 ns

Address Hold after CLK Rise 0.5 0.5 ns
ADSP, ADSC Hold after CLK Rise 0.5 0.5 ns
ADV Hold after CLK Rise 0.5 0.5 ns
GW, BWE, BW

Hold after CLK Rise 0.5 0.5 ns

[A:D]

Data Input Hold after CLK Rise 0.5 0.5 ns
Chip Enable Hold after CLK Rise 0.5 0.5 ns

[12]

[13, 14, 15]

[13, 14, 15]

[10, 11]

166 MHz 133 MHz

Min. Max Min. Max

1 1ms

0 0 ns

3.5 4.0 ns

0 0 ns

3.5 4.0 ns

Unit

Notes:

10.Timing reference level is 1.5V when V

11.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

12.This part has a voltage regulator internally; t
can be initiated.

, t

13.t

CHZ

14.At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect para meters guaran teed over worst case user conditi ons. Device is d esigned
to achieve High-Z prior to Low-Z under the same system conditions.

15.This parameter is sampled and not 100% tested.

CLZ,tOELZ

, and t

are specified with AC test conditions shown in p art (b) of AC Test Loads. Transition is measured ± 200 mV from ste ady-state vo ltage.

OEHZ

= 3.3V and is 1.25 when V

DDQ

is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation

POWER

is less than t

OEHZ

OELZ

and t

= 2.5V.

DDQ

is less than t

CHZ

to eliminate bus contention between SRAMs when sharing the same

CLZ

Document #: 38-05666 Rev. *B Page 9 of 15

[+] Feedback

Switching Waveforms

D

Read Cycle Timing

[16]

t

CYC

CY7C1215H

CLK

ADSP

ADSC

ADDRESS

GW, BWE,

BW[A:D]

CE

ADV

OE

ata Out (Q)

t

ADS

t

AS

t

CES

t

t

CL

CH

t

ADH

t

t

ADH

ADS

t

AH

A1

t

WES

t

CEH

High-Z

A2 A3

t

WEH

t

t

ADVH

ADVS

ADV
suspends
burst.

t

t

t

CLZ

t

CO

Single READ BURST READ

OEHZ

Q(A1)

OEV

t

OELZ

t

CO

t

DOH

Q(A2) Q(A2 + 1) Q(A2 + 2)

Burst continued with
new base address

Deselect
cycle

t

CHZ

Q(A2) Q(A2 + 1)Q(A2 + 3)

Burst wraps around
to its initial state

DON’T CARE

UNDEFINED

Note:

16.On this diagram, when CE

is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 38-05666 Rev. *B Page 10 of 15

[+] Feedback

Switching Waveforms (continued)

D

Write Cycle Timing

[16, 17]

t

CYC

CY7C1215H

CLK

ADSP

ADSC

ADDRESS

BWE,

BW[A :D]

GW

CE

t

t

CL

CH

t

t

ADH

ADS

t

ADS

t

t

AH

AS

A1

Byte write signals are
ignored for first cycle when
ADSP initiates burst

t

t

CEH

CES

t

ADH

ADSC extends burst

A2 A3

t

t

WEH

WES

t

ADS

t

ADH

t

WES

t

ADVS

t

WEH

t

ADVH

ADV

ADV suspends burst

OE

t

t

DH

DS

Data In (D)

ata Out (Q)

Note:

17.

Full width Write can be initiated by either GW

High-Z

BURST READ BURST WRITE

t

OEHZ

D(A1)

Single WRITE

LOW; or by GW HIGH, BWE LOW and BW

D(A2) D(A2 + 1) D(A2 + 1)

DON’T CARE

UNDEFINED

[A:D]

LOW

D(A2 + 2)

.

D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)

Extended BURST WRITE

Document #: 38-05666 Rev. *B Page 11 of 15

[+] Feedback

Switching Waveforms (continued)

D

Read/Write Cycle Timing

[16, 18, 19]

t

CYC

CY7C1215H

CLK

ADSP

ADSC

ADDRESS

BWE,

BW[A:D]

CE

ADV

OE

Data In (D)

t

t

CL

CH

t

t

ADH

ADS

t

t

AH

AS

High-Z

t

CES

A2

t

CEH

t

CO

t

CLZ

t

OEHZ

t

WES

t

DS

A3

D(A3)

t

t

DH

A1

A4 A5 A6

WEH

t

OELZ

D(A5) D(A6)

ata Out (Q)

High-Z

Q(A2)Q(A1)

Single WRITE

DON’T CARE UNDEFINED

Q(A4) Q(A4+1) Q(A4+2)

BURST READBack-to-Back READs

Q(A4+3)

Back-to-Back

WRITEs

Notes:

18.The data bus (Q) remains in High-Z following a Write cycle unless an ADSP

19.GW

is HIGH.

, ADSC, or ADV cycle is performed.

Document #: 38-05666 Rev. *B Page 12 of 15

[+] Feedback

Switching Waveforms (continued)

A

CLK

[20, 21]

t

ZZ

ZZ Mode Timing

CY7C1215H

t

ZZREC

I

SUPPLY

LL INPUTS

ZZ

t

ZZI

I

DDZZ

t

RZZI

DESELECT or READ Only

(except ZZ)

Outputs (Q)

High-Z

DON’T CARE

Notes:

20.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

21.DQs are in High-Z when exiting ZZ sleep mode.

Document #: 38-05666 Rev. *B Page 13 of 15

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CY7C1215H

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

Speed

(MHz) Ordering Code

100 CY7C1215H-100AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1215H-100AXI Industrial

133 CY7C1215H-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial

CY7C1215H-133AXI Industrial

Package Diagram

visit www.cypress.com for actual products offered.

Package
Diagram Package Type

100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)

16.00±0.20

14.00±0.10

100

1

81

80

0.30±0.08

Operating

Range

1.40±0.05

20.00±0.10

22.00±0.20

GAUGE PLANE

R 0.08 MIN.

0.20 MAX.

0.25

0°-7°

0.60±0.15

1.00 REF.

30

31 50

0° MIN.

R 0.08 MIN.

0.20 MAX.

0.20 MIN.

A

DETAIL

0.65
TYP.

51

STAND-OFF

0.05 MIN.

0.15 MAX.

SEATING PLANE

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3. DIMENSIONS IN MILLIMETERS

12°±1°

(8X)

SEE DETAIL

0.20 MAX.

1.60 MAX.

0.10

51-85050-*B

i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark
of IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders.

A

Document #: 38-05666 Rev. *B Page 14 of 15

© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change withou t n oti ce. C ypr ess S emi con duct or Corpo ration assu mes no resp onsib ility for the u se
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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CY7C1215H

Document History Page

Document Title: CY7C1215H 1-Mbit (32K x 32) Pipelined Sync SRAM
Document Number: 38-05666

REV. ECN NO. Issue Date

** 343896 See ECN PCI New Data Sheet

*A 430678 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from

*B 481916 See ECN VKN Converted from Preliminary to Final.

Orig. of

Change Description of Change

“3901 North First Street” to “198 Champion Court”
Added 2.5VI/O option
Changed Three-State to Tri-State
Included Maximum Ratings for V
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

relative to GND

DDQ

Electrical Characteristics Table
Modified test condition from V
Replaced Package Name column with Package Diagram in the Ordering

IH

< V

DD to VIH

< V

Information table

Updated the Ordering Information table.

DD

Document #: 38-05666 Rev. *B Page 15 of 15

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