CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
18-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency)
Features
Note
1. The QDR consortium specification for V
DDQ
is 1.5V + 0.1V . The Cyp ress QDR devices exceed th e QDR consorti um specifi catio n and ar e capab le of support ing V
DDQ
= 1.4V to V
DD
.
Functional Description
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 300 MHz to 400 MHz clock for high bandwidth
■ 4-word burst to reduce address bus frequency
■ Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 800 MHz) at 400 MHz
■ Read latency of 2.5 clock cycles
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate port selects for depth expansion
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ Available in x8, x9, x18, and x36 configurations
■ Full data coherency providing most current data
■ Core V
■ Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ Variable drive HSTL output buffers
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
= 1.8V ± 0.1V; IO V
DD
= 1.4V to V
DDQ
DD
[1]
The CY7C1161V18, CY7C1176V18, CY7C1163V18, and
CY7C1165V18 are 1.8V Synchronous Pipelined SRAMs
equipped with QDR™-II+ architecture. QDR-II+ architecture
consists of two separate ports to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR-II+ architecture has separate data inputs and
data outputs to completely eliminate the need to turn around the
data bus that is required with common IO devices. Each port can
be accessed through a common address bus. Addresses for
read and write addresses are latched onto alternate rising edges
of the input (K) clock. Accesses to the QDR-II+ read and write
ports are completely independent of one another. In order to
maximize data throughput, both read and write ports are
equipped with Double Data Rate (DDR) interfaces. Each
address location is associated with four 8-bit words
(CY7C1161V18), 9-bit words (CY7C1176V18), 18-bit words
(CY7C1163V18), or 36-bit words (CY7C1165V18) that burst
sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input
clocks K and K
, memory bandwidth is maximized while simpli-
fying system design by eliminating bus turnarounds.
Depth expansion is accomplished with port selects for each port.
Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K
registers controlled by the or K or K
input clocks. All data outputs pass through output
input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Configurations
With cycle read latency of 2.5 cycles:
CY7C1161V18 – 2M x 8
CY7C1176V18 – 2M x 9
CY7C1163V18 – 1M x 18
CY7C1165V18 – 512K x 36
Selection Guide
Description 400 MHz 375 MHz 333 MHz 300 MHz Unit
Maximum Operating Frequency 400 375 333 300 MHz
Maximum Operating Current 1080 1020 920 850 mA
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-06582 Rev. *D Revised March 06, 2008
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CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Logic Block Diagram (CY7C1161V18)
512K x 8 Array
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
D
[7:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q
[7:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
16
19
8
32
8
NWS
[1:0]
V
REF
Write Add. Decode
Write
Reg
16
A
(18:0)
19
512K x 8 Array
512K x 8 Array
512K x 8 Array
Write
Reg
Write
Reg
Write
Reg
8
CQ
CQ
DOFF
QVLD
512K x 9 Array
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
D
[8:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q
[8:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
19
9
36
9
BWS
[0]
V
REF
Write Add. Decode
Write
Reg
18
A
(18:0)
19
512K x 9 Array
512K x 9 Array
512K x 9 Array
Write
Reg
Write
Reg
Write
Reg
9
CQ
CQ
DOFF
QVLD
Logic Block Diagram (CY7C1176V18)
Document Number: 001-06582 Rev. *D Page 2 of 29
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CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Logic Block Diagram (CY7C1163V18)
256K x 18 Array
CLK
A
(17:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q
[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
18
18
72
18
BWS
[1:0]
V
REF
Write Add. Decode
Write
Reg
36
A
(17:0)
18
256K x 18 Array
256K x 18 Array
256K x 18 Array
Write
Reg
Write
Reg
Write
Reg
18
CQ
CQ
DOFF
QVLD
128K x 36 Array
CLK
A
(16:0)
Gen.
K
K
Control
Logic
Address
Register
D
[35:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q
[35:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
72
17
36
144
36
BWS
[3:0]
V
REF
Write Add. Decode
Write
Reg
72
A
(16:0)
17
128K x 36 Array
128K x 36 Array
128K x 36 Array
Write
Reg
Write
Reg
Write
Reg
36
CQ
CQ
DOFF
QVLD
Logic Block Diagram (CY7C1165V18)
Document Number: 001-06582 Rev. *D Page 3 of 29
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CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Pin Configurations
CY7C1161V18 (2M x 8)
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
23
4
5
6
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
NC/72M A
NWS
1
K
WPS
NC/144M
NC NC
NC
NC
NC
TDO
NC
NC
D5
NC
NC
NC
TCK
NC
NC
A NC/288M K NWS
0
V
SS
ANCA
NC V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
Q4
NC
V
DDQ
NC
NC
NC
NC
Q7
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
Q5 V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
ANC
V
SS
A
A
A
D4 V
SS
NC V
SS
NC
NC
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
QVLD
NC
Q6
NC
D7
D6
V
DD
A
8
91011
NC
ANC/36M
RPS
CQ
A NC NC Q3
V
SS
NC NC D3
NC
V
SS
NC
Q2
NC
NC
NC
V
REF
NC
NC
V
DDQ
NC
V
DDQ
NC NC
V
DDQ
V
DDQ
V
DDQ
D1V
DDQ
NC
Q1
NC
V
DDQ
V
DDQ
NC
V
SS
NC D0
NC
TDITMS
V
SS
A
NC
A
NC
D2
NC
ZQ
NC
Q0
NC
NC
NC
NC
A
NC/144M
CY7C1176V18 (2M x 9)
23
4
5
6
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
NC/72M A NC K
WPS NC/144M
NC NC
NC
NC
NC
TDO
NC
NC
D6
NC
NC
NC
TCK
NC
NC
A NC/288M K BWS
0
V
SS
ANCA
NC V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
Q5
NC
V
DDQ
NC
NC
NC
NC
Q8
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
Q6 V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
ANC
V
SS
A
A
A
D5 V
SS
NC V
SS
NC
NC
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
QVLD
NC
Q7
NC
D8
D7
V
DD
A
8
91011
Q0
ANC/36MRPS
CQ
A
NC
NC Q4
V
SS
NC NC D4
NC
V
SS
NC
Q3
NC
NC
NC
V
REF
NC
NC
V
DDQ
NC
V
DDQ
NC NC
V
DDQ
V
DDQ
V
DDQ
D2V
DDQ
NC
Q2
NC
V
DDQ
V
DDQ
NC
V
SS
NC D1
NC
TDITMS
V
SS
A
NC
A
NC
D3
NC
ZQ
NC
Q1
NC
NC
D0
NC
A
NC
NC
Document Number: 001-06582 Rev. *D Page 4 of 29
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CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Pin Configurations (continued)
CY7C1163V18 (1M x 18)
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
23
4
567
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
NC/144M NC/36M BWS
1
KWPS NC/288M
Q9 D9
NC
NC
NC
TDO
NC
NC
D13
NC
NC
NC
TCK
NC
D10
A NC K BWS
0
V
SS
ANCA
Q10 V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
Q11
D12
V
DDQ
D14
Q14
D16
Q16
Q17
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
Q13 V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
A
V
SS
A
A
A
D11 V
SS
NC V
SS
Q12
NC
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
QVLD
NC
Q15
NC
D17
D15
V
DD
A
8
91011
Q0
ANC/72MRPS
CQ
A NC NC Q8
V
SS
NC Q7 D8
NC
V
SS
NC
Q6
D5
NC
NC
V
REF
NC
Q3
V
DDQ
NC
V
DDQ
NC Q5
V
DDQ
V
DDQ
V
DDQ
D4V
DDQ
NC
Q4
NC
V
DDQ
V
DDQ
NC
V
SS
NC D2
NC
TDITMS
V
SS
A
NC
A
D7
D6
NC
ZQ
D3
Q2
D1
Q1
D0
NC
A
NC
CY7C1165V18 (512K x 36)
23
456
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
Q27
D27
D28
D34
DOFF
Q33
NC/288M NC/72M
BWS
2
KWPS BWS
1
Q18
D18
Q30
D31
D33
TDO
Q28
D29
D22
D32
Q34
Q31
TCK
D35
D19
A
BWS
3
K
BWS
0
V
SS
ANCA
Q19 V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
Q20
D21
V
DDQ
D23
Q23
D25
Q25
Q26
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
Q22 V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
A
NC
V
SS
A
A
A
D20 V
SS
Q29 V
SS
Q21
D30
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
QVLD
Q32
Q24
Q35
D26
D24
V
DD
A
891011
Q0
NC/36M
NC/144M
RPS
CQ
A D17
Q17
Q8
V
SS
D16 Q7 D8
Q16
V
SS
D15
Q6
D5
D9
Q14
V
REF
Q11
Q3
V
DDQ
Q15
V
DDQ
D14 Q5
V
DDQ
V
DDQ
V
DDQ
D4V
DDQ
D12
Q4
Q12
V
DDQ
V
DDQ
D11
V
SS
D10 D2
Q10
TDITMS
V
SS
A
Q9
A
D7
D6
D13
ZQ
D3
Q2
D1
Q1
D0
Q13
A
Document Number: 001-06582 Rev. *D Page 5 of 29
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CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Pin Definitions
Pin Name IO Pin Description
D
[x:0]
Input-
Synchronous
WPS Input-
Synchronous
, BWS1,
, Input-
1
Synchronous
Input-
Synchronous
3
NWS0, NWS
BWS
0
BWS2, BWS
A Input-
Synchronous
Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
CY7C1 161V18−D
CY7C1 176V18−D
CY7C1 163V18−D
CY7C1 165V18−D
[7:0]
[8:0]
[17:0]
[35:0]
Write Port Select − Active LOW . Sampled on the rising edge of the K clock. When asserted active,
a write operation is initiated. Deasserting deselects the write port. Deselecting the write port causes
D
to be ignored.
[x:0]
Nibble Write Select 0, 1 − Active LOW (CY7C1161V18 Only). Sampled on the rising edge of the
K and K
controls D
All the nibble write selects are sampled on the same edge as the data. Deselecting a nibble write
clocks during Write operations. Used to select the nibble that is written into the device. NWS0
and NWS1 controls D
[3:0]
[7:4]
.
select causes the corresponding nibble of data to be ignored and not written into the device.
Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks
during write operations. Used to select the byte that is written into the device during the current portion
of the write operation. Bytes not written remain unaltered.
CY7C1 176V18 − BWS
CY7C1 163V18 − BWS0 controls D
CY7C1 165V18 − BWS0 controls D
controls D
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
[35:27].
controls D
0
[8:0].
and BWS1 controls D
[8:0]
, BWS1 controls D
[8:0]
causes the corresponding byte of data to be ignored and not written into the device.
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.
These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1161V18, 2M x 9 (4 arrays each of 512K
x 9) for CY7C1176V18, 1M x 18 (4 arrays each of 256K x 18) for CY7C1163V18, and 512K x 36 (4
arrays each of 128K x 36) for CY7C1165V18. Therefore, only 19 address inputs are needed to access
the entire memory array of CY7C1161V18 and CY7C1 176V18, 18 address inputs for CY7C1 163V18,
and 17 address inputs for CY7C1165V18. These inputs are ignored when the appropriate port is
deselected.
[17:9]..
, BWS2 controls D
[17:9]
[26:18],
and BWS3
Q
[x:0]
RPS Input-
Outputs-
Synchronous
Synchronous
Data Output Signals. These pins drive out the requested data during a read operation. Valid data
is driven out on the rising edge of both the K and K
in single clock mode. When the read port is deselected, Q
CY7C1 161V18 − Q
CY7C1 176V18 − Q
CY7C1 163V18 − Q
CY7C1 165V18 − Q
[7:0]
[8:0]
[17:0]
[35:0]
.
.
.
.
clocks during read operations or K and K when
are automatically tri-stated.
[x:0]
Read Port Select − Active LOW . Sampled on the rising edge of positive input clock (K). When active,
a read operation is initiated. Deasserting causes the read port to be deselected. When deselected,
the pending access is enabled to complete and the output drivers are automatically tri-stated following
the next rising edge of the K clock. Each read access consists of a burst of four sequential transfers.
QVLD Valid Output
Valid Output Indicator. Indicates valid output data. QVLD is edge-aligned with CQ and CQ.
Indicator
K Input-
Clock
K
InputClock
Positive Input Clock Input. Rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
edge of K.
when in single clock mode. All accesses are initiated on the rising
[x:0]
Negative Input Clock Input. K is used to capture synchronous inputs presented to the device and
to drive out data through Q
when in single clock mode.
[x:0]
CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
clock (K) of the QDR-II+. The timings for the echo clocks are shown in “Switching Characteristics”
on page 23.
Document Number: 001-06582 Rev. *D Page 6 of 29
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CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Pin Definitions (continued)
Pin Name IO Pin Description
CQ
ZQ Input Output Impedance Matching Input. Used to tune the device outputs to the system data bus
DOFF
TDO Output TDO for JTAG.
TCK Input TCK Pin for JTAG.
TDI Input TDI Pin for JTAG.
TMS Input TMS Pin for JTAG.
NC N/A Not Connected to the Die. Can be tied to any voltage level.
NC/36M N/A Not Connected to the Die. Can be tied to any voltage level.
NC/72M N/A Not Connected to the Die. Can be tied to any voltage level.
NC/144M N/A Not Connected to the Die. Can be tied to any voltage level.
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
clock (K
on page 23.
impedance. CQ, CQ
connected between ZQ and ground. Alternatively, this pin is connected directly to V
enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
Input DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The
timings in the DLL turned-off operation are different from those listed in this data sheet. For normal
operation, this pin is connected to a pull up through a 10 KΩ or less pull up resistor. The device
behaves in QDR-I mode when the DLL is turned off. In this mode, the device operates at a frequency
of up to 167 MHz with QDR-I timing.
) of the QDR-II+. The timings for the echo clocks are shown in “Switching Characteristics”
and Q
output impedance are set to 0.2 x RQ, where RQ is a resistor
[x:0]
DDQ
, which
NC/288M N/A Not Connected to the Die. Can be tied to any voltage level.
V
V
V
V
REF
DD
SS
DDQ
Input-
Reference
Power Supply Power Supply Inputs to the Core of the Device.
Ground Ground for the Device.
Power Supply Power Supply Inputs for the Outputs of the Device.
Reference Volt age Input. Static input used to set the reference level for HSTL inputs, outputs, and
AC measurement points.
Document Number: 001-06582 Rev. *D Page 7 of 29
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CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Functional Overview
The CY7C1161V18, CY7C1176V18, CY7C1163V18, and
CY7C1165V18 are synchronous pipelined burst SRAMs
equipped with both a read port and a write port. The read port is
dedicated to read operations and the write port is dedicated to
write operations. Data flows into the SRAM through the write port
and out through the read port. These devices multiplex the
address inputs in order to minimize the number of address pins
required. By having separate read and write ports, the QDR-II+
completely eliminates the need to “turn-around” the data bus. It
avoids any possible data contention, thereby , simplify ing system
design. Each access consists of four 8-bit data transfers in the
case of CY7C1161V18, four 9-bit data transfers in the case of
CY7C1176V18, four 18-bit data transfers in the case of
CY7C1163V18, and four 36-bit data transfers in the case of
CY7C1165V18 in two clock cycles.
Accesses for both ports are initiated on the positive input clock
(K). All synchronous input and output timings are referenced to
the rising edge of the Input clocks (K/K
All synchronous data inputs (D
controlled by the input clocks (K and K
outputs (Q
rising edge of the Input clocks (K and K
) pass through output registers controlled by the
[x:0]
[x:0]
All synchronous control (RPS, WPS, BWS
through input registers controlled by the rising edge of the input
clocks (K and K).
CY7C1163V18 is described in the following sections. The same
basic descriptions apply to CY7C1161V18, CY7C1176V18, and
CY7C1165V18.
Read Operations
The CY7C1163V18 is organized internally as four arrays of 256K
x 18. Accesses are completed in a burst of four sequential 18-bit
data words. Read operations are initiated by asserting RPS
active at the rising edge of the positive input clock (K). The
address presented to address inputs are stored in the Read
address register. Following the next two K clock rises, the corresponding lowest order 18-bit word of data is driven onto the
using K as the output timing reference. On the subse-
Q
[17:0]
quent rising edge of K, the next 18-bit data word is driven onto
the Q
have been driven out onto Q
0.45 ns from the rising edge of the Input clock K or K
maintain the internal logic, each read access must be allowed to
complete. Each read access consists of four 18-bit data words
and takes two clock cycles to complete. Therefore, read
accesses to the device cannot be initiated on two consecutive K
clock rises. The internal logic of the device ignores the second
read request. Read accesses can be initiated on every other K
clock rise. Doing so pipelines the data flow such that data is
transferred out of the device on every rising edge of the input
clocks K and K
When the read port is deselected, the CY7C1163V18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tri-states the outputs following the next
rising edge of the negative input clock (K
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
. This process continues until all four 18-bit data words
[17:0]
[17:0]
.
).
) pass through input registers
). All synchronous data
) also.
) inputs pass
[x:0]
. The requested data is valid
. In order to
). This allows for a
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the following K
clock rise, the data presented to D
the lower 18-bit write data register, provided BWS
asserted active. On the subsequent rising edge of the negative
input clock (K), the information presented to D
into the write data register, provided BWS
active. This process continues for one more cycle until four 18-bit
is latched and stored into
[17:0]
[1:0]
[1:0]
is also stored
[17:0]
are both asserted
are both
words (a total of 72 bits) of data are stored in the SRAM. The 72
bits of data are then written into the memory array at the specified
location. Therefore, write accesses to the device cannot be
initiated on two consecutive K clock rises. The inte rnal logic of
the device ignores the second write request. Write accesses are
initiated on every other rising edge of the positive input clock (K).
Doing so pipelines the data flow such that 18 bits of data can be
transferred into the device on every rising edge of the input
clocks (K and K
).
When deselected, the write port ignores all inputs after the
pending write operations are completed.
Byte Write Operations
Byte write operations are supported by the CY7C1163V18. A
write operation is initiated as described in the Write Operations
section above. The bytes that are written are determined by
BWS
and BWS1, which are sampled with each set of 18-bit data
0
words. Asserting the appropriate byte write select input during
the data portion of a write enables the data being presented to
be latched and written into the device. Deasserting the byte write
select input during the data portion of a write allows the data
stored in the device for that byte to remain unaltered. This feature
is used to simplify read, modify, and write operations to a byte
write operation.
Concurrent Transactions
The read and write ports on the CY7C1163V18 operate
completely independent of one another. Because each port
latches the address inputs on different clock edges, the user can
read or write to any location, regardless of the transaction on the
other port. If the ports access the same location when a read
follows a write in successive clock cycles, the SRAM delivers the
most recent information associated with the specified address
location. This includes forwarding data from a write cycle initiated
on the previous K clock rise.
Read accesses and write access are scheduled such that one
transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on the
previous state of the SRAM. If both ports are deselected, the
read port takes priority . If a read is initiated on the previous cycle,
the write port assumes priority (because read operations cannot
be initiated on consecutive cycles). If a write was initiated on the
previous cycle, the read port assumes priority (because write
operations cannot be initiated on consecutive cycles). Therefore,
asserting both port selects active from a deselected state results
in alternating read or write operations initiated, with the first
access being a read.
Document Number: 001-06582 Rev. *D Page 8 of 29
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CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Depth Expansion
The CY7C1163V18 has a port select input for each port. This
enables easy depth expansion. Both port selects are only
sampled on the rising edge of the positive input clock (K). Each
port select input can deselect the specified port. Deselecting a
port does not affect the other port. All pending transactions (read
and write) are completed before the device is deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V
driver impedance. The value of RQ must be 5X the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
to enable the SRAM to adjust its output
SS
, with V
=1.5V. The
DDQ
Echo Clocks
Echo clocks are provided on the QDR-II+ to simplify data capture
on high speed systems. Two echo clocks are generated by the
QDR-II+. CQ is referenced with respect to K and CQ is referenced with respect to K
synchronized to the input clock of the QDR-II+. The timings for
the echo clocks are shown in the AC timing table.
. These are free running clocks and are
Valid Data Indicator (QVLD)
QVLD is provided on the QDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the QDR-II+ device
along with data output. This signal is also edge-aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF
pin. When the DLL is turned off, the device behaves in
QDR-I mode (with 1.0 cycle latency and a longer access time).
For more information, refer to the application note, “DLL Consid-
erations in QDRII/DDRII/QDRII+/DDRII+.” The DLL can also be
reset by slowing or stopping the input clocks K and K
minimum of 30 ns. However, it is not necessary for the DLL to be
reset in order to lock to the desired frequency. During power up
when the DOFF
of stable clock.
is tied HIGH, the DLL is locked after 2048 cycles
for a
Document Number: 001-06582 Rev. *D Page 9 of 29
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CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Application Example
BUS MASTER
(CPU or ASIC)
DATA IN
DATA OUT
Address
Source K
Source K
Vt
Vt
Vt
R
R
CLKIN/CLKIN
D
A
K
SRAM #4
RQ = 250ohms
ZQ
CQ/CQ
Q
K
RPS
WPS
BWS
D
A
K
SRAM #1
RQ = 250ohms
ZQ
CQ/CQ
Q
K
RPS
WPS
BWS
RPS
WPS
BWS
R = 50ohms, Vt = V /2
DDQ
R
Notes
2. The above application shows four QDR-II+ being used.
3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
↑ represents rising edge.
4. Device powers up deselected and the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.
6. “t” represents the cycle at which a read or write operation is started. t + 1, t + 2, t + 3 and t + 4 are the first, second, third, and fourth clock cycles, resp ectively succeeding
the “t” clock cycle.
7. Data inputs are registered at K and K
rising edges. Data outputs are delivered on K and K rising edges.
8. It is recommended that K = K
= HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line ch arging symmetrically.
9. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
10.This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
second read or write request.
Figure 1 shows four QDR-II+ used in an application.
Figure 1. Application Example
Truth Table
The truth table for the CY7C1161V18, CY7C117 6V18, CY7C1163V18, and CY7C1165V18 follows.
[3, 4, 5, 6, 7, 8]
Operation K RPS WPS DQ DQ DQ DQ
Write Cycle: Load
L-H H
[9]L[10]
D(A) at K(t + 1) ↑ D(A + 1) at K(t + 1) ↑ D(A + 2) at K(t + 2) ↑ D(A + 3) at K(t + 2) ↑
address on rising edge of
K; input write data on two
consecutive K and K
rising
edges.
Read Cycle (2.5 Cycle
L-H L
[10]
X Q(A) at K(t + 2) ↑ Q(A + 1) at K(t + 3) ↑ Q(A + 2) at K(t + 3)↑ Q(A + 3) at K(t + 4) ↑
Latency): Load address on
rising edge of K; wait one
and a half cycle; read data
on two consecutive K
and
K rising edges.
NOP: No operation. L-H H H D = X
Q = High Z
D = X
Q = High Z
D = X
Q = High Z
D = X
Q = High Z
Standby: Clock stopped. Stopped X X Previous State Previous State Previous State Previous State
Document Number: 001-06582 Rev. *D Page 10 of 29
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CY7C1163V18, CY7C1165V18
Write Cycle Descriptions
Note
11.Is based upon a Write cycle was initiated per the Write Cycle Description Truth Table. NWS
0
, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different
portions of a Write cycle, as long as the setup and hold requirement s are achieved.
The write cycle descriptions of CY7C1161V18 and CY7C1163V18 follow.
[3, 11]
BWS0/
NWS
0
BWS1/
NWS
K
1
K
Comments
L L L–H – During the data portion of a write sequence:
CY7C1161V18 − both nibbles (D
CY7C1163V18 − both bytes (D
) are written into the device.
[7:0]
) are written into the device.
[17:0]
L L – L-H During the data portion of a write sequence:
CY7C1161V18 − both nibbles (D
CY7C1163V18 − both bytes (D
) are written into the device.
[7:0]
) are written into the device.
[17:0]
L H L–H – During the data portion of a write sequence:
CY7C1161V18 − only the lower nibble (D
CY7C1163V18 − only the lower byte (D
) is written into the device, D
[3:0]
) is written into the device, D
[8:0]
L H – L–H During the data portion of a write sequence:
CY7C1161V18 − only the lower nibble (D
CY7C1163V18 − only the lower byte (D
) is written into the device, D
[3:0]
) is written into the device, D
[8:0]
H L L–H – During the data portion of a write sequence:
CY7C1161V18 − only the upper nibble (D
CY7C1163V18 − only the upper byte (D
) is written into the device, D
[7:4]
) is written into the device, D
[17:9]
H L – L–H During the data portion of a write sequence:
CY7C1161V18 − only the upper nibble (D
CY7C1163V18 − only the upper byte (D
) is written into the device, D
[7:4]
) is written into the device, D
[17:9]
H H L–H – No data is written into the device during this portion of a write operation.
H H – L–H No data is written into the device during this portion of a write operation.
remains unaltered.
[7:4]
remains unaltered.
[17:9]
remains unaltered.
[7:4]
remains unaltered.
[17:9]
remains unaltered.
[3:0]
remains unaltered.
[8:0]
remains unaltered.
[3:0]
remains unaltered.
[8:0]
The write cycle operation of CY7C1176V18 follows.
BWS
K K Comments
0
L L–H – During the data portion of a write sequence, the single byte (D
L – L–H During the data portion of a write sequence, the single byte (D
[3, 11]
[8:0]
[8:0]
H L–H – No data is written into the device during this portion of a write operation.
H – L–H No data is written into the device during this portion of a write operation.
) is written into the device.
) is written into the device.
Document Number: 001-06582 Rev. *D Page 11 of 29
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CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
The write cycle descriptions of CY7C1165V18 follows.
[3, 11]
BWS0BWS1BWS2BWS3K K Comments
LLLLL–H–During the data portion of a write sequence, all four bytes (D
the device.
LLLL–L–HDuring the data portion of a write sequence, all four bytes (D
the device.
L H H H L–H – During the data portion of a write sequence, only the lower byte (D
into the device. D
remains unaltered.
[35:9]
L H H H – L–H During the data portion of a write sequence, only the lower byte (D
into the device. D
remains unaltered.
[35:9]
H L H H L–H – During the data portion of a write sequence, only the byte (D
the device. D
[8:0]
and D
remains unaltered.
[35:18]
H L H H – L–H During the data portion of a write sequence, only the byte (D
the device. D
[8:0]
and D
remains unaltered.
[35:18]
H H L H L–H – During the data portion of a write sequence, only the byte (D
the device. D
[17:0]
and D
remains unaltered.
[35:27]
H H L H – L–H During the data portion of a write sequence, only the byte (D
the device. D
[17:0]
and D
remains unaltered.
[35:27]
H H H L L–H – During the data portion of a write sequence, only the byte (D
the device. D
remains unaltered.
[26:0]
H H H L – L–H During the data portion of a write sequence, only the byte (D
the device. D
remains unaltered.
[26:0]
) are written into
[35:0]
) are written into
[35:0]
[8:0]
[8:0]
) is written into
[17:9]
) is written into
[17:9]
) is written into
[26:18]
) is written into
[26:18]
) is written into
[35:27]
) is written into
[35:27]
) is written
) is written
HHHHL–H–No data is written into the device during this portion of a write operation.
HHHH–L–HNo data is written into the device during this portion of a write operation.
Document Number: 001-06582 Rev. *D Page 12 of 29
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CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA p ackage. This part is fully compliant with
IEEE Standard 114 9.1-2001. The TAP operates using JEDEC
standard 1.8V IO logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively
be connected to V
unconnected. Upon power up, the device comes up in a reset
state which does not interfere with the operation of the device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this pin unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
Test Data In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the i nstructio n that
is loaded into the TAP instruction register. For information on
loading the instruction register, see “TAP Controller State
Diagram” on page 15 TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSb) on any register.
Test Data Out (TDO)
The TDO output pin is used to serially clock data out from the
registers. The output is active depending upon the curre nt state
of the TAP state machine, see “Instruction Codes” on page 18
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSb) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a high Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
enables data to be scanned into and out of the SRAM test
circuitry. Only one register is selected at a time through the
instruction registers. Data is serially loaded into the TDI pin on
the rising edge of TCK. Data outputs on the TDO pin on the falling
edge of TCK.
through a pull up resistor. TDO must be left
DD
Instruction Register
Three-bit instructions are serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins as shown in “TAP Controller Block Diagram” on
page 16. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture IR state, the two least
significant bits are loaded with a binary “01” pattern to allow fault
isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables data to be shifted through the SRAM
with minimal delay. The bypass register is set LOW (V
the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are also
included in the scan register to reserve pins for higher de nsity
devices.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can
be used to capture the contents of the Input and Output ring.
The “Boundary Scan Order” on page 19 show the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSb of the register is connected to
TDI and the LSb is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the “Identification Register Definitions”
on page 18.
SS
) when
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the “Instruction
Codes” on page 18. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described below.
Instructions are loaded into the TAP controller during the Shif t-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI a nd TDO pins. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
Document Number: 001-06582 Rev. *D Page 13 of 29
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CY7C1163V18, CY7C1165V18
IDCODE
The IDCODE instruction causes a vendor-specific 32-bit code to
be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and enable s
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction is
loaded into the instruction register upon power up or whenever
the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High Z state until the next command is given
during the Update IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a
snapshot of data on the inputs and output pins is captured in the
boundary scan register.
The user must be aware that the TAP controller clock only operates at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a
large difference in the clock frequencies, it is possible that during
the Capture-DR state, an input or output undergoes a transition.
The TAP then tries to capture a signal while in transition (metastable state). This does not harm the device but there is no guarantee as to the value that is captured. Repeatable results are not
possible.
To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal is stabilized long enough
to meet the TAP controller's capture setup plus hold times (t
and tCH). The SRAM clock input is not captured correctly if there
is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to
capture all other signals and simply ignore the value of the CK
and CK
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
captured in the boundary scan register.
CS
PRELOAD enables an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
before the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required—that is, while data captured
is shifted out, the preloaded data is shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller puts the
output bus into a tri-state mode.
The boundary scan register has a special bit located at bit 4 7.
When this scan cell, called the “extest output bus tri-state”, is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a High
Z condition.
This bit is set by entering the SAMPLE/PRELOAD or EXTEST
command, and then shifting the desired bit into that cell, during
the Shift-DR state. During Update-DR, the value loaded into that
shift register cell latches into the preload register. When the
EXTEST instruction is entered, this bit directly controls the output
Q-bus pins. Note that this bit is preset HIGH to enable the output
when the device is powered up, and also when the T AP controller
is in the Test Logic Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-06582 Rev. *D Page 14 of 29
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CY7C1163V18, CY7C1165V18
TAP Controller State Diagram
TEST-LOGIC
RESET
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
SELECT
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
1
0
1
1
0
1
0
1
0
0
0
1
1
1
0
1
0
1
0
0
0
1
0
1
1
0
1
0
0
1
1
0
Note
12.The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Figure 2. Tap Controller State Diagram
[12]
Document Number: 001-06582 Rev. *D Page 15 of 29
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CY7C1163V18, CY7C1165V18
TAP Controller Block Diagram
0
012..
29
3031
Boundary Scan Register
Identification Register
012..
.
.106
012
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TA P Controller
TDI
TDO
TCK
TMS
Notes
13.These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
14.Overshoot: V
IH
(AC) < V
DDQ
+ 0.35V (pulse width less than t
CYC
/2), Undershoot: VIL(AC) > −0.3V (pulse width less than t
CYC
/2)
15.All voltage referenced to ground.
Figure 3. Tap Controller Block Diagram
TAP Electrical Characteristics
The Tap Electrical Characteristics table over the operating range follows.
Parameter Description Test Conditions Min Max Unit
Output HIGH Voltage I
Output HIGH Voltage I
Output LOW Voltage IOL = 2.0 mA 0.4 V
Output LOW Voltage IOL = 100 μA0.2V
Input HIGH Voltage 0.65 VDDV
Input LOW Voltage –0.3 0.35 V
Input and Output Load Current GND ≤ VI ≤ V
V
V
V
V
V
V
I
OH1
OH2
OL1
OL2
IH
IL
X
[13, 14, 15]
= −2.0 mA 1.4 V
OH
= −100 μA1.6 V
OH
DD
+ 0.3 V
DD
DD
–5 5 μA
V
Document Number: 001-06582 Rev. *D Page 16 of 29
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CY7C1163V18, CY7C1165V18
TAP AC Switching Characteristics
t
TL
t
TH
(a)
TDO
C
L
= 20 pF
Z
0
= 50
Ω
GND
0.9V
50
Ω
1.8V
0V
ALL INPUT PULSES
0.9V
Test Clock
Test Mode Select
TCK
TMS
Test Data In
TDI
Test Data Out
t
TCYC
t
TMSH
t
TMSS
t
TDIS
t
TDIH
t
TDOV
t
TDOX
TDO
Notes
16.t
CS
and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
17.Test conditions are specified using the load in TAP AC test conditions. t
R/tF
= 1 ns.
The Tap AC Switching Characteristics over the operating range follows.
Parameter Description Min Max Unit
t
TCYC
t
TF
t
TH
t
TL
TCK Clock Cycle Time 50 ns
TCK Clock Frequency 20 MHz
TCK Clock HIGH 20 ns
TCK Clock LOW 20 ns
Setup Times
t
TMSS
t
TDIS
t
CS
TMS Setup to TCK Clock Rise 5 ns
TDI Setup to TCK Clock Rise 5 ns
Capture Setup to TCK Rise 5 ns
Hold Times
t
TMSH
t
TDIH
t
CH
TMS Hold after TCK Clock Rise 5 ns
TDI Hold after Clock Rise 5 ns
Capture Hold after Clock Rise 5 ns
Output Times
t
TDOV
t
TDOX
TCK Clock LOW to TDO Valid 10 ns
TCK Clock LOW to TDO Invalid 0 ns
[16, 17]
TAP Timing and Test Conditions
The Tap Timing and Test Conditions for the CY7C1161V18, CY7C1176V18, CY7C1163V18, and CY7C1165V18 follows.
[17]
Document Number: 001-06582 Rev. *D Page 17 of 29
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CY7C1163V18, CY7C1165V18
Identification Register Definitions
Instruction Field
Revision Number
(31:29)
Cypress Device ID
(28:12)
Cypress JEDEC ID
(11:1)
ID Register
Presence (0)
CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18
000 000 000 000 Version number.
11010010001000101 11010010001001101 11010010001010101 11010010001 100101 Defines the type of
00000110100 00000110100 00000110100 00000110100 Enables uni que
1 1 1 1 Indicates the
Value
Description
SRAM.
identification of
SRAM vendor.
presence of an ID
register.
Scan Register Sizes
Register Name Bit Size
Instruction 3
Bypass 1
ID 32
Boundary Scan 107
Instruction Codes
Instruction Code Description
EXTEST 000 Captures the input and output ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI
SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the input and output ring contents. Places the boundary scan register
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect
and TDO. This operation does not affect SRAM operation.
TDI and TDO. This forces all SRAM output drivers to a High Z state.
between TDI and TDO. This operation does not affect the SRAM operation.
SRAM operation.
Document Number: 001-06582 Rev. *D Page 18 of 29
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CY7C1163V18, CY7C1165V18
Boundary Scan Order
Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID
0 6R 27 11H 54 7B 81 3G
1 6P 28 10G 55 6B 82 2G
26N 299G 566A 831J
3 7P 30 11F 57 5B 84 2J
4 7N 31 11G 58 5A 85 3K
57R 329F 594A 863J
6 8R 33 10F 60 5C 87 2K
7 8P 34 11E 61 4B 88 1K
8 9R 35 10E 62 3A 89 2L
9 11P 36 10D 63 1H 90 3L
10 10P 37 9E 64 1A 91 1M
11 10N 38 10C 65 2B 92 1L
12 9P 39 11D 66 3B 93 3N
13 10M 40 9C 67 1C 94 3M
1411N 419D 681B 951N
15 9M 42 11B 69 3D 96 2M
16 9N 43 11C 70 3C 97 3P
1711L 449B 711D 982N
18 11M 45 10B 72 2C 99 2P
19 9L 46 11A 73 3E 100 1P
20 10L 47 Internal 74 2D 101 3R
2111K 489A 752E 1024R
22 10K 49 8B 76 1E 103 4P
23 9J 50 7C 77 2F 104 5P
24 9K 51 6C 78 3F 105 5N
25 10J 52 8A 79 1G 106 5R
26 11J 53 7A 80 1F
Document Number: 001-06582 Rev. *D Page 19 of 29
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Power Up Sequence in QDR-II+ SRA
K
K
Fix HIGH (tie to V
DDQ
)
VDD/V
DDQ
DOFF
Clock Start (Clock Starts after VDD/V
DDQ
is Stable)
Unstable Clock > 2048 Stable Clock
Start Normal
Operation
~
~
VDD/V
DDQ
Stable (< + 0.1V DC per 50 ns)
During power up, when the DOFF is tied HIGH, the DLL gets
locked after 2048 cycles of stable clock. QDR-II+ SRAMs must
be powered up and initialized in a predefined manner to prevent
undefined operations.
Power Up Sequence
■ Apply power with DOFF tied HIGH (All other inputs can be
HIGH or LOW)
❐ Apply V
❐ Apply V
■ Provide stable power and clock (K, K) for 2048 cycles to lock
the DLL
before V
DD
before V
DDQ
DDQ
or at the same time as V
REF
REF
Power Up Waveforms
Figure 4. Power Up Waveforms
DLL Constraints
■ DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as t
■ The DLL functions at frequencies down to 120 MHz
■ If the input clock is unstable and the D LL is enabl ed, the n the
DLL locks onto an incorrect frequency, causing unstable SRAM
behavior. To avoid this, provide 2048 cycles stable clock to
relock to the desired clock frequency
~
~
KC Var
Document Number: 001-06582 Rev. *D Page 20 of 29
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Maximum Ratings
Notes
18.Power up: Is based upon a linear ramp from 0V to V
DD
(min) within 200 ms. During this time VIH < V
DD
and V
DDQ
< VDD.
19.Output are impedance controlled. I
OH
= −(V
DDQ
/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
20.Output are impedance controlled. I
OL
= (V
DDQ
/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
21.V
REF
(min) = 0.68V or 0.46V
DDQ
, whichever is larger, V
REF
(max) = 0.95V or 0.54V
DDQ
, whichever is smaller.
22.The operation current is calculated with 50% read cycle and 50% write cycle.
Exceeding maximum ratings may impair the useful life of the
device. User guidelines are not tested .
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with Power Applied. –55°C to + 125°C
Supply Voltage on VDD Relative to GND.......–0.5V to + 2.9V
Supply Voltage on V
DC Applied to Outputs in High Z ........–0.5V to V
DC Input Voltage
Relative to GND..... –0.5V to + V
DDQ
[14]
...............................–0.5V to VDD + 0.3V
DDQ
DD
+ 0.3V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V
Latch up Current.................................................... > 200 mA
Operating Range
Range
Temperature (TA) V
Commercial 0°C to +70°C 1.8 ± 0.1V 1.4V to
Industrial –40°C to +85°C
Ambient
DD
[18]
V
DDQ
V
DD
Electrical Characteristics
The DC Electrical Characteristics over the operating range follows.
Parameter Description Test Conditions Min Typ Max Unit
V
DD
V
DDQ
V
OH
V
OL
V
OH(LOW)
V
OL(LOW)
V
IH
V
IL
I
X
I
OZ
V
REF
[22]
I
DD
I
SB1
Power Supply Voltage 1.7 1.8 1.9 V
IO Supply Voltage 1.4 1.5 V
Output HIGH Voltage Note 19 V
Output LOW Voltage Note 20 V
Output HIGH Voltage I
= −0.1 mA, Nominal Impedance V
OH
Output LOW Voltage IOL = 0.1 mA, Nominal Impedance V
Input HIGH Voltage V
Input LOW Voltage –0.15 V
Input Leakage Current GND ≤ VI ≤ V
Output Leakage Current GND ≤ VI ≤ V
Input Reference Voltage
VDD Operating Supply V
Automatic Power Down
Current
[21]
Typical Value = 0.75V 0.68 0.75 0.95 V
= Max, I
DD
f = f
= 1/t
max
Max VDD,
Both Ports Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = f
= 1/t
max
Inputs Static
[15]
/2 – 0.12 V
DDQ
/2 – 0.12 V
DDQ
– 0.2 V
DDQ
SS
+ 0.1 V
REF
DDQ
Output Disabled −22μA
DDQ,
OUT
CYC
= 0 mA,
300 MHz 850 mA
333 MHz 920 mA
−22μA
/2 + 0.12 V
DDQ
/2 + 0.12 V
DDQ
0.2 V
DDQ
REF
375 MHz 1020 mA
400 MHz 1080 mA
300 MHz 250 mA
333 MHz 260 mA
CYC,
375 MHz 290 mA
400 MHz 300 mA
DD
DDQ
+ 0.15 V
– 0.1 V
[18]
V
V
AC Electrical Characteristics
Over the operating range follows.
Parameter Description Test Conditions Min Typ Max Unit
V
IH
V
IL
Document Number: 001-06582 Rev. *D Page 21 of 29
Input HIGH Voltage V
Input LOW Voltage –0.24 – V
[21]
+ 0.2 – V
REF
DDQ
REF
+ 0.24 V
– 0.2 V
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CY7C1163V18, CY7C1165V18
Capacitance
1.25V
0.25V
R = 50Ω
5pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
Device
R
L
= 50Ω
Z
0
= 50Ω
V
REF
= 0.75V
V
REF
= 0.75V
[23]
0.75V
Under
Test
0.75V
Device
Under
Test
OUTPUT
0.75V
V
REF
V
REF
OUTPUT
ZQ
ZQ
(a)
Slew Rate = 2 V/ns
RQ =
250
Ω
(b)
RQ =
250
Ω
Notes
23.Unless otherwise noted, test conditions are based upon signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, V
DDQ
= 1.5V , i nput
pulse levels of 0.25V to 1.25V, and output loading of the specified I
OL/IOH
and load capacitance shown in (a) of AC Test Loads.
Tested initially and after any design or process change that may affect these parameters.
Parameter Description Test Conditions Max Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
V
= 1.8V
C
CLK
C
O
Clock Input Capacitance 6 pF
Output Capacitance 7pF
V
DD
DDQ
= 1.5V
5pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter Description Test Conditions
Θ
Θ
Thermal Resistance
JA
(junction to ambient)
Thermal Resistance
JC
(junction to case)
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
165 FBGA
Package
17.2 °C/W
4.15 °C/W
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms
Unit
Document Number: 001-06582 Rev. *D Page 22 of 29
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Switching Characteristics
Notes
24.When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input t imings of th e frequency ra nge in which it is bei ng
operated and outputs data with the output timings of that fre quency range.
25.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied ab ove V
DD
minimum initially before a Read or Write operat ion ca n
be initiated.
26.These parameters are extrapolated from the input timing parameters (t
KHKH
– 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t
KC Var
) is already
included in the t
KHKH
). These parameters are only guaranteed by design and are not tested in production.
27.t
CHZ
, t
CLZ
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ± 100 mV from steady state voltage.
28.At any voltage and temperature t
CHZ
is less than t
CLZ
and t
CHZ
less than tCO.
29.t
QVLD
spec is applicable for both rising and falling edges of QVLD signal.
Over the operating range
[23, 24]
Cypress
Parameter
t
POWER
t
CYC
t
KH
t
KL
t
KHKH
Consortium
Parameter
t
KHKH
t
KHKL
t
KLKH
t
KHKH
Setup Times
t
SA
t
SC
t
SCDDR
t
SD
t
AVKH
t
IVKH
t
IVKH
t
DVKH
Hold Times
t
HA
t
HC
t
HCDDR
t
HD
t
KHAX
t
KHIX
t
KHIX
t
KHDX
Output Times
t
CO
t
DOH
t
CCQO
t
CQOH
t
CQD
t
CQDOHtCQHQX
t
CQH
t
CQHCQHtCQHCQH
t
CHZ
t
CLZ
t
QVLD
t
CHQV
t
CHQX
t
CHCQV
t
CHCQX
t
CQHQV
t
CQHCQL
t
CHQZ
t
CHQX1
t
QVLD
Description
VDD(Typical) to the First Access
[25]
400 MHz 375 MHz 333 MHz 300 MHz
Min Max Min Max Min Max Min Max
Unit
1–1–1–1–ms
K Clock Cycle Time 2.50 8.40 2.66 8.40 3.0 8.40 3.3 8.40 ns
Input Clock (K/K) HIGH 0.4–0.4–0.4–0.4–t
Input Clock (K/K) LOW 0.4–0.4–0.4–0.4–t
K Clock Rise to K Clock Rise
1.06–1.13–1.28–1.40– ns
CYC
CYC
(rising edge to rising edge)
Address Setup to K Clock Rise 0.4 – 0.4 – 0.4 – 0.4 – ns
Control Setup to K Clock Rise (RPS, WPS) 0.4–0.4–0.4–0.4– ns
Double Data Rate Control Setup to Clock (K, K)
Rise (BWS
D
[X:0]
, BWS
0
BWS2, BWS3)
1,
Setup to Clock (K/K) Rise 0.28–0.28–0.28–0.28– ns
0.28–0.28–0.28–0.28– ns
Address Hold after K Clock Rise 0.4 – 0.4 – 0.4 – 0.4 – ns
Control Hold after K Clock Rise (RPS, WPS) 0.4–0.4–0.4–0.4– ns
Double Data Rate Control Hold after Clock (K/K)
Rise (BWS
D
[X:0]
, BWS
0
BWS2, BWS3)
1,
Hold after Clock (K/K) Rise 0.28–0.28–0.28–0.28– ns
0.28–0.28–0.28–0.28– ns
K/K Clock Rise to Data Valid – 0.45 – 0.45 – 0.45 – 0.45 ns
Data Output Hold after Output K/K Clock Rise
–0.45 – –0.45 – –0.45 – –0.45 – ns
(Active to Active)
K/K Clock Rise to Echo Clock Valid – 0.45 – 0.45 – 0.45 – 0.45 ns
Echo Clock Hold after K/K Clock Rise –0.45 – –0.45 – –0.45 – –0.45 – ns
Echo Clock High to Data Valid – 0.2 0.2 0.2 0.2 ns
Echo Clock High to Data Invalid –0.2 – –0.2 – –0.2 – –0.2 – ns
Output Clock (CQ/CQ) HIGH
CQ Clock Rise to CQ Clock Rise
[26]
[26]
0.81–0.88–1.03–1.15– ns
0.81–0.88–1.03–1.15– ns
(rising edge to rising edge)
Clock (K/K) Rise to High Z (Active to High Z)
Clock (K/K) Rise to Low Z
Echo Clock High to QVLD Valid
[27, 28]
[29]
[27, 28]
–0.45–0.45–0.45–0.45ns
–0.45 – –0.45 – –0.45 – –0.45 – ns
–0.20 0.20 –0.20 0.20 –0.20 0.20 –0.20 0.20 ns
Document Number: 001-06582 Rev. *D Page 23 of 29
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Switching Characteristics
Note
30.Hold to >V
IH
or <VIL.
Over the operating range
[23, 24]
(continued)
Cypress
Parameter
Consortium
Parameter
DLL Timing
t
KC Var
t
KC lock
t
KC ResettKC Reset
t
KC Var
t
KC lock
Description
400 MHz 375 MHz 333 MHz 300 MHz
Min Max Min Max Min Max Min Max
Unit
Clock Phase Jitter – 0.20 – 0.20 – 0.20 – 0.20 ns
DLL Lock Time (K) 2048 – 2048 – 2048 – 2048 – Cycles
K Static to DLL Reset
[30]
30–30–30–30– ns
Document Number: 001-06582 Rev. *D Page 24 of 29
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Switching Waveforms
Z
Notes
31.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.
32.Outputs are disabled (High Z) one clock cycle after a NOP.
33.In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write dat a is forwarded immed iately as read result s. This note applies t o the whole diagram.
Read/Write/Deselect Sequence
Figure 6. Waveform for 2.5 Cycle Read Latency
[31, 32, 33]
RPS
WPS
A
D
QVLD
CQ
NOP
1
WRITE
23 4
READ
WRITE
NOPREAD
567
8
K
t
KH
t
KL
t
CYC
t
KHKH
K
t
t
SC
HC
A0 A1
tt
SA HA
t
SD
t
HD
t
QVLD
A2
D10
Q
(Read Latency = 2.5 Cycles)
t
CQH
t
CQHCQH
t
CQOH
t
CLZ
D11
t
CQOH
t
SC HC
A3
t
SD
D12
t
CO
Q00
t
CCQO
t
t
HD
D13
Q01
t
CCQO
D30
t
DOH
t
CQD
Q03
D31
D32 D33
t
CQDOH
Q20Q02 Q21
t
QVLD
Q22 Q23
t
CH
CQ
DON’T CARE UNDEFINED
Document Number: 001-06582 Rev. *D Page 25 of 29
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Ordering Information
Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com
for actual products offered.
Speed
(MHz) Ordering Code
400 CY7C1161V18-400BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial
CY7C1 176V18-400BZC
CY7C1 163V18-400BZC
CY7C1 165V18-400BZC
CY7C1 161V18-400BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1 176V18-400BZXC
CY7C1 163V18-400BZXC
CY7C1 165V18-400BZXC
CY7C1161V18-400BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial
CY7C1 176V18-400BZI
CY7C1 163V18-400BZI
CY7C1 165V18-400BZI
CY7C1 161V18-400BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1 176V18-400BZXI
CY7C1 163V18-400BZXI
CY7C1 165V18-400BZXI
375 CY7C1161V18-375BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial
CY7C1 176V18-375BZC
CY7C1 163V18-375BZC
CY7C1 165V18-375BZC
CY7C1 161V18-375BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1 176V18-375BZXC
CY7C1 163V18-375BZXC
CY7C1 165V18-375BZXC
CY7C1161V18-375BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial
CY7C1 176V18-375BZI
CY7C1 163V18-375BZI
CY7C1 165V18-375BZI
CY7C1 161V18-375BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1 176V18-375BZXI
CY7C1 163V18-375BZXI
CY7C1 165V18-375BZXI
Package
Diagram Package Type
Operating
Range
Document Number: 001-06582 Rev. *D Page 26 of 29
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CY7C1163V18, CY7C1165V18
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Contact your local sales representative or visit www.cypress.com
for actual products offered.
Speed
(MHz) Ordering Code
333 CY7C1161V18-333BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial
CY7C1 176V18-333BZC
CY7C1 163V18-333BZC
CY7C1 165V18-333BZC
CY7C1 161V18-333BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1 176V18-333BZXC
CY7C1 163V18-333BZXC
CY7C1 165V18-333BZXC
CY7C1161V18-333BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial
CY7C1 176V18-333BZI
CY7C1 163V18-333BZI
CY7C1 165V18-333BZI
CY7C1 161V18-333BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1 176V18-333BZXI
CY7C1 163V18-333BZXI
CY7C1 165V18-333BZXI
300 CY7C1161V18-300BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial
CY7C1 176V18-300BZC
CY7C1 163V18-300BZC
CY7C1 165V18-300BZC
CY7C1 161V18-300BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1 176V18-300BZXC
CY7C1 163V18-300BZXC
CY7C1 165V18-300BZXC
CY7C1161V18-300BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial
CY7C1 176V18-300BZI
CY7C1 163V18-300BZI
CY7C1 165V18-300BZI
CY7C1 161V18-300BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free
CY7C1 176V18-300BZXI
CY7C1 163V18-300BZXI
CY7C1 165V18-300BZXI
Package
Diagram Package Type
Operating
Range
Document Number: 001-06582 Rev. *D Page 27 of 29
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Package Diagram
A
1
PIN 1 CORNER
15.00±0.10
13.00±0.10
7.00
1.00
Ø0.50 (165X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.35±0.06
SEATING PLANE
0.53±0.05
0.25 C
0.15 C
PIN 1 CORNER
TOP VIEW
BOTTOM VIEW
2345678910
10.00
14.00
B
C
D
E
F
G
H
J
K
L
M
N
11
1110986754321
P
R
P
R
K
M
N
L
J
H
G
F
E
D
C
B
A
A
15.00±0.10
13.00±0.10
B
C
1.00
5.00
0.36
-0.06
+0.14
1.40 MAX.
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
NOTES :
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AC
51-85180-*A
Figure 7. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180
Document Number: 001-06582 Rev. *D Page 28 of 29
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CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
Document History Page
Document Title: CY7C1161V18/CY7C1176V18/CY7C1163V18/CY7C1165V18, 18-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
Document Number: 001-06582
REV. ECN No. Issue Date
** 430351 See ECN NXR New data sheet
*A 461654 See ECN NXR Revised the MPNs from
*B 497629 See ECN NXR Changed the V
*C 1167806 See ECN VKN/KKVTMP Converted from preliminary to final
*D 2199066 See ECN VKN/AESA Added footnote# 22 related to I
Orig. of
Change
Description of Change
CY7C1176BV18 to CY7C1176V18
CY7C1163BV18 to CY7C1163V18
CY7C1165BV18 to CY7C1165V18
Changed t
t
from 10 ns to 5 ns and changed t
CH
Switching Characteristics table
TH
and t
from 40 ns to 20 ns, changed t
TL
, t
TMSS
from 20 ns to 10 ns in TAP AC
TDOV
TDIS
, tCS, t
TMSH
, t
TDIH
Modified power up waveform
operating voltage to 1.4V to VDD in the Features section, in
Operating Range table and in the DC Electrical Characteristics table
DDQ
Added foot note in page 1
Changed the Maximum rating of Ambient T emperature with Power Applied from
–10°C to +85°C to –55°C to +125°C
Changed V
istics table and in the note below the table
(max) spec from 0.85V to 0.95V in the DC Electrical Character-
REF
Updated foot note 22 to specify Overshoot and Undershoot Spec
Updated Θ
Removed x9 part and its related information
JA
and Θ
JC
values
Updated footnote 25
Added x8 and x9 parts
Changed IDD values from 800 mA to 1080 mA for 400 MHz, 766 mA to 1020 mA
for 375 MHz, 708 mA to 920 mA for 333 MHz, 663 mA to 850 mA for 300 MHz
Changed ISB values from 235 mA to 300 mA for 400 MHz, 227 mA to 290 mA
for 375 MHz, 212 mA to 260 mA for 333 MHz, 201 mA to 250 mA for 300 MHz
Changed t
Changed Θ
CYC(max)
Updated Ordering Information table
spec to 8.4 ns for all speed bins
value from 13.48 °C/W to 17.2 °C/W
JA
DD
,
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Document Number: 001-06582 Rev. *D Revised March 06, 2008 Page 29 of 29
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