Cypress CY7C1145V18, CY7C1143V18, CY7C1141V18, CY7C1156V18 User Manual
CY7C1141V18, CY7C1156V18
CY7C1143V18, CY7C1145V18
18-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.0 Cycle Read Latency)
Features
Note
1. The QDR consortium specification for V
DDQ
is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V
DDQ
= 1.4V to V
DD
.
Functional Description
■ Separate Independent read and write data ports
❐ Supports concurrent transactions
■ 300 MHz to 375 MHz clock for high bandwidth
■ 4-Word Burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 750 MHz) at 375 MHz
■ Read latency of 2.0 clock cycles
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate Port Selects for depth expansion
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ Available in x8, x9, x18, and x36 configurations
■ Full data coherency providing most current data
■ Core V
■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ Variable drive HSTL output buffers
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
= 1.8V ± 0.1V; IO V
DD
= 1.4V to V
DDQ
DD
[1]
The CY7C1141V18, CY7C1156V18, CY7C1143V18, and
CY7C1145V18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR™-II+ architecture. QDR-II+ architecture
consists of two separate ports to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR-II+ architecture has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus required with common IO devices. Access to each
port is accomplished through a common address bus.
Addresses for read and write addresses are latched on alternate
rising edges of the input (K) clock. Accesses to the QDR-II+ read
and write ports are completely independent of one another. To
maximize data throughput, both read and write ports are
equipped with Double Data Rate (DDR) interfaces. Each
address location is associated with four 8-bit words
(CY7C1141 V18), or 9-bit words (CY7C1 156V18), or 18-bit words
(CY7C1143V18), or 36-bit words (CY7C1145V18) that burst
sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input
clocks K and K
, memory bandwidth is maximized while simpli-
fying system design by eliminating bus “turn-arounds”.
Depth expansion is accomplished with Port Selects for each port.
Port Selects enable each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K
registers controlled by the K or K
input clocks. All data outputs pass through output
input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C1141V18 – 2M x 8
CY7C1156V18 – 2M x 9
CY7C1143V18 – 1M x 18
CY7C1145V18 – 512K x 36
Selection Guide
Maximum Operating Frequency 375 333 300 MHz
Maximum Operating Current 1020 920 850 mA
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-06583 Rev. *D Revised March 06, 2008
Description 375 MHz 333 MHz 300 MHz Unit
[+] Feedback [+] Feedback
CY7C1141V18, CY7C1156V18
CY7C1143V18, CY7C1145V18
Logic Block Diagram (CY7C1141V18)
512K x 8 Array
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
D
[7:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q
[7:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
16
19
8
32
8
NWS
[1:0]
V
REF
Write Add. Decode
Write
Reg
16
A
(18:0)
19
512K x 8 Array
512K x 8 Array
512K x 8 Array
Write
Reg
Write
Reg
Write
Reg
8
CQ
CQ
DOFF
QVLD
512K x 9 Array
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
D
[8:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q
[8:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
19
9
36
9
BWS
[0]
V
REF
Write Add. Decode
Write
Reg
18
A
(18:0)
19
512K x 9 Array
512K x 9 Array
512K x 9 Array
Write
Reg
Write
Reg
Write
Reg
9
CQ
CQ
DOFF
QVLD
Logic Block Diagram (CY7C1156V18)
Document Number: 001-06583 Rev. *D Page 2 of 28
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CY7C1141V18, CY7C1156V18
CY7C1143V18, CY7C1145V18
Logic Block Diagram (CY7C1143V18)
256K x 18 Array
CLK
A
(17:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q
[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
18
18
72
18
BWS
[1:0]
V
REF
Write Add. Decode
Write
Reg
36
A
(17:0)
18
256K x 18 Array
256K x 18 Array
256K x 18 Array
Write
Reg
Write
Reg
Write
Reg
18
CQ
CQ
DOFF
QVLD
128K x 36 Array
CLK
A
(16:0)
Gen.
K
K
Control
Logic
Address
Register
D
[35:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Q
[35:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
72
17
36
144
36
BWS
[3:0]
V
REF
Write Add. Decode
Write
Reg
72
A
(16:0)
17
128K x 36 Array
128K x 36 Array
128K x 36 Array
Write
Reg
Write
Reg
Write
Reg
36
CQ
CQ
DOFF
QVLD
Logic Block Diagram (CY7C1145V18)
Document Number: 001-06583 Rev. *D Page 3 of 28
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CY7C1141V18, CY7C1156V18
CY7C1143V18, CY7C1145V18
Pin Configurations
CY7C1141V18 (2M x 8)
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
23
4
5
6
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
NC/72M A
NWS
1
K
WPS
NC/144M
NC NC
NC
NC
NC
TDO
NC
NC
D5
NC
NC
NC
TCK
NC
NC
A NC/288M K NWS
0
V
SS
ANCA
NC V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
Q4
NC
V
DDQ
NC
NC
NC
NC
Q7
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
Q5 V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
ANC
V
SS
A
A
A
D4 V
SS
NC V
SS
NC
NC
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
QVLD
NC
Q6
NC
D7
D6
V
DD
A
8
91011
NC
A NC/36M
RPS
CQ
A NC NC Q3
V
SS
NC NC D3
NC
V
SS
NC
Q2
NC
NC
NC
V
REF
NC
NC
V
DDQ
NC
V
DDQ
NC NC
V
DDQ
V
DDQ
V
DDQ
D1V
DDQ
NC
Q1
NC
V
DDQ
V
DDQ
NC
V
SS
NC D0
NC
TDITMS
V
SS
A
NC
A
NC
D2
NC
ZQ
NC
Q0
NC
NC
NC
NC
A
NC/144M
CY7C1156V18 (2M x 9)
23
4
5
6
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
NC/72M A NC K
WPS NC/144M
NC NC
NC
NC
NC
TDO
NC
NC
D6
NC
NC
NC
TCK
NC
NC
A NC/288M K BWS
0
V
SS
ANCA
NC V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
Q5
NC
V
DDQ
NC
NC
NC
NC
Q8
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
Q6 V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
ANC
V
SS
A
A
A
D5 V
SS
NC V
SS
NC
NC
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
QVLD
NC
Q7
NC
D8
D7
V
DD
A
8
91011
Q0
A NC/36MRPS CQ
A
NC
NC Q4
V
SS
NC NC D4
NC
V
SS
NC
Q3
NC
NC
NC
V
REF
NC
NC
V
DDQ
NC
V
DDQ
NC NC
V
DDQ
V
DDQ
V
DDQ
D2V
DDQ
NC
Q2
NC
V
DDQ
V
DDQ
NC
V
SS
NC D1
NC
TDITMS
V
SS
A
NC
A
NC
D3
NC
ZQ
NC
Q1
NC
NC
D0
NC
A
NC
NC
Document Number: 001-06583 Rev. *D Page 4 of 28
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CY7C1141V18, CY7C1156V18
CY7C1143V18, CY7C1145V18
Pin Configurations (continued)
CY7C1143V18 (1M x 18)
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
23
4
567
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
NC/144M NC/36M BWS
1
KWPS NC/288M
Q9 D9
NC
NC
NC
TDO
NC
NC
D13
NC
NC
NC
TCK
NC
D10
A NC K BWS
0
V
SS
ANCA
Q10 V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
Q11
D12
V
DDQ
D14
Q14
D16
Q16
Q17
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
Q13 V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
A
V
SS
A
A
A
D11 V
SS
NC V
SS
Q12
NC
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
QVLD
NC
Q15
NC
D17
D15
V
DD
A
8
91011
Q0
A NC/72MRPS
CQ
A NC NC Q8
V
SS
NC Q7 D8
NC
V
SS
NC
Q6
D5
NC
NC
V
REF
NC
Q3
V
DDQ
NC
V
DDQ
NC Q5
V
DDQ
V
DDQ
V
DDQ
D4V
DDQ
NC
Q4
NC
V
DDQ
V
DDQ
NC
V
SS
NC D2
NC
TDITMS
V
SS
A
NC
A
D7
D6
NC
ZQ
D3
Q2
D1
Q1
D0
NC
A
NC
CY7C1145V18 (512K x 36)
23
456
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
Q27
D27
D28
D34
DOFF
Q33
NC/288M NC/72M
BWS
2
KWPS BWS
1
Q18
D18
Q30
D31
D33
TDO
Q28
D29
D22
D32
Q34
Q31
TCK
D35
D19
A
BWS
3
K
BWS
0
V
SS
ANCA
Q19 V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
Q20
D21
V
DDQ
D23
Q23
D25
Q25
Q26
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
Q22 V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
A
NC
V
SS
A
A
A
D20 V
SS
Q29 V
SS
Q21
D30
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
QVLD
Q32
Q24
Q35
D26
D24
V
DD
A
891011
Q0
NC/36M
NC/144M
RPS
CQ
A D17
Q17
Q8
V
SS
D16 Q7 D8
Q16
V
SS
D15
Q6
D5
D9
Q14
V
REF
Q11
Q3
V
DDQ
Q15
V
DDQ
D14 Q5
V
DDQ
V
DDQ
V
DDQ
D4V
DDQ
D12
Q4
Q12
V
DDQ
V
DDQ
D11
V
SS
D10 D2
Q10
TDITMS
V
SS
A
Q9
A
D7
D6
D13
ZQ
D3
Q2
D1
Q1
D0
Q13
A
Document Number: 001-06583 Rev. *D Page 5 of 28
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CY7C1141V18, CY7C1156V18
CY7C1143V18, CY7C1145V18
Pin Definitions
Pin Name IO Pin Description
D
[x:0]
Input-
Synchronous
WPS Input-
Synchronous
, NWS
, BWS1,
, BWS
, Input-
1
Synchronous
Input-
Synchronous
3
NWS
BWS
BWS
0
0
2
A Input-
Synchronous
Q
[x:0]
Outputs-
Synchronous
RPS Input-
Synchronous
QVLD Valid output
indicator
K Input-
Clock
K Input-
Clock
CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
CY7C1141V18−D
CY7C1156V18−D
CY7C1143V18−D
CY7C1145V18−D
[7:0]
[8:0]
[17:0]
[35:0]
Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active,
a write operation is initiated. Deasserting deselects the write port. Deselecting the write port causes
D
to be ignored.
[x:0]
Nibble Write Select 0, 1 − Active LOW .(CY7C1141V18 Only) Sampled on the rising edge of the K
and K
clocks during write operations. This is used to select the nibble that is written into the device
NWS
controls D
0
All the Nibble Write Selects are sampled on the same edge as the dat a . Deselecting a N ibble W rite
and NWS1 controls D
[3:0]
[7:4]
.
Select causes the corresponding nibble of data to be ignored and not written into the device.
Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks
during write operations. This is used to select the byte that is written into the device during the current
portion of the write operations. Bytes not written remain unaltered.
CY7C1156V18 − BWS
CY7C1143V18
CY7C1145V18
controls D
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
−
−
[35:27]
controls D
0
BWS0 controls D
BWS
controls D
0
.
[8:0]
and BWS1 controls D
[8:0]
, BWS1 controls D
[8:0]
.
[17:9]
, BWS2 controls D
[17:9]
[26:18],
and BWS3
causes the corresponding byte of data to be ignored and not written into the device.
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.
These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1141V18, 2M x 9 (4 arrays each of 512K
x 9) for CY7C1156V 18, 1M x 18 (4 array s each of 256K x 18) for C Y7C1143V18, and 512K x 36 (4
arrays each of 128K x 36) for CY7C1 145V18. Therefore, only 19 address inputs are needed to access
the entire memory array of CY7C1 141V18 and CY7C1 156V18, 18 address inputs for CY7C1 143V18
and 17 address inputs for CY7C1145V18. These inputs are ignored when the appropriate port is
deselected.
Data Output signals. These pins drive out the requested data during a read operation. V alid data is
driven out on the rising edge of both the K and K
single clock mode. When the read port is deselected, Q
CY7C1141V18−Q
CY7C1156V18−Q
CY7C1143V18−Q
CY7C1145V18−Q
[7:0]
[8:0]
[17:0]
[35:0]
clocks during read operations or K and K when in
are automatically tri-stated.
[x:0]
Read Port Select − Active LOW. Sampled on the rising edge of Positive Input Clock (K). When
active, a read operation is initiated. Deasserting causes the read port to be deselected. When
deselected, the pending access is enabled to complete and the output drivers are automatically
tri-stated following the next rising edge of the K clock. Each read access consists of a burst of four
sequential transfers.
Valid Output Indicator. The Q Valid indicates valid output data. QV LD is edge aligned with CQ and
CQ
.
Positive Input Clock Input. The rising edge of K is used to capture synchronous input s to the device
and to drive out data through Q
edge of K.
when in single clock mode. All accesses are initiated on the rising
[x:0]
Negative Input Clock Input. K is used to capture synchronous inputs presented to the device and
to drive out data through Q
when in single clock mode.
[x:0]
clock (K) of the QDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”
on page 23.
Document Number: 001-06583 Rev. *D Page 6 of 28
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CY7C1141V18, CY7C1156V18
CY7C1143V18, CY7C1145V18
Pin Definitions (continued)
Pin Name IO Pin Description
CQ
ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data
DOFF Input DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The
TDO Output TDO for JTAG.
TCK Input TCK Pin for JTAG.
TDI Input TDI Pin for JTAG.
TMS Input TMS Pin for JTAG.
NC N/A Not Connected to the Die. Tie to any voltage level.
NC/36M N/A Not Connected to the Die. Tie to any voltage level.
NC/72M N/A Not Connected to the Die. Tie to any voltage level.
NC/144M N/A Not Connected to the Die. Tie to any voltage level.
NC/288M N/A Not Connected to the Die. Tie to any voltage level.
V
REF
V
DD
V
SS
V
DDQ
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
Input-
Reference
Power Supply Power Supply Inputs to the Core of the Device.
Ground Ground for the Device.
Power Supply Power Supply Inputs for the Outputs of the Device.
clock (K
) of the QDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”
on page 23.
bus impedance. CQ, CQ
connected between ZQ and ground. Alternatively, connect this pin directly to V
the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
timings in the DLL turned off operationis different from those listed in this data sheet. For normal
operation, connect this pin to a pull up through a 10 KΩ or less pull up resistor . The device behaves
in QDR-I mode when the DLL is turned off. In this mode, operate the device at a frequency of up to
167 MHz with QDR-I timing.
Reference Volt age Input . Static input used to set the reference level for HSTL inputs, outputs, and
AC measurement points.
and Q
output impedance are set to 0.2 x RQ, where RQ is a resistor
[x:0]
, which enables
DDQ
Document Number: 001-06583 Rev. *D Page 7 of 28
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CY7C1141V18, CY7C1156V18
CY7C1143V18, CY7C1145V18
Functional Overview
The CY7C1141V18, CY7C1156V18, CY7C1143V18, and
CY7C1145V18 are synchronous pipelined Burst SRAMs
equipped with both a read port and a write port. The read port is
dedicated to read operations and the write port is dedicated to
write operations. Data flows into the SRAM through the write port
and out through the read port. These devices multiplex the
address inputs in order to minimize the number of address pins
required. By having separate read and write ports, the QDR-II+
completely eliminates the need to “turn-around” the data bus and
avoids any possible data contention, thereby simplifying system
design. Each access consists of four 8-bit data transfers in the
case of CY7C1141V18, four 9-bit data transfers in the case of
CY7C1156V18, four 18-bit data transfers in the case of
CY7C1143V18, and four 36-bit data transfers in the case of
CY7C1145V18 in two clock cycles.
Accesses for both ports are initiated on the Positive Input Clock
(K). All synchronous input and output timing refer to the rising
edge of the Input clocks (K/K
All synchronous data inputs (D
controlled by the input clocks (K and K
outputs (Q
rising edge of the Input clocks (K and K
) pass through output registers controlled by the
[x:0]
All synchronous control (RPS
through input registers controlled by the rising edge of the input
clocks (K/K
). CY7C1143V18 is described in the following
sections. The same basic descriptions apply to CY7C1141V18,
CY7C1156V18, and CY7C1145V18.
Read Operations
The CY7C1 143V18 is organized internally as four arrays of 256K
x 18. Accesses are completed in a burst of four sequential 18-bit
data words. Read operations are initiated by asserting RPS
active at the rising edge of the Positive Input Clock (K). The
address presented to Address inputs are stored in the read
address register. Following the next two K clock rise, the corresponding lowest order 18-bit word of data is driven onto the
Q
using K as the output timing reference. On the subse-
[17:0]
quent rising edge of K the next 18-bit data word is driven onto
the Q
are driven out onto Q
from the rising edge of the Input clock K or K
internallogic, each read access must be allowed to complete.
Each read access consists of four 18-bit data words and takes
two clock cycles to complete. Therefore, read accesses to the
device cannot be initiated on two consecutive K clock rises. The
internal logic of the device ignores the second read request.
Initiate read accesses on every other K clock rise. This pipelines
the data flow such that data is transferred out of the device on
every rising edge of the input clocks K and K
When the read port is deselected, the CY7C1143V18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tri-states the outputs following the next
rising edge of the Positive Input Clock (K). This enables for a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
. This process continues until all four 18-bit data words
[17:0]
).
) pass through input registers
[x:0]
). All synchronous data
) as well.
, WPS, BWS
. The requested data is valid 0.45 ns
[17:0]
) inputs pass
[x:0]
. To maintain the
.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the Positive Input Clock (K). On the following K
clock rise the data presented to D
the lower 18-bit Write Data register, provided BWS
asserted active. On the subsequent rising edge of the Negative
Input Clock (K
) the information presented to D
into the Write Data register , provided BWS
active. This process continues for one more cycle until four 18-bit
is latched and stored into
[17:0]
[1:0]
[1:0]
is also stored
[17:0]
are both asserted
are both
words (a total of 72 bits) of data are stored in the SRAM. The 72
bits of data are then written into the memory array at the specified
location. Therefore, write accesses to the device cannot be
initiated on two consecutive K clock rises. The internal logic of
the device ignores the second write request. Initiate write
accesses on every other rising edge of the Positive Input Clock
(K). This pipelines the data flow such that 18 bits of data can be
transferred into the device on every rising edge of the input
clocks (K and K
).
When deselected, the write port ignores all inputs after the
pending write operations are completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1143V18. A
write operation is initiated as described in the Write Operations.
The bytes that are written are determined by BWS
which are sampled with each set of 18-bit data words. Asserting
and BWS1,
0
the appropriate Byte Write Select input during the data portion of
a write enables the data being presented to be latched and
written into the device. Deasserting the Byte Write Select input
during the data portion of a write enables the data stored in the
device for that byte to remain unaltered. Use this feature to
simplify read/modify/write operations to a Byte Write operation.
Concurrent Transactions
The read and write ports on the CY7C1 143V18 operate independently of one another. Because each port latches the address
inputs on different clock edges, the user can read or write to any
location, regardless of the transaction on the other port. If the
ports access the same location when a read follows a write in
successive clock cycles, the SRAM delivers the most recent
information associated with the specified address location. This
includes forwarding data from a write cycle that was initiated on
the previous K clock rise.
Read accesses and write access must be scheduled such that
one transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on the
previous state of the SRAM. If both ports were deselected, the
read port takes priority. If a read was initiated on the previous
cycle, the write port is based on priority (since read operations
cannot be initiated on consecutive cycles). If a write was initiated
on the previous cycle, the read port is based on priority (since
write operations cannot be initiated on consecutive cycles).
Therefore, asserting both port selects active from a deselected
state results in alternating read/write operations initiated, with the
first access being a read.
Document Number: 001-06583 Rev. *D Page 8 of 28
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CY7C1141V18, CY7C1156V18
CY7C1143V18, CY7C1145V18
Depth Expansion
The CY7C1143V18 has a Port Select input for each port. This
enables easy depth expansion. Both Port Selects are sampled
on the rising edge of the Positive Input Clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed before the device is deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V
driver impedance. The value of RQ must be 5X the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
to enable the SRAM to adjust its output
SS
, with V
=1.5V. The
DDQ
Echo Clocks
Echo clocks are provided on the QDR-II+ to simplify data capture
on high speed systems. Two echo clocks are generated by the
QDR-II+. CQ is referenced with respect to K and CQ
enced with respect to K
. These are free running clocks and are
is refer-
synchronized to the input clock of the QDR-II+. The timings for
the echo clocks are shown in the AC timing table.
Vali d Da ta Indicator (QVLD)
QVLD is provided on the QDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the QDR-II+ device
along with data output. This signal is also edge-aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
DLL
These chips use a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF
pin. When the DLL is turned off, the device behaves in
QDR-I mode (with 1.0 cycle latency and a longer access time).
For more information, refer to the application note, “DLL Considerations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be
reset by slowing or stopping the input clocks K and K
minimum of 30 ns. However, it is not necessary for the DLL to be
reset to lock to the desired frequency . During power up, when the
DOFF
is tied HIGH, the DLL gets locked after 2048 cycles of
stable clock.
for a
Document Number: 001-06583 Rev. *D Page 9 of 28
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