Cypress CY7C1148V18, CY7C1146V18, CY7C1157V18, CY7C1150V18 User Manual
CY7C1146V18, CY7C1157V18
CY7C1148V18, CY7C1150V18
18-Mbit DDR-II+ SRAM 2-Word Burst
Architecture (2.0 Cycle Read Latency)
Features
Note
1. The QDR consortium specification for V
DDQ
is 1.5V + 0.1V . The Cyp ress QDR devices exceed th e QDR consorti um specifi catio n and ar e capab le of support ing V
DDQ
= 1.4V to V
DD
.
Functional Description
■ 18 Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
■ 300 MHz to 375 MHz clock for high bandwidth
■ 2-Word burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces
(data transferred at 750 MHz) at 375 MHz
■ Read latency of 2.0 clock cycles
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ Core V
■ HSTL inputs and Variable drive HSTL output buffers
■ Available in 165-Ball FBGA p ackage (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1-compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
= 1.8V ± 0.1V; IO V
DD
= 1.4V to V
DDQ
DD
[1]
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C1146V18 – 2M x 8
CY7C1157V18 – 2M x 9
CY7C1148V18 – 1M x 18
CY7C1150V18 – 512K x 36
The CY7C1146V18, CY7C1157V18, CY7C1148V18, and
CY7C1150V18 are 1.8V Synchronous Pipelined SRAMs
equipped with DDR-II+ architecture. The DDR-II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K
of K and K
. Each address location is associated with two 8-bit
. Read data is driven on the rising edges
words (CY7C1146V18) or 9-bit words (CY7C1157V18) or 18-bit
words (CY7C1148V18) or 36-bit words (CY7C1150V18) that
burst sequentially into or out of the device.
Asynchronous inputs include output impedance matching input
(ZQ). Synchronous data outputs (Q, sharing the same physical
pins as the data inputs D) are tightly matched to the two output
echo clocks CQ/CQ
, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K
registers controlled by the K or K
input clocks. All data outputs pass through output
input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
Maximum Operating Frequency 375 333 300 MHz
Maximum Operating Current 1020 920 850 mA
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-06621 Rev. *D Revised March 06, 2008
Description 375 MHz 333 MHz 300 MHz Unit
[+] Feedback [+] Feedback
CY7C1146V18, CY7C1157V18
CY7C1148V18, CY7C1150V18
Logic Block Diagram (CY7C1146V18)
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
DQ
[7:0]
Output
Logic
Reg.
Reg.
Reg.
8
8
16
8
NWS
[1:0]
V
REF
Write Add. Decode
8
8
LD
Control
20
1M x 8 Array
1M x 8 Array
Write
Reg
Write
Reg
CQ
CQ
R/W
DOFF
QVLD
8
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
DQ
[8:0]
Output
Logic
Reg.
Reg.
Reg.
9
9
18
9
BWS
[0]
V
REF
Write Add. Decode
9
9
LD
Control
20
1M x 9 Array
1M x 9 Array
Write
Reg
Write
Reg
CQ
CQ
R/W
DOFF
QVLD
9
Logic Block Diagram (CY7C1157V18)
Document Number: 001-06621 Rev. *D Page 2 of 27
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CY7C1146V18, CY7C1157V18
CY7C1148V18, CY7C1150V18
Logic Block Diagram (CY7C1148V18)
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
DQ
[17:0]
Output
Logic
Reg.
Reg.
Reg.
18
18
36
18
BWS
[1:0]
V
REF
Write Add. Decode
18
18
LD
Control
19
512K x 18 Array
512K x 18 Array
Write
Reg
Write
Reg
CQ
CQ
R/W
DOFF
QVLD
18
CLK
A
(17:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
DQ
[35:0]
Output
Logic
Reg.
Reg.
Reg.
36
36
72
36
BWS
[3:0]
V
REF
Write Add. Decode
36
36
LD
Control
18
256K x 36 Array
256K x 36 Array
Write
Reg
Write
Reg
CQ
CQ
R/W
DOFF
QVLD
36
Logic Block Diagram (CY7C1150V18)
Document Number: 001-06621 Rev. *D Page 3 of 27
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CY7C1146V18, CY7C1157V18
CY7C1148V18, CY7C1150V18
Pin Configurations
CY7C1146V18 (2M x 8)
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
234 5671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
NC/72M A
NWS
1
KR/W
NC/144M
NC
NC
NC
NC
NC
TDO
NC
NC
NC
NC
NC
NC
TCK
NC
NC
A NC/288M
K
NWS
0
V
SS
AAA
NC V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
DQ4
NC
V
DDQ
NC
NC
NC
NC
DQ7
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
DQ5 V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
A
NC
V
SS
A
A
A
NC V
SS
NC V
SS
NC
NC
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
QVLD
NC
DQ6
NC
NC
NC
V
DD
A
891011
NC
A NC/36M
LD
CQ
A NC
NC
DQ3
V
SS
NC NC NC
NC
V
SS
NC
DQ2
NC
NC
NC
V
REF
NC
NC
V
DDQ
NC
V
DDQ
NC NC
V
DDQ
V
DDQ
V
DDQ
NCV
DDQ
NC
DQ1
NC
V
DDQ
V
DDQ
NC
V
SS
NC NC
NC
TDITMS
V
SS
A
NC
A
NC
NC
NC
ZQ
NC
DQ0
NC
NC
NC
NC
A
CY7C1157V18 (2M x 9)
234 5671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
NC/72M A NC
K
R/W
NC/144M
NC
NC
NC
NC
NC
TDO
NC
NC
NC
NC
NC
NC
TCK
NC
NC
A NC/288M
K
BWS
0
V
SS
AAA
NC V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
DQ4
NC
V
DDQ
NC
NC
NC
NC
DQ7
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
DQ5 V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
A
NC
V
SS
A
A
A
NC V
SS
NC V
SS
NC
NC
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
QVLD
NC
DQ6
NC
NC
NC
V
DD
A
891011
DQ8
A NC/36M
LD
CQ
A NC
NC
DQ3
V
SS
NC NC NC
NC
V
SS
NC
DQ2
NC
NC
NC
V
REF
NC
NC
V
DDQ
NC
V
DDQ
NC NC
V
DDQ
V
DDQ
V
DDQ
NCV
DDQ
NC
DQ1
NC
V
DDQ
V
DDQ
NC
V
SS
NC NC
NC
TDITMS
V
SS
A
NC
A
NC
NC
NC
ZQ
NC
DQ0
NC
NC
NC
NC
A
Document Number: 001-06621 Rev. *D Page 4 of 27
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CY7C1146V18, CY7C1157V18
CY7C1148V18, CY7C1150V18
Pin Configurations (continued)
CY7C1148V18 (1M x 18)
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
234 5671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
NC/72M A
BWS
1
K
R/W
NC/144M
DQ9
NC
NC
NC
NC
TDO
NC
NC
NC
NC
NC
NC
TCK
NC
NC
A NC/288M
K
BWS
0
V
SS
ANCA
DQ10 V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
DQ11
NC
V
DDQ
NC
DQ14
NC
DQ16
DQ17
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
DQ13 V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
A
NC
V
SS
A
A
A
NC V
SS
NC V
SS
DQ12
NC
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
QVLD
NC
DQ15
NC
NC
NC
V
DD
A
891011
DQ0
A NC/36M
LD
CQ
A NC
NC
DQ8
V
SS
NC DQ7 NC
NC
V
SS
NC
DQ6
NC
NC
NC
V
REF
NC
DQ3
V
DDQ
NC
V
DDQ
NC DQ5
V
DDQ
V
DDQ
V
DDQ
NCV
DDQ
NC
DQ4
NC
V
DDQ
V
DDQ
NC
V
SS
NC NC
NC
TDITMS
V
SS
A
NC
A
NC
NC
NC
ZQ
NC
DQ2
NC
DQ1
NC
NC
A
CY7C1150V18 (512K x 36)
234 5671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
CQ
NC
NC
NC
NC
DOFF
NC
NC/144M NC/36M
BWS
2
K
R/W
BWS
1
DQ27
DQ18
NC
NC
NC
TDO
NC
NC
DQ31
NC
NC
NC
TCK
NC
DQ28
A
BWS
3
K
BWS
0
V
SS
ANCA
DQ19 V
SS
V
SS
V
SS
V
SS
V
DD
A
V
SS
V
SS
V
SS
V
DD
DQ20
DQ21
V
DDQ
DQ32
DQ23
DQ34
DQ25
DQ26
A
V
DDQ
V
SS
V
DDQ
V
DD
V
DD
DQ22 V
DDQ
V
DD
V
DDQ
V
DD
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
V
DDQ
V
SS
V
SS
V
SS
V
SS
A
ANC
V
SS
A
A
A
DQ29 V
SS
NC V
SS
DQ30
NC
V
REF
V
SS
V
DD
V
SS
V
SS
A
V
SS
QVLD
NC
DQ33
NC
DQ35
DQ24
V
DD
A
891011
DQ0
A NC/72M
LD
CQ
A NC
NC
DQ8
V
SS
NC DQ17 DQ7
NC
V
SS
NC
DQ6
DQ14
NC
NC
V
REF
NC
DQ3
V
DDQ
NC
V
DDQ
NC DQ5
V
DDQ
V
DDQ
V
DDQ
DQ4V
DDQ
NC
DQ13
NC
V
DDQ
V
DDQ
NC
V
SS
NC DQ1
NC
TDITMS
V
SS
A
NC
A
DQ16
DQ15
NC
ZQ
DQ12
DQ2
DQ10
DQ11
DQ9
NC
A
Document Number: 001-06621 Rev. *D Page 5 of 27
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CY7C1146V18, CY7C1157V18
CY7C1148V18, CY7C1150V18
Pin Definitions
Pin Name IO Pin Description
DQ
[x:0]
Input OutputSynchronous
LD Input-
Synchronous
NWS
BWS
BWS
, NWS
0
, BWS1,
0
, BWS
2
, Input-
1
Synchronous
Input-
Synchronous
3
Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks when write
operations are valid. These pins drive out the requested data when a read operation is active. Valid
data is driven out on the rising edge of both the K and K
When read access is deselected, Q
CY7C1 146V18 − DQ
CY7C1 157V18 − DQ
CY7C1 148V18 − DQ
CY7C1 150V18 − DQ
[7:0]
[8:0]
[17:0]
[35:0]
are automatically tri-stated.
[x:0]
Synchronous Load. This input is brought LOW when a bus cycle sequence is to be defined. This
definition includes address and read/write direction. All transactions operate on a burst of two data.
LD must meet the setup and hold times around edge of K.
Nibble Write Select 0, 1 − Active LOW.(CY7C1146V18 Only) Sampled on the rising edge of the K
and K
clocks when the write operation is active. It is used to select the nibble that is written into the
device NWS
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write
controls D
0
and NWS1 controls D
[3:0]
[7:4]
Select causes the corresponding nibble of data to be ignored and not written into the device.
Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks
when the Write operation is active. It is used to select the byte that is written into the device when
the current portion of the write operation is active. Bytes not written remain unaltered.
CY7C1 157V18 − BWS
CY7C1 148V18 − BWS0 controls D
CY7C1 148V18 − BWS0 controls D
controls D
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
[35:27]
.
controls D
0
[8:0]
, and BWS1 controls D
[8:0]
, BWS1 controls D
[8:0]
causes the corresponding byte of data to be ignored and not written into the device.
clocks when read operations are active.
.
[17:9].
, BWS2 controls D
[17:9]
[26:18]
, and BWS3
A Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.
These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 2M x 8 (two arrays each of1M x 8) for CY7C1146V18, 2M x 9 (two arrays each of 1M
x 9) for CY7C1157V18, 1M x 18 (two arrays each of 512K x 18) for CY7C1148V18, and 512K x 36
(two arrays each of 256K x 18) for CY7C1150V18. All the address inputs are ignored when the
appropriate port is deselected.
R/W
Input-
Synchronous
Synchronous Read/Write Input. When LD is LOW, this input designates the access type (read
when R/W
is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold
times around edge of K.
QVLD Valid Output
Indicator
K Input-
Clock
K Input-
Clock
Valid Output Indicator . The Q V alid indicates valid output data. QVLD is edge aligned with CQ and
CQ
.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
edge of K.
when in single clock mode. All accesses are initiated on the rising
[x:0]
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device
and to drive out data through Q
when in single clock mode.
[x:0]
CQ Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
clock (K) of the DDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”
on page 22.
CQ
Clock Output
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
clock (K) of the DDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”
on page 22.
ZQ Input Output Impe dance Matching Input. This input is used to tune the device outputs to the system dat a
bus impedance. CQ, CQ,
connected between ZQ and ground. Alternatively, connect this pin directly to V
the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
and Q
output impedance are set to 0.2 x RQ, where RQ is a resistor
[x:0]
, which enables
DDQ
Document Number: 001-06621 Rev. *D Page 6 of 27
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CY7C1146V18, CY7C1157V18
CY7C1148V18, CY7C1150V18
Pin Definitions (continued)
Pin Name IO Pin Description
DOFF
TDO Output TDO for JTAG.
TCK Input TCK Pin for JT AG.
TDI Input TDI Pin for JTAG.
TMS Input TMS Pin for JTAG.
NC N/A Not Connected to the Die. Tie to any voltage level.
NC/36M N/A Not Connected to the Die. Tie to any voltage level.
NC/72M N/A Not Connected to the Die. Tie to any voltage level.
NC/144M N/A Not Connected to the Die. Tie to any voltage level.
NC/288M N/A Not Connected to the Die. Tie to any voltage level.
V
REF
V
DD
V
SS
V
DDQ
Input DLL Turn Off − Active LOW . Connecting this pin to ground turns off the DLL inside the device. The
timings in the DLL turned off operation are different from those listed in this data sheet. For normal
operation, connect this pin to a pull up through a 10 KΩ or less pull up resistor. The device behaves
in DDR-I mode when the DLL is turned off. In this mode, operate the device at a frequency of up to
167 MHz with DDR-I timing.
Input-
Reference
Power Supply Power Supply Inputs to the Core of the Device.
Ground Ground for the Device.
Power Supply Power Supply Inputs for the Outputs of the Device.
Reference Volt age Input. S tatic input used to set the reference level for HSTL inputs, Outputs, and
AC measurement points.
Document Number: 001-06621 Rev. *D Page 7 of 27
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CY7C1146V18, CY7C1157V18
CY7C1148V18, CY7C1150V18
Functional Overview
The CY7C1146V18, CY7C1157V18, CY7C1148V18, and
CY7C1150V18 are synchronous pipelined Burst SRAMs
equipped with a DDR interface.
Accesses are initiated on the rising edge of the p ositive input
clock (K). All synchronous input and output timings refer to the
rising edge of the Input clocks (K/K).
All synchronous data inputs (D
controlled by the rising edge of the input clocks (K/K
synchronous data outputs (Q
controlled by the rising edge of the input clocks (K/K
All synchronous control (R/W, LD, BWS
input registers controlled by the rising edge of the input clock (K).
CY7C1148V18 is described in the following sections. The same
basic descriptions apply to CY7C1146V18, CY7C1157V18, and
CY7C1150V18.
Read Operations
The CY7C1148V18 is organized internally as a single array of
1M x 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
R/W
HIGH and LD LOW at the rising edge of the positive input
clock (K). The address presented to Address inputs are stored in
the read address register. Following the next two K clock rise the
corresponding 18-bit word of data from this address location is
driven onto the Q
the subsequent rising edge of K
using K as the output timing reference. On
[17:0]
the address location generated by the burst counter is driven
onto the Q
rising edge of the input clock (K/K
. The requested data is valid 0.45 ns from the
[17:0]
each read access must be enabled to complete. Initiate read
accesses on every rising edge of the positive input clock (K).
When read access is deselected, the CY7C1148V18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tri-states the outputs following the next
rising edge of the positive Input clock (K). This enables a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to Address inputs is stored in the write
address register. On the following K clock rise the data presented
to D
provided BWS
rising edge of the Negative Input Clock (K
presented to D
provided BWS
is then written into the memory array at the specified location.
Initiate write accesses on every rising edge of the positive input
clock (K). This pipelines the data flow such that 18 bits of data
transfers into the device on every rising edge of the input clocks
(K and K
When write access is deselected, the device ignores all inputs
after the pending write operations are completed.
is latched and stored into the 18-bit Write Data register
[17:0]
are both asserted active. On the subseque nt
[1:0]
is also stored into the Write Data register
[17:0]
are both asserted active. The 36 bits of data
[1:0]
).
) pass through input registers
[x:0]
) pass through output registers
[x:0]
) inputs pass through
[0:X]
) as well.
the next 18-bit data word from
). T o maintain the internal logic,
) the information
). All
Byte Write Operations
Byte Write operations are supported by the CY7C1148V18. A
write operation is initiated as described in the Write Operations.
The bytes that are written are determined by BWS
which are sampled with each set of 18-bit data word. Asserting
and BWS
0
the appropriate Byte Write Select input when the data portion of
a write enables the data presented to be latched and written into
the device. Deasserting the Byte Write Select input when the
data portion of a write enables the data stored in the device fo r
that byte to remain unaltered. Use this feature to simplify
read/modify/write operations to a Byte Write operation.
Double Data Rate Operation
The CY7C1148V18 enables high-performance operation
through high clock frequencies (achieved through pipelining) and
double data rate mode of operation. The CY7C1148V18 requires
two No Operation (NOP) cycle when transitioning from a read to
a write cycle. At higher frequencies, some applications may
require a third NOP cycle to avoid contention.
If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information must be stored
because the SRAM cannot perform the last word write to the
array without conflicting with the read. The data stays in this
register until the next write cycle occurs. On the first write cycle
after the read(s), the stored data from the earlier write is written
into the SRAM array. This is called a Posted Write.
If a Read is performed on the same address on which a write is
performed in the previous cycle, the SRAM reads out the most
current data. The SRAM does this by bypassing the memory
array and reading the data from the registers.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V
driver impedance. The value of RQ must be 5x the value of the
to allow the SRAM to adjust its output
SS
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω
output impedance is adjusted every 1024 cycles upon power up
, with V
=1.5V. The
DDQ
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the DDR-II+ to simplify data capture
on high-speed systems. Two echo clocks are generated by the
DDR-II+. CQ is referenced with respect to K and CQ is referenced with respect to K
. These are free-running clocks and are
synchronized to the Input clock of the DDR-II+. The timings for
the echo clocks are shown in the “Switching Characteristics” on
page 22.
Valid Data Indicator (QVLD)
QVLD is provided on the DDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the DDR-II+ device
along with Data output. This signal is also edge-aligned with the
1
Document Number: 001-06621 Rev. *D Page 8 of 27
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CY7C1146V18, CY7C1157V18
CY7C1148V18, CY7C1150V18
echo clock and follows the timing of any data pin. This signal is
Notes
2. The above application shows two DDR-II+ used.
3. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW,
↑ represents rising edge.
4. Device powers up deselected and the outputs in a tri-state condition.
5. “A” represents address location latched by the devices when transaction was initiated and A + 1 represents the addresses sequence in the burst.
6. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
7. Data inputs are registered at K and K
rising edges. Data outputs are delivered on K and K rising edges.
8. It is recommended that K = K
= HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line ch arging symmetrically.
asserted half a cycle before valid data arrives.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF
pin. When the DLL is turned off, the device behaves in
Application Example
Figure 1 shows two DDR-II+ used in an application.
Figure 1. Application Example
DDR-I mode (with 1.0 cycle latency and a longer access time).
For more information, refer to the application note, “DLL Considerations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be
reset by slowing or stopping the input clocks K and K for a
minimum of 30 ns. However, it is not necessary for the DLL to be
reset in order to lock to the desired frequency. During Power up,
when the DOFF
is tied HIGH, the DLL gets locked after 2048
cycles of stable clock.
ZQ
CQ/CQ
K
K
R = 250ohms
DQ
A
SRAM#2
LD R/W
BUS
MASTER
(CPU or ASIC)
Echo Clock1/Echo Clock1
Echo Clock2/Echo Clock2
Addresses
Cycle Start
R/W
Source CLK
Source CLK
DQ
DQ
A
SRAM#1
LD R/W
Truth Table
The truth table for the CY7C1146V18, CY7C1157V18, CY7C1148V18, and CY7C1150V18 follows.
Operation K LD R/W DQ DQ
Write Cycle:
Load address; wait one cycle; input write data on consecutive
K and K
rising edges.
Read Cycle: (2.0 cycle latency)
Load address; wait two cycle; read data on consecutive K and
K
rising edges.
L – H L L D(A) at K (t + 1) ↑ D(A + 1) at K (t + 1) ↑
L – H L H Q(A) at K (t + 2)↑ Q(A + 1) at K
ZQ
CQ/CQ
K
K
[3, 4, 5, 6, 7, 8]
R = 250ohms
(t + 2) ↑
NOP: No Operation L – H H X High-Z High-Z
Standby: Clock Stopped Stopped X X Previous State Previous St ate
Document Number: 001-06621 Rev. *D Page 9 of 27
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