Page 1
CY7C1049GN
4-Mbit (512K words × 8-bit) Static RAM
4-Mbit (512K words × 8-bit) Static RAM
Note
1. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V
CC
= 1.8 V (for a VCC range of 1.65 V–2.2 V),
V
CC
= 3 V (for a VCC range of 2.2 V–3.6 V), and VCC = 5 V (for a VCC range of 4.5 V–5.5 V), TA = 25 °C.
Features
Functional Description
■ High speed
❐ t
= 10 ns
AA
■ Low active and standby currents
❐ Active current: I
❐ Standby current: I
■ Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and
= 38 mA typical
CC
= 6 mA typical
SB2
4.5 V to 5.5 V
■ 1.0 V data retention
■ TTL-compatible inputs and outputs
■ Pb-free 36-pin SOJ and 44-pin TSOP II packages
CY7C1049GN is a high-performance CMOS fast static RAM
device organized as 512K words by 8-bits.
Data writes are performed by asserting the Chip Enable (CE
Write Enable (WE
) inputs LOW, while providing the data on I/O
through I/O7 and address on A0 through A18 pins.
Data reads are performed by asserting the Chip Enable (CE
Output Enable (OE
) inputs LOW and providing the required
address on the address lines. Read data is accessible on the I/O
lines (I/O0 through I/O7).
All I/Os (I/O0 through I/O7) are placed in a high-impedance state
during the following events:
■ The device is deselected (CE HIGH)
■ The control signal OE is de-asserted
The logic block diagram is on page 2.
Product Portfolio
Power Dissipation
f = f
max
Max Typ
Standby, I
[1]
SB2
Product Range VCC Range (V)
Speed
(ns)
10/15
Operating ICC, (mA)
[1]
Typ
CY7C1049GN18 Industrial 1.65 V–2.2 V 15 – 40 6 8
CY7C1049GN30 2.2 V–3.6 V 10 38 45
CY7C1049GN 4.5 V–5.5 V 10 38 45
) and
0
) and
(mA)
Max
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 002-10613 Rev. *C Revised November 14, 2017
Page 2
CY7C1049GN
Logic Block Diagram – CY7C1049GN
512Kx8
RAMARRAY
ROWDECODER
A1
A2
A3
A4
A5
A6
A7
A8
A9
A0
COLUMN
DECODER
A10
SENSE
AMPLIFIERS
A11
A12
A13
A14
A15
A16
A17
A18
INPUTBUFFER
I/O0‐I/O
7
WE
OE
CE
Document Number: 002-10613 Rev. *C Page 2 of 17
Page 3
CY7C1049GN
Contents
Pin Configurations ........................................................... 4
Maximum Ratings .............................................................5
Operating Range ...............................................................5
DC Electrical Characteristics ..........................................5
Capacitance ......................................................................6
Thermal Resistance ..........................................................6
AC Test Loads and Waveforms ....................................... 6
Data Retention Characteristics .......................................7
Data Retention Waveform ................................................7
AC Switching Characteristics ......................................... 8
Switching Waveforms ......................................................9
Truth Table ......................................................................12
Ordering Information ......................................................13
Ordering Code Definitions ......................................... 13
Package Diagrams ..........................................................14
Acronyms ........................................................................15
Document Conventions .................................................15
Units of Measure ....................................................... 15
Document History Page .................................................16
Sales, Solutions, and Legal Information ......................17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC® Solutions ......................................................17
Cypress Developer Community ................................. 17
Technical Support ..................................................... 17
Document Number: 002-10613 Rev. *C Page 3 of 17
Page 4
CY7C1049GN
Pin Configurations
SOJ
A18A1
235
A17A2
334
A16A3
433
I/O7I/O0
730
OE
631
CE
GNDV
CC
928
VCCGND
10 27
I/O5I/O2
11 26
I/O4I/O3
12 25
A14
WE
13 24
A13
A5
14 23
A12
A6
15 22
A11
A7
16 21
A10
A8
17 20
NCA9
18 19
NCA0
136
I/O6I/O1
829
A15A4
532
NCNC
243
NCA0
342
A18A1
441
A15A4
738
A16
639
A3
I/O7I/O0
936
I/O6I/O1
10 35
VSSVCC
11 34
VCCVSS
12 33
I/O5
I/O2
13 32
I/O4
I/O3
14 31
A14
/WE
15 30
A13
A5
16 29
A12A6
17 28
A11A7
18 27
A10A8
19 26
NCA9
20 25
NC
NC
21 24
NC
22 23
NCNC
144
/OE/CE
837
A17A2
540
NC
44-pin TSOP II
Note
2. NC pins are not connected internally to the die.
Figure 1. 36-pin SOJ pinout
[2]
Document Number: 002-10613 Rev. *C Page 4 of 17
Figure 2. 44-pin TSOP II pinout, Single Chip Enable
[2]
Page 5
CY7C1049GN
Maximum Ratings
Notes
3. V
IL(min)
= –2.0 V and V
IH(max)
= VCC + 2 V for pulse durations of less than 20 ns.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= 1.8 V (for VCC range of 1.65 V – 2.2 V),
V
CC
=3V (for VCC range of 2.2V – 3.6 V), and VCC = 5 V (for VCC range of 4.5 V – 5.5 V), TA = 25 °C.
5. This parameter is guaranteed by design and not tested.
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature
with power applied ................................... –55 C to +125 C
Supply voltage
on V
relative to GND
CC
DC voltage applied to outputs
in HI-Z State
[3]
................................... –0.5 V to VCC + 0.5 V
[3]
..................... –0.5 to VCC + 0.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
DC input voltage
[3]
..............................–0.5 V to VCC + 0.5 V
Current into outputs (in LOW state) ............................ 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Latch-up current .................................................... > 140 mA
Operating Range
Grade Ambient Temperature V
Industrial –40 C to +85 C 1.65 V to 2.2 V,
CC
2.2 V to 3.6 V,
4.5 V to 5.5 V
Parameter Description Test Conditions
V
OH
V
OL
V
IH
Output HIGH
voltage
Output LOW
voltage
Input HIGH
voltage
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA 1.4 – – V
2.2 V to 2.7 V V
2.7 V to 3.0 V V
3.0 V to 3.6 V V
4.5 V to 5.5 V V
4.5 V to 5.5 V V
= Min, IOH = –1.0 mA 2 – –
CC
= Min, IOH = –4.0 mA 2.2 – –
CC
= Min, IOH = –4.0 mA 2.4 – –
CC
= Min, IOH = –4.0 mA 2.4 – –
CC
= Min, IOH = –0.1mA VCC – 0.5
CC
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA – – 0.2 V
2.2 V to 2.7 V V
2.7 V to 3.6 V V
4.5 V to 5.5 V V
= Min, IOL = 2 mA – – 0.4
CC
= Min, IOL = 8 mA – – 0.4
CC
= Min, IOL = 8 mA – – 0.4
CC
1.65 V to 2.2 V – 1.4 – VCC + 0.2
2.2 V to 2.7 V – 2 – V
2.7 V to 3.6 V – 2 – VCC + 0.3
4.5 V to 5.5 V – 2 – VCC + 0.5
V
IL
Input LOW
voltage
1.65 V to 2.2 V – –0.2
2.2 V to 2.7 V – –0.3
2.7 V to 3.6 V – –0.3
4.5 V to 5.5 V – –0.5
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Input leakage current GND < VIN < V
Output leakage current GND < V
Operating supply current Max VCC, I
CMOS levels
Automatic CE power-down
current – TTL inputs
Automatic CE power-down
current – CMOS inputs
Max VCC, CE > VIH,
V
Max VCC, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
OUT
OUT
> VIH or VIN < VIL, f = f
IN
CC
< VCC, Output disabled –1 – +1 A
= 0 mA,
10 ns/15 ns
Min Ty p
[5]
[3]
[3]
[3]
[3]
[4]
Max
––
+ 0.3
CC
–0.4V
–0.6
–0.8
–0.8
Unit
[3]
V
[3]
[3]
[3]
–1 – +1 A
f = 100 MHz – 38 45 mA
f = 66.7 MHz – – 40
––15mA
MAX
–68mA
Document Number: 002-10613 Rev. *C Page 5 of 17
Page 6
CY7C1049GN
Capacitance
90%
10%
V
HIGH
GND
90%
10%
All Input Pulses
V
CC
Output
5 pF*
* Including
jig and
scope
(b)
R1
R2
Rise Time:
Fall Time:
> 1 V/ns
(c)
Output
50
Z0= 50
V
TH
30 pF*
* Capacitive load consists
of all components of the
test environment
High-Z Characteristics:
(a)
> 1 V/ns
Notes
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full-device AC operation assumes a 100-µs ramp time from 0 to V
CC(min)
and a 100-µs wait time after VCC stabilization.
Parameter
C
IN
C
OUT
[6]
Description Test Conditions 36-pin SOJ 44-pin TSOP II Unit
Input capacitance TA = 25 C, f = 1 MHz,
I/O capacitance 10 10 pF
Thermal Resistance
Parameter
JA
JC
[6]
Description Test Conditions 36-pin SOJ 44-pin TSOP II Unit
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
= V
V
CC
CC(typ)
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
Figure 3. AC Test Loads and Waveforms
10 10 pF
59.52 68.85 C/W
31.48 15.97 C/W
[7]
Parameters 1.8 V 3.0 V 5.0 V Unit
R1 1667 317 317
R2 1538 351 351
0.9 1.5 1.5 V
1.8 3 3 V
V
V
HIGH
TH
Document Number: 002-10613 Rev. *C Page 6 of 17
Page 7
CY7C1049GN
Data Retention Characteristics
t
CDR
t
R
VDR = 1.0 V
DATA RETENTION MODE
V
CC(min)
V
CC(min)
V
CC
CE
Notes
8. Full-device operation requires linear VCC ramp from V
DR
to V
CC(min)
> 100 s or stable at V
CC (min)
> 100 s.
9. These parameters are guaranteed by design.
Over the operating range of –40 C to 85 C
Parameter Description Conditions Min Max Unit
V
DR
I
CCDR
t
CDR
[8, 9]
t
R
[9]
VCC for data retention 1 – V
Data retention current V
Chip deselect to data retention
= 1.2 V, CE > VCC – 0.2 V
CC
V
> VCC – 0.2 V, or VIN < 0.2 V
IN
[8]
,
–8mA
0–ns
time
Operation recovery time VCC > 2.2 V 10 – ns
VCC < 2.2 V 15 – ns
Data Retention Waveform
Figure 4. Data Retention Waveform
[8]
Document Number: 002-10613 Rev. *C Page 7 of 17
Page 8
CY7C1049GN
AC Switching Characteristics
Notes
10. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
l ev el s o f 0 to 3 V ( fo r V
CC
> 3 V) and 0 to VCC (f o r VCC < 3 V). Test conditions for the read cycle use output loading, as shown in part (a) of Fig ur e 3 on pa ge 6, unless specified otherwise.
11. t
HZOE
, t
HZCE
, t
HZWE
, t
LZOE
, t
LZCE
, and t
LZWE
are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 3 on page 6. Transition is measured 200 mV from steady state
voltage.
12. These parameters are guaranteed by design and are not tested.
13. The internal write time of the memory is defined by the overlap of WE
= VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
14. The minimum write cycle pulse width in Write Cycle No. 2 (WE
Controlled, OE LOW) should be equal to sum of tDS and t
HZWE
.
Over the operating range of –40 C to 85 C
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
[10]
Description
10 ns 15 ns
Min Max Min Max
Read cycle time 10 – 15 – ns
Address to data – 10 – 15 ns
Data hold from address change 3 – 3 – ns
CE LOW to data – 10 – 15 ns
OE LOW to data – 4.5 – 8 ns
[12, 13]
[12, 13]
[11]
[11]
0–0–ns
–5–8ns
3–3–ns
–5–8ns
0–0–ns
–10–15ns
OE LOW to low impedance
OE HIGH to High-Z
[11]
CE LOW to low impedance
CE HIGH to High-Z
[11]
CE LOW to power-up
CE HIGH to power-down
[13, 14]
Write cycle time 10 – 15 – ns
CE LOW to write end 7 – 12 – ns
Address setup to write end 7 – 12 – ns
Address hold from write end 0–0 – ns
Address setup to write start 0 – 0 – ns
WE pulse width 7 – 12 – ns
Data setup to write end 5 – 8 – ns
Data hold from write end 0 – 0 – ns
WE HIGH to low impedance
WE LOW to High-Z
[11]
[11]
3–3–ns
–5–8ns
Unit
Document Number: 002-10613 Rev. *C Page 8 of 17
Page 9
CY7C1049GN
Switching Waveforms
ADDRESS
DATA I/O
PREVIOUS DATA
OUT
VALID
DATA
OUT
VALID
t
RC
t
OHA
t
AA
t
RC
t
HZCE
t
PD
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
DATA
OUT
VALID
HIGH
IMPEDANCE
ADDRESS
CE
OE
DATA I /O
t
HZOE
SUPPLY
CURRENT
V
CC
I
SB
Notes
15. WE is HIGH for the read cycle.
16. Address valid prior to or coincident with CE
LOW transition.
Figure 5. Read Cycle No. 1 (Address Transition Controlled)
[15, 16]
Figure 6. Read Cycle No. 2 (OE Controlled)
[15, 16]
Document Number: 002-10613 Rev. *C Page 9 of 17
Page 10
CY7C1049GN
Switching Waveforms (continued)
ADDRESS
CE
WE
DATA I/O
OE
t
WC
t
SCE
t
AW
t
SA
t
PWE
t
HA
t
HD
t
HZOE
t
SD
DATAIN V AL ID
ADDRESS
CE
DATA I /O
t
WC
t
SCE
t
HD
t
SD
t
AW
t
HA
t
SA
t
PWE
t
LZWE
t
HZWE
WE
DATAIN VALID
Notes
17. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
18. Data I/O is in HI-Z state if CE
= VIH, or OE = VIH.
19. The minimum write cycle pulse width should be equal to sum of t
SD
and t
HZWE
.
Figure 7. Write Cycle No. 1 (CE Controlled)
[17, 18]
Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW)
[17, 18, 19]
Document Number: 002-10613 Rev. *C Page 10 of 17
Page 11
CY7C1049GN
Switching Waveforms (continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA IN VALID
NOTE 23
CE
1
ADDRESS
CE
2
WE
DATA I/O
OE
Notes
20. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
21. Data I/O is in HI-Z state if CE
= VIH, or OE = VIH.
22. Data I/O is high impedance if OE
= VIH.
23. During this period the I/Os are in output state. Do not apply input signals.
Figure 9. Write Cycle No. 3 (WE Controlled)
[20, 21, 22]
Document Number: 002-10613 Rev. *C Page 11 of 17
Page 12
CY7C1049GN
Truth Table
Note
24. The input voltage levels on these pins should be either at VIH or VIL.
CE OE WE I/O0–I/O
HX
[24]
[24]
X
HI-Z Power down Standby (ISB)
7
Mode Power
L L H Data out Read all bits Active (I
L X L Data in Write all bits Active (I
L H H HI-Z Selected, outputs disabled Active (I
CC
CC
CC
)
)
)
Document Number: 002-10613 Rev. *C Page 12 of 17
Page 13
CY7C1049GN
Ordering Information
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range: I = Industrial
Pb-free
Package Type: XX = ZS or V
ZS = 44-pin TSOP II; V= 36-pin Molded SOJ
Speed: XX = 10 ns
Voltage Range: XX = 30 or blank
30 = 2.2 V–3.6 V; no character = 4.5 V–5.5 V
Process Technology: GN = 65 nm
Data Width: 9 = × 8-bits
Density: 04 = 4-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CCY 1
-
XX I7 04 GN9
XX
XX
X
X
Speed
(ns)
10 2.2 V–3.6 V CY7C1049GN30-10ZSXI 51-85087 44-pin TSOP II Industrial
Voltage
Range
CY7C1049GN30-10ZSXIT 51-85087 44-pin TSOP II, Tape and Reel
CY7C1049GN30-10VXI 51-85090 36-pin Molded SOJ
CY7C1049GN30-10VXIT 51-85090 36-pin Molded SOJ, Tape and Reel
4.5 V–5.5 V CY7C1049GN-10VXI 51-85090 36-pin Molded SOJ
CY7C1049GN-10VXIT 51-85090 36-pin Molded SOJ, Tape and Reel
Ordering Code
Package
Diagram
Package Type (all Pb-free)
Operating
Ordering Code Definitions
Range
Document Number: 002-10613 Rev. *C Page 13 of 17
Page 14
CY7C1049GN
Package Diagrams
51-85087 *E
51-85090 *G
Figure 10. 44-pin TSOP Z44-II Package Outline, 51-85087
Figure 11. 36-pin SOJ V36.4 (Molded) Package Outline, 51-85090
Document Number: 002-10613 Rev. *C Page 14 of 17
Page 15
CY7C1049GN
Acronyms Document Conventions
Acronym Description
BHE byte high enable
BLE
CE
CMOS complementary metal oxide semiconductor
I/O input/output
OE
SRAM static random access memory
TSOP thin small outline package
TTL transistor-transistor logic
VFBGA very fine-pitch ball grid array
WE
byte low enable
chip enable
output enable
write enable
Units of Measure
Symbol Unit of Measure
°C Degrees Celsius
MHz megahertz
A microamperes
s microseconds
mA milliamperes
mm millimeter
ns nanoseconds
ohms
% percent
pF picofarads
V volts
W watts
Document Number: 002-10613 Rev. *C Page 15 of 17
Page 16
CY7C1049GN
Document History Page
Document Title: CY7C1049GN, 4-Mbit (512K words × 8-bit) Static RAM
Document Number: 002-10613
Rev. ECN No.
Orig. of
Change
** 5074703 NILE 01/06/2016 New data sheet.
*A 5082587 NILE 01/12/2016 Updated Logic Block Diagram – CY7C1049GN.
*B 5437570 NILE 09/15/2016 Updated DC Electrical Characteristics:
*C 5966829 NILE 11/14/2017 Updated Switching Waveforms:
Submission
Date
Description of Change
Updated Ordering Information:
Updated part numbers.
Removed details of V
Test Condition “V
Added details of V
Test Condition “V
Added details of V
Test Condition “V
Changed minimum value of V
from 2.2 V to 2 V.
parameter corresponding to “2.7 V to 3.6 V” and
OH
= Min, IOH = –4.0 mA”.
CC
parameter corresponding to “2.7 V to 3.0 V” and
OH
= Min, IOH = –4.0 mA”.
CC
parameter corresponding to “3.0 V to 3.6 V” and
OH
= Min, IOH = –4.0 mA”.
CC
parameter corresponding to “4.5 V to 5.5 V”
IH
Updated Note 3 (Replaced “2 ns” with “20 ns”).
Updated Ordering Information:
Updated part numbers.
Updated to new template.
Updated Figure 6.
Updated Figure 7.
Updated Figure 8.
Updated Figure 9.
Updated to new template.
Completing Sunset Review.
Document Number: 002-10613 Rev. *C Page 16 of 17
Page 17
CY7C1049GN
Sales, Solutions, and Legal Information
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© Cypress Se miconductor Corporation, 2016-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and trea ties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
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permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the applicatio n or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application mad e of th is inf ormat ion and any resulti ng pro duct. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-10613 Rev. *C Revised November 14, 2017 Page 17 of 17
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