Cypress CY7C1041DV33 User Manual
CY7C1041DV33
4 Mbit (256K x 16) Static RAM
Features
14
15
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
256K × 16
A
0
A
11
A13A
12
AAA
16
A
17
A
9
A
10
IO0–IO
7
OE
IO8–IO
15
CE
WE
BLE
BHE
Logic Block Diagram
Note
1. For guidelines on SRAM system design, refer to the “System Design Guidelines” Cypress application note, availa ble at www.cypress.com.
■ Pin and function compatible with CY7C1041CV33
■ High speed
❐ t
= 10 ns
AA
■ Low active power
❐ I
= 90 mA at 10 ns (industrial)
CC
■ Low CMOS standby power
❐ I
= 10 mA
SB2
■ 2.0V data retention
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in Pb-free 48-ball VFBGA, 44-pin (400-mil) molded
SOJ, and 44-pin TSOP II packages
Functional Description
The CY7C1041DV33
organized as 256K words by 16 bits. T o write to the device, take
Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte
LOW Enable (BLE
is written into the location specified on the address pins (A
). If Byte HIGH Enable (BHE) is LOW, then data from IO pins
A
17
(IO
to IO15) is written into the location specified on the address
8
pins (A
to A17).
0
To read from the device, take Chip Enable (CE
Enable (OE
BLE
) LOW while forcing the Write Enable (WE) HIGH. If
is LOW, then data from the memory location specified by
the address pins appears on IO
from memory appears on IO
page 9 for a complete description of read and write modes.
The input and output pins (IO
impedance state when the device is deselected (CE
outputs are disabled (OE
(BHE
, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
The CY7C1041DV33 is available in a standard 44-pin 400-mil
wide SOJ and 44-pin TSOP II package with center power and
ground (revolutionary) pinout and a 48-ball fine-pitch ball g rid
array (FBGA) package.
[1]
is a high performance CMOS Static RAM
) is LOW, then data from IO pins (IO0 to IO7)
to
0
) and Output
to IO7. If BHE is LOW, then data
0
to IO15. See the Truth Table on
8
to IO15) are placed in a high
0
HIGH),
HIGH), BHE and BLE are disabled
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05473 Rev. *E Revised July 17, 2008
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CY7C1041DV33
Selection Guide
1
2
3
4
5
6
7
8
9
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
A
17
18
17
20
19
27
28
25
26
22
21
23
24
A
16
A
15
A
0
A
1
A
2
A
3
A
4
A
7
A
6
A
14
A
13
A
12
A
11
A
9
A
8
A
10
OE
BHE
BLE
CE
WE
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
IO
8
IO
9
IO
10
IO
11
IO
12
IO
13
IO
14
IO
15
V
CC
V
CC
V
SS
V
SS
NC
10
A
5
WE
V
CC
A
11
A
10
NC
A
6
A
0
A
3
CE
IO
2
IO
0
IO
1
A
4
A
5
IO
3
IO
5
IO
4
IO
6
IO
7
V
SS
A
9
A
8
OE
V
SS
A
7
IO
8
BHE
NC
A
17
A
2
A
1
BLE
V
CC
IO
9
IO
10
IO
11
IO
12
IO
13
IO
14
IO
15
A
15
A
14
A
13
A
12
NC
NC
NC
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A
16
WE
V
CC
A
11
A
10
NC
A
6
A
0
A
3
CE
IO
10
IO
8
IO
9
A
4
A
5
IO
11
IO
13
IO
12
IO
14
IO
15
V
SS
A
9
A
8
OE
V
SS
A
7
IO
0
BHE
NC
A
17
A
2
A
1
BLE
V
CC
IO
2
IO
1
IO
3
IO
4
IO
5
IO
6
IO
7
A
15
A
14
A
13
A
12
NC
NC
NC
3
2
6
5
4
1
D
E
B
A
C
F
G
H
A
16
Notes
2. Automotive product information is Preliminary.
3. NC pins are not connected on the die.
4. Pinout 1 is compliant with CY7C1041CV33 and pinout 2 is JE DEC compliant . The diff erence betwe en the two is that the hig her and lower byte IOs (IO
[7:0]
and IO
[15:8]
balls) are swapped.
Description –10 (Industrial) –12 (Automotive)
Maximum Access Time 10 12 ns
Maximum Operating Current 90
95 mA
Maximum CMOS Standby Current 10 15 mA
[2]
Unit
Pin Configuration
Figure 1. 44-Pin SOJ/TSOP II
[3, 4]
Figure 2. 48-Ball VFBGA (Pinout 1)
Document #: 38-05473 Rev. *E Page 2 of 13
Figure 3. 48-Ball VFBGA (Pinout 2)
[3, 4]
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CY7C1041DV33
Maximum Ratings
Exceeding maximum ratings may shorten the us eful life of the
device. These user guidelines are not tested.
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied ............................................–55°C to +125°C
Supply Voltage on V
DC Voltage Applied to Outputs
in High-Z State
DC Input Voltage
Relative to GND
CC
[5]
.................................. ..–0.3V to VCC +0.3V
[5]
................................–0.3V to VCC +0.3V
[5]
....–0.3V to +4.6V
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
I
SB2
OH
OL
IH
IL
[5]
[5]
Output HIGH Voltage VCC = Min, IOH = –4.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min, IOL = 8.0 mA 0.4 0.4 V
Input HIGH Voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 V
Input LOW Voltage –0.3 0.8 –0.3 0.8 V
Input Leakage Current GND < VI < V
Output Leakage
GND < V
Current
VCC Operating
VCC = Max, f = f
Supply Current
Automatic CE Power Down
Current—TTL Inputs
Automatic CE Power Down
Current—CMOS Inputs
Max VCC, CE > V
VIN > VIH or
< VIL, f = f
V
IN
Max VCC,
CE
> VCC – 0.3V,
V
> VCC – 0.3V,
IN
< 0.3V, f = 0
or V
IN
CC
< VCC, Output Disabled –1 +1 –1 +1 μA
OUT
= 1/tRC100 MHz 90 -mA
MAX
IH
MAX
Current into Outputs (LOW) ........................................20 mA
Static Discharge Voltage............................................>2001V
(MIL-STD-883, Method 3015)
Latch Up Current.....................................................>200 mA
Operating Range
Range
Industrial –40°C to +85°C3.3V ± 0.3V 10 ns
Automotive –40°C to +125°C 3.3V ± 0.3V 12 ns
83 MHz 80
66 MHz 70
40 MHz 60
Ambient
Temperature
V
CC
Speed
–10 (Industrial) –12 (Automotive)
Min Max Min Max
–1 +1 –1 +1 μA
95 mA
85 mA
75 mA
20 25 mA
10
15 mA
Unit
Note
5. Minimum voltage is –2.0V and V
(max) = VCC + 2V for pulse durations of less than 20 ns.
IH
Document #: 38-05473 Rev. *E Page 3 of 13
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CY7C1041DV33
Capacitance
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
Rise Time: 1 V/ns
Fall Time: 1 V/ns
30 pF*
OUTPUT
Z = 50Ω
50Ω
1.5V
(b)
(a)
3.3V
OUTPUT
5 pF
(c)
R 317Ω
R2
351Ω
High-Z Characteristics
10 ns device
Notes
6. Tested initially and after any design or process changes that may affect these parameters.
7. AC characteristics (except High-Z) are tested using the load conditions shown in AC Test Loads and Waveforms (a). High-Z characteristics are tested for all speeds
using the test load shown in (c).
[6]
Parameter Description Test Conditions Max Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V 8 pF
IO Capacitance 8 pF
Thermal Resistance
[6]
Parameter Description Test Condit ion s
Θ
Θ
Thermal Resistance (Junction
JA
to Ambient)
Thermal Resistance (Junction
JC
to Case)
Still Air, soldered on a 3 × 4.5 inch,
four layer printed circuit board
AC Test Loads and Waveforms
The AC test loads and waveform diagram follows.
[7]
FBGA
Package
SOJ
Package
TSOP II
Package
27.89 57.91 50.66 °C/W
14.74 36.73 17.17 °C/W
Unit
Document #: 38-05473 Rev. *E Page 4 of 13
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