Cypress CY7C1034DV33 User Manual

CY7C1034DV33

6-Mbit (256K X 24) Static RAM

Features

COLUMN

DECODER

ROW DECODER

SENSE AMPS

INPUT BUFFER

256K x 24

ARRAY

IO0 – IO

23

OE

CE1, CE2, CE

3

WE

CONTROL LOGIC

Logic Block Diagram

A

(9:0)

A

(17:10)

Functional Description

■ High speed
❐ t

= 10 ns

AA

■ Low active power
❐ I

= 175 mA at 10 ns

CC

■ Low CMOS standby power
❐ I

= 25 mA

SB2

■ Operating voltages of 3.3 ± 0.3V

■ 2.0V data retention

■ Automatic power down when deselected

■ TTL compatible inputs and outputs

■ Easy memory expansion with CE

■ Available in Pb-free standard 119-Ball PBGA

, CE2, and CE3 features

1

The CY7C1034DV33 is a high performance CMOS static RAM
organized as 256K words by 24 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.

To write to the device, enable the chip (CE
and CE

LOW) while forcing the Write Enable (WE) input LOW.

3

To read from the device, enable the chip by taking CE
HIGH, and CE3 LOW, while forcing the Output Enable (OE) LOW
and the Write Enable (WE

) HIGH. See the Truth Table on page

LOW, CE2 HIGH,

1

LOW, CE

1

7 for a complete description of Read and Write modes.

The 24 IO pins (IO
when the device is deselected (CE
HIGH) or when the output enable (OE) is HIGH during a write
operation. (CE

to IO23) are placed in a high impedance state

0

LOW, CE2 HIGH, CE3 LOW, and WE LOW).

1

HIGH, CE2 LOW, or CE

1

2

3

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-08351 Rev. *C Revised January 16, 2009

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CY7C1034DV33

Selection Guide

1 2 3 4 5 6 7

A NCAAAAANC

B NC A A CE

1

AANC

C IO

12

NC CE

2

ACE3NC IO

0

D IO

13

V

DD

V

SS

V

SS

V

SS

V

DD

IO

1

E IO

14

V

SS

V

DD

V

SS

V

DD

V

SS

IO

2

F IO

15

V

DD

V

SS

V

SS

V

SS

V

DD

IO

3

G IO

16

V

SS

V

DD

V

SS

V

DD

V

SS

IO

4

H IO

17

V

DD

V

SS

V

SS

V

SS

V

DD

IO

5

J NC V

SS

V

DD

V

SS

V

DD

V

SS

NC

K IO

18

V

DD

V

SS

V

SS

V

SS

V

DD

IO

6

L IO

19

V

SS

V

DD

V

SS

V

DD

V

SS

IO

7

M IO

20

V

DD

V

SS

V

SS

V

SS

V

DD

IO

8

N IO

21

V

SS

V

DD

V

SS

V

DD

V

SS

IO

9

P IO

22

V

DD

V

SS

V

SS

V

SS

V

DD

IO

10

R IO

23

NC NC NC NC NC IO

11

T NC A A WE AANC

U NC A A OE AANC

Note

1. NC pins are not connected on the die.

Description –10 Unit

Maximum Access Time 10 ns

Maximum Operating Current 175 mA

Maximum CMOS Standby Current 25 mA

Pin Configuration

Figure 1. 119-Ball PBGA Top View

[1]

Document Number: 001-08351 Rev. *C Page 2 of 9

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CY7C1034DV33

Maximum Ratings

Notes

2. V

IL

(min) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns.

3. CE

refers to a combination of CE1, CE2, and CE3. CE is active LOW when CE1 is LOW, CE2 is HIGH, and CE3 is LOW. CE is HIGH when CE1 is HIGH or CE2 is LOW

or CE

3

is HIGH.

Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with

Power Applied ............................................ –55°C to +125°C

Supply Voltage on V

DC Voltage Applied to Outputs
in High Z State

Relative to GND

CC

[2]

................................... –0.5V to VCC + 0.5V

[2]

....–0.5V to +4.6V

DC Electrical Characteristics

Over the operating range

DC Input Voltage

[2]

............................... –0.5V to VCC + 0.5V

Current into Outputs (LOW) ........................................ 20 mA

Static Discharge Voltage............. ...............................>2001V

(MIL-STD-883, Method 3015)

Latch up Current...................................................... >200 mA

Operating Range

Range

Industrial –40°C to +85°C3.3V ± 0.3V

Ambient

Temperature

V

CC

Parameter Description Test Conditions

V

V

V

V

I

I

I

I

I

OH

OL

IH

IL

IX

OZ

CC

SB1

SB2

[2]

Output HIGH Voltage VCC = Min, IOH = –4.0 mA 2.4 V

Output LOW Voltage VCC = Min, IOL = 8.0 mA 0.4 V

Input HIGH Voltage 2.0 VCC + 0.3 V

Input LOW Voltage –0.3 0.8 V

Input Leakage Current GND < VI < V

Output Leakage Current GND < V

VCC Operating Supply
Current

Automatic CE Power Down
Current — TTL Inputs

Automatic CE Power Down
Current — CMOS Inputs

VCC = Max, f = f

= 0 mA CMOS levels

I

OUT

Max VCC, CE1, CE3 > V
V

> VIH or VIN < VIL, f = f

IN

Max VCC, CE1, CE3 > VCC – 0.3V, CE2 < 0.3V,
V

> VCC – 0.3V, or VIN < 0.3V, f = 0

IN

CC

< VCC, output disabled –1 +1 μA

OUT

= 1/tRC,

MAX

IH, CE2

MAX

[3]

< VIL,

–10

Min Max

–1 +1 μA

175 mA

30 mA

25 mA

Capacitance

Tested initially and after any design or process changes that may affect these parameters.

Parameter Description Test Conditions Max Unit

C

C

IN

OUT

Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V 8 pF

IO Capacitance 10 pF

Thermal Resistance

Tested initially and after any design or process changes that may affect these parameters.

Parameter Description Test Conditions

Θ

JA

Θ

JC

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

Still air, soldered on a 3 × 4.5 inch,
four layer printed circuit board

119-Ba ll

PBGA

20.31 °C/W

8.35 °C/W

Unit

Unit

Document Number: 001-08351 Rev. *C Page 3 of 9

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