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CY7C1034DV33
User Manual
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Cypress CY7C1034DV33 User Manual

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CY7C1034DV33
6-Mbit (256K X 24) Static RAM

Features

COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
256K x 24
ARRAY
IO0 – IO
23
OE
CE1, CE2, CE
3
WE
CONTROL LOGIC

Logic Block Diagram

A
(9:0)
A
(17:10)

Functional Description

■ High speed ❐ t
= 10 ns
■ Low active power ❐ I
= 175 mA at 10 ns
CC
■ Low CMOS standby power ❐ I
= 25 mA
SB2
■ Operating voltages of 3.3 ± 0.3V
■ 2.0V data retention
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
■ Easy memory expansion with CE
■ Available in Pb-free standard 119-Ball PBGA
, CE2, and CE3 features
1
The CY7C1034DV33 is a high performance CMOS static RAM organized as 256K words by 24 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected.
To write to the device, enable the chip (CE and CE
LOW) while forcing the Write Enable (WE) input LOW.
3
To read from the device, enable the chip by taking CE HIGH, and CE3 LOW, while forcing the Output Enable (OE) LOW and the Write Enable (WE
) HIGH. See the Truth Table on page
LOW, CE2 HIGH,
1
LOW, CE
1
7 for a complete description of Read and Write modes.
The 24 IO pins (IO when the device is deselected (CE HIGH) or when the output enable (OE) is HIGH during a write operation. (CE
to IO23) are placed in a high impedance state
0
LOW, CE2 HIGH, CE3 LOW, and WE LOW).
1
HIGH, CE2 LOW, or CE
1
2
3
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-08351 Rev. *C Revised January 16, 2009
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CY7C1034DV33

Selection Guide

1 2 3 4 5 6 7
A NCAAAAANC
B NC A A CE
1
AANC
C IO
12
NC CE
2
ACE3NC IO
0
D IO
13
V
DD
V
V
V
V
DD
IO
1
E IO
14
V
V
DD
V
V
DD
V
IO
2
F IO
15
V
DD
V
V
V
V
DD
IO
3
G IO
16
V
V
DD
V
V
DD
V
IO
4
H IO
17
V
DD
V
V
V
V
DD
IO
5
J NC V
V
DD
V
V
DD
V
NC
K IO
18
V
DD
V
V
V
V
DD
IO
6
L IO
19
V
V
DD
V
V
DD
V
IO
7
M IO
20
V
DD
V
V
V
V
DD
IO
8
N IO
21
V
V
DD
V
V
DD
V
IO
9
P IO
22
V
DD
V
V
V
V
DD
IO
10
R IO
23
NC NC NC NC NC IO
11
T NC A A WE AANC
U NC A A OE AANC
Note
1. NC pins are not connected on the die.
Description –10 Unit
Maximum Access Time 10 ns
Maximum Operating Current 175 mA
Maximum CMOS Standby Current 25 mA

Pin Configuration

Figure 1. 119-Ball PBGA Top View
[1]
Document Number: 001-08351 Rev. *C Page 2 of 9
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CY7C1034DV33

Maximum Ratings

Notes
2. V
IL
(min) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns.
3. CE
refers to a combination of CE1, CE2, and CE3. CE is active LOW when CE1 is LOW, CE2 is HIGH, and CE3 is LOW. CE is HIGH when CE1 is HIGH or CE2 is LOW
or CE
3
is HIGH.
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage on V
DC Voltage Applied to Outputs in High Z State
Relative to GND
CC
[2]
................................... –0.5V to VCC + 0.5V
[2]
....–0.5V to +4.6V

DC Electrical Characteristics

Over the operating range
DC Input Voltage
[2]
............................... –0.5V to VCC + 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage............. ...............................>2001V
(MIL-STD-883, Method 3015)
Latch up Current...................................................... >200 mA

Operating Range

Range
Industrial –40°C to +85°C3.3V ± 0.3V
Ambient
Temperature
V
CC
Parameter Description Test Conditions
V
V
V
V
I
I
I
I
I
OH
OL
IH
IL
IX
OZ
CC
SB1
SB2
[2]
Output HIGH Voltage VCC = Min, IOH = –4.0 mA 2.4 V
Output LOW Voltage VCC = Min, IOL = 8.0 mA 0.4 V
Input HIGH Voltage 2.0 VCC + 0.3 V
Input LOW Voltage –0.3 0.8 V
Input Leakage Current GND < VI < V
Output Leakage Current GND < V
VCC Operating Supply Current
Automatic CE Power Down Current — TTL Inputs
Automatic CE Power Down Current — CMOS Inputs
VCC = Max, f = f
= 0 mA CMOS levels
I
OUT
Max VCC, CE1, CE3 > V V
> VIH or VIN < VIL, f = f
IN
Max VCC, CE1, CE3 > VCC – 0.3V, CE2 < 0.3V, V
> VCC – 0.3V, or VIN < 0.3V, f = 0
IN
CC
< VCC, output disabled –1 +1 μA
OUT
= 1/tRC,
MAX
IH, CE2
MAX
[3]
< VIL,
–10
Min Max
–1 +1 μA
175 mA
30 mA
25 mA

Capacitance

Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V 8 pF
IO Capacitance 10 pF

Thermal Resistance

Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions
Θ
JA
Θ
JC
Thermal Resistance (Junction to Ambient)
Thermal Resistance (Junction to Case)
Still air, soldered on a 3 × 4.5 inch, four layer printed circuit board
119-Ba ll
PBGA
20.31 °C/W
8.35 °C/W
Unit
Unit
Document Number: 001-08351 Rev. *C Page 3 of 9
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CY7C1034DV33
Figure 2. AC Test Loads and Waveform
90%
10%
3.0V
GND
90%
10%
All input pulses
3.3V
OUTPUT
5 pF*
(a)
(b)
R1 317 Ω
R2
351Ω
Fall Time:> 1V/ns
(c)
OUTPUT
50Ω
Z
0
= 50Ω
V
TH
= 1.5V
30 pF*
*Capacitive Load consists of all components of the test environment
Rise Time > 1V/ns
*Including jig and scope
Notes
4. Valid SRAM operation does not occur until the power supplies reach the minimum operating V
DD
(3.0V). 100 μs (t
power
) after reaching the minimum operating VDD,
normal SRAM operation begins including reduction in VDD to the data retention (V
CCDR
, 2.0V) voltage.
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output loading as shown in part a) of the AC Test Loads and Waveform
[4]
, unless specified otherwise.
6. t
POWER
gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
7. t
HZOE
, t
HZCE
, t
HZWE
, t
LZOE
, t
LZCE
, and t
LZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady
state voltage.
8. These parameters are guaranteed by design and are not tested.
[4]

AC Switching Characteristics

Over the operating range
Parameter Description
Read Cycle
[6]
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Document Number: 001-08351 Rev. *C Page 4 of 9
[5]
–10
Min Max
VCC(Typical) to the First Access 100 μs
Read Cycle Time 10 ns
Address to Data Valid 10 ns
Data Hold from Address Change 3 ns
CE Active LOW to Data Valid
[3]
10 ns
OE LOW to Data Valid 5 ns
OE LOW to Low Z
OE HIGH to High Z
CE Active LOW to Low Z
CE Deselect HIGH to High Z
CE Active LOW to Power Up
CE Deselect HIGH to Power Down
[7]
[7]
[3, 7]
[3, 7]
[3, 8]
[3, 8]
1ns
5ns
3ns
5ns
0ns
10 ns
Unit
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CY7C1034DV33
AC Switching Characteristics (continued)
3.0V3.0V
t
CDR
V
DR
> 2V
DATA RETENTION MODE
t
R
CE
V
CC
Notes
9. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE2 HIGH, CE3 LOW, and WE LOW. Chip enables must be active and WE must be LOW to initiate a write and the transition of any of these signals terminates the write. The input data setup and hold timing are referenced to the leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle No. 3 (WE
controlled, OE LOW) is the sum of t
HZWE
and tSD.
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 50 μs or stable at V
CC(min)
> 50 μs.
Over the operating range
Parameter Description
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
[9, 10]
[5]
Write Cycle Time 10 ns
CE Active LOW to Write End
[3]
Address Setup to Write End 7 ns
Address Hold from Write End 0 ns
Address Setup to Write Start 0 ns
WE Pulse Width 7 ns
Data Setup to Write End 5.5 ns
Data Hold from Write End 0 ns
WE HIGH to Low Z
WE LOW to High Z
[7]
[7]

Data Retention Characteristics

Over the operating range
Parameter Description Conditions
V
DR
I
CCDR
t
CDR
[12]
t
R
[11]
VCC for Data Retention 2 V
Data Retention Current9 V
= 2V, CE1, CE3 > VCC – 0.2V,
CC
CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V
Chip Deselect to Data Retention Time 0 ns
Operation Recovery Time t
–10
Min Max
Unit
7ns
3ns
5ns
[3]
Min Typ Max Unit
25 mA
RC
ns
Figure 3. Data Retention Waveform
Document Number: 001-08351 Rev. *C Page 5 of 9
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Switching Waveforms

PREVIOUS DATA VALID DATA VALID
RC
t
AA
t
OHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
ICC
ISB
IMPEDANCE
OE
CE
ADDRESS
DATA OUT
V
CC
SUPPLY
CURRENT
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
t
SCE
CE
WE
DATA IO
ADDRESS
Notes
13. Device is continuously selected. OE
, CE = VIL.
14. WE
is HIGH for read cycle.
15. Address valid before or similar to CE
transition LOW.
16. Data IO is high impedance if OE
= VIH.
17. If CE
goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Figure 4. Read Cycle No. 1 (Address Transition Controlled)
[13, 14]
Figure 5. Read Cycle No. 2 (OE Controlled)
Figure 6. Write Cycle No. 1 (CE Controlled)
[3, 14, 15]
[3, 16, 17]
Document Number: 001-08351 Rev. *C Page 6 of 9
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CY7C1034DV33
Switching Waveforms (continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATAINVALID
NOTE 18
CE
ADDRESS
WE
DATA IO
OE
DATA VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
NOTE 18
CE
ADDRESS
WE
DATA IO
Note
18. During this period, the IOs are in the output state and input signals are not applied.
Figure 7. Write Cycle No. 2 (WE
Controlled, OE HIGH During Write)
[3, 16, 17]
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW)

Truth Table

CE
HXXXXHigh Z Power Down Standby (I
CE
1
CE
2
OE WE IO0 – IO
3
X L X X X High Z Power Down Standby (I
X X H X X High Z Power Down Standby (I
L H L L H Full Data Out Read Active (ICC)
L H L X L Full Data In Write Active (I
L H L H H High Z Selected, Outputs Disabled Active (I
Document Number: 001-08351 Rev. *C Page 7 of 9
23
[3, 17]
Mode Power
CC
CC
)
)
)
)
)
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CY7C1034DV33

Ordering Information

51-85115-*B
Speed
(ns)
10 CY7C1034DV33-10BGXI 51-85115 119-Ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-Free) Industrial
Ordering Code
Package
Name
Package Type
Operating

Package Diagram

Figure 9. 119-Ball PBGA (14 x 22 x 2.4 mm)
Range
Document Number: 001-08351 Rev. *C Page 8 of 9
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Document History Page

Document Title: CY7C1034DV33 6-Mbit (256K X 24) Static RAM Document Number: 001-08351
REV. ECN NO.
Orig. of
Change
Submission
Date
Description of Change
** 469517 NXR See ECN New data sheet
*A 499604 NXR See ECN Added note 1 for NC pins
Changed I Updated Test Condition for I Added note for t Table on page 4
specification from 150 mA to 185 mA
CC
ACE
, t
LZCE
in DC Electrical Characteristics table
CC
, t
, tPU, tPD, t
HZCE
in AC Switching Characteristics
SCE
*B 1462586 VKN/SFV See ECN Converted from preliminary to final
Updated block diagram Changed I Updated thermal specs
specification from 185 mA to 225 mA
CC
*C 2644842 VKN/PYRS 01/23/09 Replaced Commercial range with the Industrial
Replaced 8 ns speed with 10 ns

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© Cypress Semiconductor Corporation, 2006-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-08351 Rev. *C Revised January 16, 2009 Page 9 of 9
All product and company names mentioned in this document are the trademarks of their respective holders.
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