Cypress CY7C1024DV33 User Manual

CY7C1024DV33

3-Mbit (128K X 24) Static RAM

Features

Logic Block Diagram

COLUMN

DECODER

ROW DECODER

SENSE AMPS

INPUT BUFFER

128K x 24

ARRAY

I/O0 – I/O

23

OE

CE1, CE2, CE

3

WE

CONTROL LOGIC

A

(9:0)

A

(16:10)

■

High speed

❐

tAA = 10 ns

■

Low active power

❐

ICC = 175 mA at 10 ns

■

Low CMOS standby power

❐

I

= 25 mA

SB2

■

Operating voltages of 3.3 ± 0.3V

■

2.0V data retention

■

Automatic power down when deselected

■

TTL compatible inputs and outputs

■

Easy memory expansion with CE1, CE2, and CE3 features

■

Available in Pb-free standard 119-ball PBGA

Functional Description

The CY7C1024DV33 is a high performance CMOS static RAM
organized as 128K words by 24 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.

To write to the device, enable the chip (CE
and CE

LOW), while forcing the Write Enable (WE) input LOW.

3

T o read from the device, enable the chip by taking CE
HIGH, and CE3 LOW while forcing the Output Enable (OE) LOW
and the Write Enable (WE

) HIGH. See the Truth Table on page

7 for a complete description of Read and Write modes.
The 24 I/O pins (I/O

state when the device is deselected (CE
CE

HIGH) or when the output enable (OE) is HIGH during a

3

write operation. (CE
LOW).

to I/O23) are placed in a high impedance

0

LOW, CE2 HIGH, CE3 LOW, and WE

1

LOW, CE2 HIGH,

1

LOW, CE

1

HIGH, CE2 LOW, or

1

2

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-08353 Rev. *C Revised November 6, 2008

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CY7C1024DV33

Selection Guide

1 2 3 4 5 6 7

A NCAAAAANC
B NC A A CE

1

AANC

C I/O

12

NC CE

2

NC CE

3

NC I/O

0

D I/O

13

V

DD

V

SS

V

SS

V

SS

V

DD

I/O

1

E I/O

14

V

SS

V

DD

V

SS

V

DD

V

SS

I/O

2

F I/O

15

V

DD

V

SS

V

SS

V

SS

V

DD

I/O

3

G I/O

16

V

SS

V

DD

V

SS

V

DD

V

SS

I/O

4

H I/O

17

V

DD

V

SS

V

SS

V

SS

V

DD

I/O

5

J NC V

SS

V

DD

V

SS

V

DD

V

SS

NC

K I/O

18

V

DD

V

SS

V

SS

V

SS

V

DD

I/O

6

L I/O

19

V

SS

V

DD

V

SS

V

DD

V

SS

I/O

7

M I/O

20

V

DD

V

SS

V

SS

V

SS

V

DD

I/O

8

N I/O

21

V

SS

V

DD

V

SS

V

DD

V

SS

I/O

9

P I/O

22

V

DD

V

SS

V

SS

V

SS

V

DD

I/O

10

R I/O

23

NC NC NC NC NC I/O

11

T NC A A WE AANC
U NC A A OE AANC

Note

1. NC pins are not connected on the die.

Description –10 Unit

Maximum Access Time 10 ns
Maximum Operating Current 175 mA
Maximum CMOS Standby Current 25 mA

Pin Configuration

Figure 1. 119-Ball PBGA Top View

[1]

Document Number: 001-08353 Rev. *C Page 2 of 9

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CY7C1024DV33

Maximum Ratings

Notes

2. V

IL

(min) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns.

3. CE

refers to a combination of CE1, CE2, and CE3. CE is LOW when CE1, CE3 are LOW and CE2 is HIGH. CE is HIGH when CE1 is HIGH, or CE2 is LOW, or CE3 is HIGH.

Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

DC Input Voltage

Current into Outputs (LOW) ..................... ... ................20 mA

Static Discharge Voltage............................................>2001V

(MIL-STD-883, Method 3015)

Latch Up Current.....................................................>200 mA

Power Applied ............................................ –55°C to +125°C

Supply Voltage on V
DC Voltage Applied to Outputs

in High Z State

Relative to GND

CC

[2]

...................................–0.5V to VCC + 0.5V

[2]

....–0.5V to +4.6V

Operating Range

DC Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions

V
V
V
V
I
I
I

I

I

OH
OL
IH

IL
IX
OZ
CC

SB1

SB2

[2]

Output HIGH Voltage VCC = Min, IOH = –4.0 mA 2.4 V
Output LOW Voltage VCC = Min, IOL = 8.0 mA 0.4 V
Input HIGH Voltage 2.0 VCC + 0.3 V
Input LOW Voltage –0.3 0.8 V
Input Leakage Current GND < VI < V
Output Leakage Current GND < V
VCC Operating Supply

Current
Automatic CE Power Down

Current —TTL Inputs
Automatic CE Power Down

Current — CMOS Inputs

VCC = Max, f = f
I

= 0 mA CMOS levels

OUT

Max VCC, CE > V
VIN > VIH or VIN < VIL, f = f

Max VCC, CE > VCC – 0.3V,

> VCC – 0.3V, or VIN < 0.3V, f = 0

V

IN

CC

< VCC, output disabled –1 +1 μA

OUT

= 1/t

MAX

RC

IH

MAX

[2]

...............................–0.5V to VCC + 0.5V

Range

Ambient

T emperature

V

CC

Industrial –40°C to +85°C3.3V ± 0.3V

[3]

–10

Min Max

Unit

–1 +1 μA

175 mA

30 mA

25 mA

Capacitance

Tested initially and after any design or process changes that may affect these parameters.

Parameter Description Test Conditions Max Unit

C
C

IN

OUT

Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V 8 pF
I/O Capacitance 10 pF

Thermal Resistance

Tested initially and after any design or process changes that may affect these parameters.

Parameter Description Test Conditions

Θ

Θ

Thermal Resistance

JA

(Junction to Ambient)
Thermal Resistance

JC

(Junction to Case)

Still air, soldered on a 3 × 4.5 inch,
four layer printed circuit board

Document Number: 001-08353 Rev. *C Page 3 of 9

119-Ball

PBGA

20.31 °C/W

8.35 °C/W

Unit

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