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CY7C1021D-10ZSXI
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CYPRESS CY7C1021D-10ZSXI Datasheet

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Page 1
CY7C1021D
1-Mbit (64 K × 16) Static RAM
1-Mbit (64 K × 16) Static RAM
64K x 16
RAM Array
I/O
0
–I/O
7
ROW DECODER
A
7
A
6
A
5
A
4
A
3
A
0
COLUMN DECODER
A
9
A10A11A
12
A13A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
2
A
1
I/O8–I/O
15
CE
WE
BLE
BHE
A
8

Logic Block Diagram

Features

■ Temperature Ranges: ❐ Industrial: –40 °C to 85 °C
❐ Automotive-A: –40 °C to 85 °C
■ Pin and Function Compatible with CY7C1021B
■ High Speed ❐ t
= 10 ns
AA
■ Low Active Power ❐ I
= 80 mA at 10 ns
CC
■ Low CMOS Standby Power ❐ I
= 3 mA
SB2
■ 2.0 V Data Retention
■ Automatic Power Down when Deselected
■ CMOS for Optimum Speed and Power
■ Independent Control of Upper and Lower Bits
■ Available in Pb-free 44-pin 400-Mil Wide Molded SOJ and
44-pin TSOP II Packages

Functional Description

The CY7C1021D is a high performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an
automatic power down feature that significantly reduces power consumption when deselected. The input and output pins (I/O through I/O15) are placed in a high impedance state when the device is deselected (CE
HIGH), outputs are disabled (OE HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW and WE LOW).
Write to the device by taking Chip Enable (CE) and Write Enable
) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
(WE from I/O pins (I/O specified on the address pins (A Enable (BHE I/O
) is written into the location specified on the address pins
15
(A
through A15).
0
Read from the device by taking Chip Enable (CE Enable (OE
) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE location specified by the address pins appears on I/O Byte High Enable (BHE appears on I/O complete description of read and write modes.
through I/O7), is written into the location
0
) is LOW, then data from I/O pins (I/O8 through
through A15). If Byte High
0
) and Output
) is LOW, then data from the memory
to I/O7. If
to I/O15. See the Truth Table on page 10 for a
) is LOW, then data from memory
8
0
The CY7C1021D device is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that require CMOS I/P levels. Please see Electrical
Characteristics on page 4 for more details and suggested
alternatives.
0
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 38-05462 Rev. *M Revised June 19, 2013
Page 2
CY7C1021D

Contents

Pin Configurations ........................................................... 3
Selection Guide ................................................................ 3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics .......................................6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ......................................................................10
Ordering Information ......................................................11
Ordering Code Definitions .........................................11
Package Diagrams ..........................................................12
Acronyms ........................................................................14
Document Conventions .................................................14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products ....................................................................17
PSoC® Solutions ......................................................17
Cypress Developer Community .................................17
Technical Support ..................................................... 17
Document Number: 38-05462 Rev. *M Page 2 of 17
Page 3
CY7C1021D

Pin Configurations

1 2 3 4 5 6 7 8 9
11
14
31
32
36 35 34 33
37
40 39 38
12 13
41
44 43 42
16
15
29
30
A
5
18
17
20
19
27
28
25
26
22
21
23
24
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
14
A
15
A
8
A
9
A
10
A
11
A
12
A
13
NC
NC
OE BHE BLE
CE
WE
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
V
CC
V
SS
V
SS
NC
10
Note
1. NC pins are not connected on the die.
Figure 1. 44-pin SOJ / 44-pin TSOP II pinout (Top View)
[1]

Selection Guide

Maximum Access Time 10 ns
Maximum Operating Current 80 mA
Maximum CMOS Standby Current 3mA
Document Number: 38-05462 Rev. *M Page 3 of 17
Description
-10 (Industrial / Automotive-A)
Unit
Page 4
CY7C1021D

Maximum Ratings

Note
2. V
IL
(min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns.
3. Please note that the maximum V
OH
limit does not exceed minimum CMOS V
IH
of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors that require
a minimum V
IH
of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider.
Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Supply Voltage on V
to Relative GND
CC
DC Voltage Applied to Outputs in High Z State
[2]
................................–0.5 V to +6.0 V
[2]
................................–0.5 V to VCC + 0.5 V
DC Input Voltage
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch Up Current ................................................... > 200 mA

Operating Range

Range
Industrial –40 C to +85 C5 V 10% 10 ns
Automotive-A

Electrical Characteristics

Over the Operating Range
Parameter Description Test Conditions
[2]
............................–0.5 V to VCC + 0.5 V
Ambient
Temperature
V
CC
Speed
-10 (Industrial / Automotive-A)
Min Max
Unit
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
I
SB2
OH
OL
IH
IL
Output HIGH Voltage IOH = –4.0 mA 2.4 – V
= –0.1 mA – 3.4
I
OH
[3]
Output LOW Voltage IOL = 8.0 mA – 0.4 V
Input HIGH Voltage 2.2 V
Input LOW Voltage
Input Leakage Current GND < VI < V
[2]
CC
0.5 0.8 V
1+1A
+ 0.5 V V
CC
Output Leakage Current GND < VI < VCC, Output Disabled 1+1A
VCC Operating Supply Current VCC = Max, I
f = f
= 1/t
max
OUT
RC
= 0 mA,
100 MHz – 80 mA
83 MHz – 72 mA
66 MHz – 58 mA
40 MHz – 37 mA
Automatic CE Power Down Current –TTL Inputs
Automatic CE Power Down Current – CMOS Inputs
Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = f
max
Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or V
< 0.3 V, f = 0
IN
–10mA
–3mA
Document Number: 38-05462 Rev. *M Page 4 of 17
Page 5
CY7C1021D

Capacitance

90%
10%
3.0 V
GND
90%
10%
ALL INPUT PULSES
* CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT
Rise Time: 3 ns
Fall Time: 3 ns
30 pF*
OUTPUT
Z = 50
50 
1.5 V
(b)
(a)
5 V
OUTPUT
5 pF
(c)
R1 480
R2
255
High-Z characteristics:
INCLUDING JIG AND SCOPE
Notes
4. Tested initially and after any design or process changes that may affect these parameters.
5. AC characteristics (except High Z) are tested using the load conditions shown in Figure 2 (a). High Z characteristics are tested for all speeds using the test load shown in Figure 2 (c).
Parameter
C
IN
C
OUT
[4]
Description Test Conditions Max Unit
Input capacitance TA = 25C, f = 1 MHz, VCC = 5.0 V 8 pF
Output capacitance 8pF

Thermal Resistance

Parameter
JA
JC
[4]
Description Test Conditions 44-pin SOJ 44-pin TSOP II Unit
Thermal resistance (junction to ambient)
Thermal resistance (junction to case)

AC Test Loads and Waveforms

Figure 2. AC Test Loads and Waveforms
Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board
[5]
59.52 53.91 C/W
36.75 21.24 C/W
Document Number: 38-05462 Rev. *M Page 5 of 17
Page 6
CY7C1021D

Data Retention Characteristics

4.5 V4.5 V
t
CDR
V
DR
> 2 V
DATA RETENTION MODE
t
R
CE
V
CC
Notes
6. V
IL
(min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns.
7. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 50 s or stable at V
CC(min)
> 50 s.
Over the Operating Range
Parameter Description Conditions Min Max Unit
V
DR
I
CCDR
t
CDR
[7]
t
R
[6]
VCC for Data Retention 2.0 – V
Data Retention Current VCC = VDR = 2.0 V, CE > VCC – 0.3 V,
V
> VCC – 0.3 V or VIN < 0.3 V
IN
–3mA
Chip Deselect to Data Retention Time 0 – ns
Operation Recovery Time t
RC
–ns

Data Retention Waveform

Figure 3. Data Retention Waveform
Document Number: 38-05462 Rev. *M Page 6 of 17
Page 7
CY7C1021D

Switching Characteristics

Notes
8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified I
OL/IOH
and 30-pF load capacitance.
9. t
POWER
gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
10. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
11. t
HZOE
, t
HZBE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in (c) of Figure 2 on page 5. Transition is measured when the outputs enter a high impedance
state.
12. The internal write time of the memory is defined by the overlap of CE
LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE /BL E must be LOW to initiate a write, and a LOW to HIGH transition on any of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write.
Over the Operating Range
Parameter
Read Cycle
[9]
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
[8]
Description
Automotive-A)
Unit
Min Max
VCC(typical) to the first access 100 – s
Read Cycle Time 10 – ns
Address to Data Valid – 10 ns
Data Hold from Address Change 3 – ns
CE LOW to Data Valid – 10 ns
OE LOW to Data Valid – 5 ns
-10 (Industrial /
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
[10]
[10, 11]
[10]
[10, 11]
0–ns
–5ns
3–ns
–5ns
CE LOW to Power-Up 0 – ns
CE HIGH to Power-Down – 10 ns
Byte Enable to Data Valid – 5 ns
Byte Enable to Low Z 0 – ns
Byte Disable to High Z – 5 ns
[12]
Write Cycle Time 10 – ns
CE LOW to Write End 7 – ns
Address Setup to Write End 7 – ns
Address Hold from Write End 0 – ns
Address Setup to Write Start 0 – ns
WE Pulse Width 7–ns
Data Setup to Write End 6 – ns
Data Hold from Write End 0 – ns
WE HIGH to Low Z
WE LOW to High Z
[10]
[10, 11]
3–ns
–5ns
Byte Enable to End of Write 7 – ns
Document Number: 38-05462 Rev. *M Page 7 of 17
Page 8
CY7C1021D

Switching Waveforms

PREVIOUS DATA VALID DATA VALID
RC
t
AA
t
OHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZBE
t
PD
t
DBE
t
LZBE
t
HZCE
HIGH
IMPEDANCE
I
CC
I
SB
OE
CE
ADDRESS
DATA OUT
V
CC
SUPPLY
BHE
,BLE
CURRENT
Notes
13. Device is continuously selected. OE
, CE, BHE and/or BLE = VIL.
14. WE
is HIGH for read cycle.
15. Address valid prior to or coincident with CE
transition LOW.
Figure 4. Read Cycle No. 1 (Address Transition Controlled)
[13, 14]
Figure 5. Read Cycle No. 2 (OE Controlled)
[14, 15]
Document Number: 38-05462 Rev. *M Page 8 of 17
Page 9
CY7C1021D
Switching Waveforms (continued)
t
HD
t
SD
t
SCE
t
SA
t
HA
t
AW
t
PWE
t
WC
BW
t
DATA I/O
ADDRESS
CE
WE
BHE,BLE
Data Valid
t
HD
t
SD
t
BW
t
SA
t
HA
t
AW
t
PWE
t
WC
t
SCE
DATA I/O
ADDRESS
BHE
,BLE
CE
WE
Data Valid
Notes
16. Data I/O is high impedance if OE
or BHE and/or BLE = VIH.
17. If CE
goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Figure 6. Write Cycle No. 1 (CE Controlled)
Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)
[16, 17]
Document Number: 38-05462 Rev. *M Page 9 of 17
Page 10
CY7C1021D
Switching Waveforms (continued)
t
HD
t
SD
t
SCE
t
HA
t
AW
t
PWE
t
WC
t
BW
t
SA
t
LZWE
t
HZWE
DATA I/O
ADDRESS
CE
WE
BHE,BLE
Data Valid
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW)

Truth Table

CE OE WE BLE BHE I/O0–I/O
7
HXXXX High Z High Z Power Down Standby (I
I/O8–I/O
15
Mode Power
)
SB
L L H L L Data Out Data Out Read – All bits Active (ICC)
L H Data Out High Z Read – Lower bits only Active (I
CC
)
H L High Z Data Out Read – Upper bits only Active (ICC)
L X L L L Data In Data In Write – All bits Active (I
L H Data In High Z Write – Lower bits only Active (I
H L High Z Data In Write – Upper bits only Active (I
L H H X X High Z High Z Selected, Outputs Disabled Active (I
L X X H H High Z High Z Selected, Outputs Disabled Active (ICC)
CC
CC
CC
CC
)
)
)
)
Document Number: 38-05462 Rev. *M Page 10 of 17
Page 11
CY7C1021D

Ordering Information

Temperature Range: X = I or A I = Industrial; A = Automotive-A
Pb-free Package Type: XX = V or ZS V = 44-pin Molded SOJ ZS = 44-pin TSOP Type II
Speed: 10 ns
D = C9, 90 nm Technology
1 = Data width × 16-bits
02 = 1-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CCY 1 - 10 XX7 02 XD1 X
Speed
(ns)
10 CY7C1021D-10VXI 51-85082 44-pin (400-Mil) Molded SOJ (Pb-free) Industrial
CY7C1021D-10ZSXI 51-85087 44-pin TSOP Type II (Pb-free)
CY7C1021D-10ZSXA Automotive-A
Shaded areas contain advance information. Contact your local Cypress sales representative for availability of these parts.
Ordering Code

Ordering Code Definitions

Package Diagram
Package Type
Operating
Range
Document Number: 38-05462 Rev. *M Page 11 of 17
Page 12
CY7C1021D

Package Diagrams

51-85082 *E
Figure 9. 44-pin SOJ (400 Mils) V44.4 Package Outline, 51-85082
Document Number: 38-05462 Rev. *M Page 12 of 17
Page 13
CY7C1021D
Package Diagrams (continued)
51-85087 *E
Figure 10. 44-pin TSOP Z44-II Package Outline, 51-85087
Document Number: 38-05462 Rev. *M Page 13 of 17
Page 14
CY7C1021D

Acronyms Document Conventions

Acronym Description
CE
CMOS Complementary Metal Oxide Semiconductor
I/O Input/Output
OE
SOJ Small Outline J-lead
SRAM Static Random Access Memory
TSOP Thin Small Outline Package
TTL Transistor-Transistor Logic
WE
Chip Enable
Output Enable
Write Enable

Units of Measure

Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA microampere
µs microsecond
mA milliampere
mm millimeter
ms millisecond
ns nanosecond
ohm
% percent
pF picofarad
Vvolt
Wwatt
Document Number: 38-05462 Rev. *M Page 14 of 17
Page 15
CY7C1021D

Document History Page

Document Title: CY7C1021D, 1-Mbit (64 K × 16) Static RAM Document Number: 38-05462
Rev. ECN No.
Orig. of
Change
** 201560 SWI See ECN Advance Information data sheet for C9 IPP
*A 233695 RKF See ECN DC parameters modified as per EROS (Spec # 01-02165)
*B 263769 RKF See ECN Added Data Retention Characteristics Table
*C 307601 RKF See ECN Reduced Speed bins to –10 and –12 ns
*D 520647 VKN See ECN Changed status from Preliminary to Final.
*E 802877 VKN See ECN Changed Commercial operating range I
*F 2751755 VKN /
PYRS
*G 2898399 AJU 03/24/2010 Updated Package Diagrams.
*H 3109897 AJU 12/14/2010 Added Ordering Code Definitions.
*I 3245199 PRAS 04/30/2011 Dislodged Automotive information to new datasheet (001-68372).
*J 3086499 AJU 06/07/2011 Updated Functional Description (Removed “For best practice
*K 3540685 TAVA / AJU 03/06/2012 Updated Features (Included Automotive-A Range information).
Submission
Date
Pb-free Offering in the Ordering Information
Added T Shaded Ordering Information
Spec in Switching Characteristics Table
power
Removed Commercial Operating range Added I Updated Thermal Resistance table
values for the frequencies 83MHz, 66MHz and 40MHz
CC
Added Automotive Product Information Updated Ordering Information Table Changed Overshoot spec from V
100MHz, 55 mA to 72 mA for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz Changed Automotive operating range I 83MHz, 90 mA to 100 mA for 66MHz, 60 mA to 63 mA for 40MHz
08/14/09 For 12 ns speed, changed I
For 12 ns speed, changed I 15 mA to 10 mA
Removed the Note “Automotive Product Information is Preliminary.” in page 3. Added Acronyms and Units of Measure. Updated in new template.
recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.”).
Updated Selection Guide (Included Automotive-A Range information). Updated Operating Range (Included Automotive-A Range information). Updated Electrical Characteristics (Included Automotive-A Range information). Updated Switching Characteristics (Included Automotive-A Range information). Updated Ordering Information (included the part number CY7C1021D-10ZSXA). Updated Package Diagrams.
Description of Change
+2V to VCC+1V in footnote #4
CC
spec from 60 mA to 80 mA for
CC
spec from 100 mA to 120 mA for
CC
spec from 120 mA to 90 mA
CC
spec from 50 mA to 10 mA and I
SB1
spec from
SB2
Document Number: 38-05462 Rev. *M Page 15 of 17
Page 16
CY7C1021D
Document History Page (continued)
Document Title: CY7C1021D, 1-Mbit (64 K × 16) Static RAM Document Number: 38-05462
Rev. ECN No.
*L 3998493 MEMJ 05/13/2013 Replaced all instances of IO with I/O across the document.
*M 4033925 MEMJ 06/19/2013 Updated Functional Description.
Orig. of Change
Submission
Date
Description of Change
Updated Switching Characteristics: Updated Note 12.
Updated Switching Waveforms: Updated Figure 6, Figure 7, Figure 8.
Updated Package Diagrams: spec 51-85082 – Changed revision from *D to *E. spec 51-85087 – Changed revision from *D to *E.
Completing Sunset Review.
Updated Electrical Characteristics. Added one more Test Condition “I maximum value corresponding to that Test Condition. Added Note 3 and referred the same note in maximum value for VOH parameter corresponding to Test Condition “I
= –0.1mA” for VOH parameter and added
OH
= –0.1mA”.
OH
Document Number: 38-05462 Rev. *M Page 16 of 17
Page 17
CY7C1021D

Sales, Solutions, and Legal Information

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© Cypress Semiconductor Corporation, 2004-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Sou rce Code and derivative works for the sole purpose of cr eating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05462 Rev. *M Revised June 19, 2013 Page 17 of 17
All products and company names mentioned in this document may be the trademarks of their respective holders.
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