Page 1
CY7C1019DV33
1-Mbit (128 K × 8) Static RAM
1-Mbit (128 K × 8) Static RAM
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUTBUFFER
POWER
DOWN
WE
OE
I/O
0
CE
I/O
1
I/O
2
I/O
3
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
13
A
11
A
12
A
9
A
10
128K × 8
ARRAY
A
14
A
15
A
16
Logic Block Diagram
Features
Functional Description
■ Pin- and function-compatible with CY7C1019CV33
■ High speed
❐ t
= 10 ns
AA
■ Low Active Power
❐ I
= 60 mA @ 10 ns
CC
■ Low CMOS Standby Power
❐ I
= 3 mA
SB2
■ 2.0 V Data retention
■ Automatic power-down when deselected
■ CMOS for optimum speed/power
■ Center power/ground pinout
■ Easy memory expansion with CE
■ Available in Pb-free 32-pin 400-Mil wide Molded SOJ, 32-pin
and OE options
TSOP II and 48-ball VFBGA packages
The CY7C1019DV33 is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE
), and three-state drivers. This device has an
automatic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE
(I/O
through I/O7) is then written into the location specified on
0
the address pins (A
) inputs LOW. Data on the eight I/O pins
through A16).
0
Reading from the device is accomplished by taking Chip Enable
(CE
) and Output Enable (OE) LOW while forcing Write Enable
) HIGH. Under these conditions, the contents of the memory
(WE
location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
the outputs are disabled (OE
LOW, and WE LOW).
(CE
through I/O7) are placed in a
0
HIGH),
HIGH), or during a write operation
The CY7C1019DV33 is available in Pb-free 32-pin 400-Mil wide
Molded SOJ, 32-pin TSOP II and 48-ball VFBGA packages.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-05481 Rev. *F Revised October 20, 2011
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CY7C1019DV33
Contents
Selection Guide ................................................................ 3
Pin Configurations ........................................................... 3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms .......................................5
Switching Characteristics ................................................6
Data Retention Characteristics .......................................7
Data Retention Waveform ................................................7
Switching Waveforms ......................................................7
Truth Table ......................................................................10
Ordering Information ......................................................11
Ordering Code Definitions .........................................11
Package Diagrams ..........................................................12
Acronyms ........................................................................14
Document Conventions .................................................14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products ....................................................................16
PSoC Solutions .........................................................16
Document Number: 38-05481 Rev. *F Page 2 of 16
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Page 3
CY7C1019DV33
Selection Guide
WE
V
CC
A
9
A
16
NC
A
4
A
2
A
1
CE
NC
I/O
0
I/O
1
A
5
A
0
NC
NC
NC
I/O
2
I/O
3
V
SS
A
10
A
3
OE
V
SS
NC
I/O
7
NC
NC
A
13
A
7
A
6
NC
V
CC
I/O
6
NC
NC
NC
I/O
4
I/O
5
A
8
A
11
A
14
A
12
A
15
NC
NC
NC
3
2
6
5
4
1
D
E
B
A
C
F
G
H
NC
Top Vi e w
SOJ/TSOPI
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
12
13
29
32
31
30
16
15
17
18
A
7
A
1
A
2
A
3
CE
I/O
0
I/O
1
V
CC
I/O
2
A
0
A
4
A
5
A
6
I/O
3
WE
V
SS
WE
V
CC
A
9
A
16
NC
A
4
A
2
A
1
CE
A
5
A
0
A
3
V
SS
NC
I/O
7
NC
A
13
A
7
A
6
I/O
6
NC
NC
NC
I/O
4
I/O
5
A
8
A
11
A
14
A
12
A
15
NC
D
E
B
A
C
F
G
H
NC
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
12
13
29
32
31
30
16
15
17
18
A
7
A
1
A
2
A
3
CE
I/O
0
I/O
1
V
CC
A
13
A
16
A
15
OE
I/O
7
I/O
6
A
12
A
11
A
10
A
9
I/O
2
A
0
A
4
A
5
A
6
I/O
4
V
CC
I/O
5
A
8
I/O
3
WE
V
SS
A
14
V
SS
Note
1. NC pins are not connected on the die.
-10 (Industrial) Unit
Maximum Access Time 10 ns
Maximum Operating Current 60 mA
Maximum Standby Current 3mA
Pin Configurations
Figure 1. 48-ball VFBGA (6 × 8 × 1 mm) (Top View)
[1]
Document Number: 38-05481 Rev. *F Page 3 of 16
Figure 2. 32-pin SOJ / TSOP II (Top View)
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Page 4
CY7C1019DV33
Maximum Ratings
Note
2. V
IL(min)
= –2.0 V and V
IH(max)
= VCC + 1 V for pulse durations of less than 5 ns.
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Supply Voltage on
V
to Relative GND
CC
DC Voltage Applied to Outputs
in High Z State
[2]
...............................–0.3 V to +4.6 V
[2]
................................–0.3 V to VCC + 0.3 V
Electrical Characteristics
Over the Operating Range
DC Input Voltage
[2]
............................–0.3 V to VCC + 0.3 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ..........................> 2001 V
Latch-up Current .................................................... > 200 mA
Operating Range
Range Ambient Temperature V
CC
Industrial –40 C to +85 C 3.3 V 0.3 V 10 ns
Speed
Parameter Description Test Conditions
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
I
SB2
OH
OL
IH
IL
Output HIGH voltage Min VCC, IOH = –4.0 mA 2.4 – V
Output LOW voltage Min VCC, IOL = 8.0 mA – 0.4 V
Input HIGH voltage 2.0 V
Input LOW voltage
Input leakage current GND < VIN < V
Output leakage current GND < V
VCC operating supply current VCC = Max, I
Automatic CE power-down
current – TTL inputs
Automatic CE power-down
current – CMOS inputs
[2]
CC
< VCC, output disabled –1 +1 A
IN
= 0 mA,
OUT
MAX
= 1/t
RC
f = f
Max VCC, CE > VIH,
V
> VIH or VIN < VIL, f = f
IN
Max VCC, CE > VCC – 0.3 V,
V
> VCC – 0.3 V or VIN < 0.3 V, f = 0
IN
MAX
-10 (Industrial)
Min Max
+ 0.3 V
CC
Unit
–0.3 0.8 V
–1 +1 A
100 MHz – 60 mA
83 MHz – 55 mA
66 MHz – 45 mA
40 MHz – 30 mA
–10mA
–3mA
Document Number: 38-05481 Rev. *F Page 4 of 16
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Page 5
CY7C1019DV33
Capacitance
90%
10%
3.0 V
GND
90%
10%
ALL INPUT PULSES
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
Rise Time: 1 V/ns
Fall Time: 1 V/ns
30 pF*
OUTPUT
Z = 50
50
1.5V
(b)
(a)
3.3 V
OUTPUT
5 pF
(c)
R1 317
R2
351
High-Z characteristics:
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 3 (a). High Z characteristics are tested for all speeds using the test load shown
in Figure 3 (c).
Parameter
C
IN
C
OUT
[3]
Description Test Conditions Max Unit
Input Capacitance TA = 25 °C, f = 1 MHz, VCC = 3.3 V 8 pF
Output Capacitance 8pF
Thermal Resistance
Parameter
JA
JC
[3]
Description Test Conditions 32-pin SOJ 32-pin TSOP II 48-ball VFBGA Unit
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
Still Air, soldered on a 3 × 4.5
inch, four-layer printed circuit
board
56.29 62.22 36 C/W
38.14 21.43 9 C/W
[4]
Document Number: 38-05481 Rev. *F Page 5 of 16
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Page 6
CY7C1019DV33
Switching Characteristics
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V.
6. t
POWER
gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in Figure 3 on page 5 (c). Transition is measured when the outputs enter a high impedance state.
9. This parameter is guaranteed by design and is not tested.
10. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals
can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle no. 3 (WE
controlled, OE LOW) is the sum of t
HZWE
and tSD.
Over the Operating Range
Parameter
Read Cycle
[6]
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
[9]
t
PU
[9]
t
PD
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
[5]
Description
-10 (Industrial)
Min Max
Unit
VCC(typical) to the first access 100 – s
Read cycle time 10 – ns
Address to data valid – 10 ns
Data hold from address change 3 – ns
CE LOW to data valid – 10 ns
OE LOW to data valid – 5 ns
OE LOW to low Z
OE HIGH to high Z
CE LOW to low Z
CE HIGH to high Z
[7]
[7]
[7, 8]
[7, 8]
0–ns
–5ns
3–ns
–5ns
CE LOW to power-up 0 – ns
CE HIGH to power-down – 10 ns
[10, 11]
Write cycle time 10 – ns
CE LOW to write end 8 – ns
Address set-up to write end 8 – ns
Address hold from write end 0 – ns
Address set-up to write start 0 – ns
WE pulse width 7–ns
Data set-up to write end 5 – ns
Data hold from write end 0 – ns
WE HIGH to low Z
WE LOW to high Z
[7]
[7, 8]
3–ns
–5ns
Document Number: 38-05481 Rev. *F Page 6 of 16
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Page 7
CY7C1019DV33
Data Retention Characteristics
3.0 V3.0 V
t
CDR
V
DR
> 2 V
DATA RETENTION MODE
t
R
CE
V
CC
PREVIOUS DATA VALID DATA OUT VALID
RC
t
AA
t
OHA
tRC
ADDRESS
DATA I/O
Notes
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 50 s or stable at V
CC(min.)
> 50 s.
14. Device is continuously selected. OE
, CE = VIL.
15. WE
is HIGH for Read cycle.
Over the Operating Range
Parameter Description Conditions Min Max Unit
V
DR
I
CCDR
t
CDR
[13]
t
R
[12]
VCC for data retention 2.0 – V
Data retention current VCC = VDR = 2.0 V, CE > VCC – 0.3 V,
V
> VCC – 0.3 V or VIN < 0.3 V
IN
Chip deselect to data retention
–3mA
0–ns
time
Operation recovery time t
RC
–ns
Data Retention Waveform
Figure 4. Data Retention Waveform
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled)
[14, 15]
Document Number: 38-05481 Rev. *F Page 7 of 16
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CY7C1019DV33
Switching Waveforms (continued)
50%
50%
DATA OUT VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
ICC
ISB
IMPEDANCE
OE
CE
ADDRESS
DATA I/O
V
CC
SUPPLY
CURRENT
t
WC
DATA IN VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
t
SCE
CE
WE
DATA I/O
ADDRESS
Notes
16. WE
is HIGH for Read cycle.
17. Address valid prior to or coincident with CE
transition LOW.
18. Data I/O is high impedance if OE
= VIH.
19. If CE
goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Figure 6. Read Cycle No. 2 (OE
Controlled)
[16, 17]
Figure 7. Write Cycle No. 1 (CE Controlled)
Document Number: 38-05481 Rev. *F Page 8 of 16
[18, 19]
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CY7C1019DV33
Switching Waveforms (continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA IN VALID
NOTE 22
CE
ADDRESS
WE
DATA I/O
OE
DATA IN VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
NOTE 22
CE
ADDRESS
WE
DATA I/O
Notes
20. Data I/O is high impedance if OE
= VIH.
21. If CE
goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
22. During this period the I/Os are in the output state and input signals should not be applied.
23. The minimum write cycle time for Write Cycle no. 3 (WE
controlled, OE LOW) is the sum of t
HZWE
and tSD.
Figure 8. Write Cycle No. 2 (WE
Controlled, OE HIGH During Write)
[20, 21]
Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW)
Document Number: 38-05481 Rev. *F Page 9 of 16
[21, 23]
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CY7C1019DV33
Truth Table
CE OE WE I/O0–I/O
H X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (I
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)
7
Mode Power
CC
)
Document Number: 38-05481 Rev. *F Page 10 of 16
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Page 11
CY7C1019DV33
Ordering Information
Temperature Range:
I = Industrial
Pb-free
Package Type: XX = V or ZS or BV
V = 32-pin Molded SOJ
ZS = 32-pin TSOP Type II
BV = 48-ball VFBGA
Speed: 10 ns
Voltage range: V33 = 3 V to 3.6 V
Process Technology: D = C9, 90 nm
Data width: 9 = × 8-bits
01 = 1-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CCY 1 - 10 XX7 01 V33 ID9 X
Speed
(ns)
10 CY7C1019DV33-10VXI 51-85033 32-pin (400-Mil) Molded SOJ (Pb-free) Industrial
CY7C1019DV33-10ZSXI 51-85095 32-pin TSOP Type II (Pb-free)
CY7C1019DV33-10BVXI 51-85150 48-ball VFBGA (Pb-free)
Ordering Code
Ordering Code Definitions
Package
Diagram
Package Type
Operating
Range
Please contact your local Cypress sales representative for availability of these parts.
Document Number: 38-05481 Rev. *F Page 11 of 16
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CY7C1019DV33
Package Diagrams
51-85033 *D
51-85095 *B
Figure 10. 32-pin SOJ (400 Mils) V32.4 (Molded SOJ V33) Package Outline, 51-85033
Figure 11. 32-pin TSOP II (20.95 × 11.76 × 1.0 mm) ZS32 Package Outline, 51-85095
Document Number: 38-05481 Rev. *F Page 12 of 16
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CY7C1019DV33
Package Diagrams (continued)
51-85150 *G
Figure 12. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
Document Number: 38-05481 Rev. *F Page 13 of 16
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CY7C1019DV33
Acronyms Document Conventions
Acronym Description
CE
CMOS complementary metal oxide semiconductor
I/O input/output
OE
SOJ small outline J-lead
SRAM static random access memory
TSOP thin small outline package
TTL transistor-transistor logic
VFBGA very fine-pitch ball gird array
WE
chip enable
output enable
write enable
Units of Measure
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
A microampere
s microsecond
mA milliampere
mm millimeter
ns nanosecond
ohm
% percent
pF picofarad
V volt
W watt
Document Number: 38-05481 Rev. *F Page 14 of 16
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CY7C1019DV33
Document History Page
Document Title: CY7C1019DV33, 1-Mbit (128 K × 8) Static RAM
Document Number: 38-05481
Rev. ECN No. Issue Date
** 201560 See ECN SWI Advance Information data sheet for C9 IPP
*A 233750 See ECN RKF DC parameters modified as per EROS (Spec # 01-02165 Rev *A)
*B 262950 See ECN RKF Added Data Retention Characteristics table
*C 307598 See ECN RKF Reduced Speed bins to -8 and -10 ns
*D 520652 See ECN VKN Converted from Preliminary to Final
*E 3110052 12/14/2010 AJU Added Ordering Code Definitions.
*F 3416342 10/20/2011 TAVA Updated Functional Description (Removed the Note “For guidelines on SRAM
Orig. of
Change
Description of Change
Pb-free Offering in Ordering Information
Added T
Shaded Ordering Information
Removed Commercial Operating range
Removed 8 ns speed bin
Added I
Added 48-ball VFBGA package
Updated Thermal Resistance table
Updated Ordering Information table
Changed Overshoot spec from VCC + 2 V to VCC + 1 V in footnote #3
Updated Package Diagrams.
system design, please refer to the ‘System Design Guidelines’ Cypress
application note, available on the internet at www.cypress.com.” and its
reference in Functional Description).
Updated Electrical Characteristics.
Updated Switching Waveforms.
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Updated in new template.
Spec in Switching Characteristics table
power
values for the frequencies 83 MHz, 66 MHz and 40 MHz
CC
Document Number: 38-05481 Rev. *F Page 15 of 16
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CY7C1019DV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
Automotive cypress.com/go/automotive
Clocks & Buffers cypress.com/go/clocks
Interface cypress.com/go/interface
Lighting & Power Control cypress.com/go/powerpsoc
cypress.com/go/plc
Memory cypress.com/go/memory
Optical & Image Sensing cypress.com/go/image
PSoC cypress.com/go/psoc
Touch Sensing cypress.com/go/touch
USB Controllers cypress.com/go/USB
Wireless/RF cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Sou rce Code and derivative works for the sole purpose of cr eating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05481 Rev. *F Revised October 20, 2011 Page 16 of 16
All products and company names mentioned in this document may be the trademarks of their respective holders.
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