CY7C1019D
1-Mbit (128K x 8) Static RAM
Features
• Pin- and function-compatible with CY7C1019B
• High speed
= 10 ns
—t
AA
• Low active power
= 80 mA @ 10 ns
—I
CC
• Low CMOS standby power
—I
= 3 mA
SB2
• 2.0V Data retention
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Center power/ground pinout
• Easy memory expansion with CE
and OE options
• Functionally equivalent to CY7C1019B
• Available in Pb-free 32-pin 400-Mil wide Molded SOJ and
32-pin TSOP II packages
Logic Block Diagram
Functional Description
[1]
The CY7C1019D is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE
active LOW Output Enable (OE
), and tri-state drivers. This
), an
device has an automatic power-down feature that significantly
reduces power consumption when deselected. The eight input
and output pins (IO
through IO7) are placed in a
0
high-impedance state when:
• Deselected (CE HIGH)
• Outputs are disabled (OE
• When the write operation is active (CE
Write to the device by taking Chip Enable (CE
Enable (WE
) inputs LOW. Data on the eight IO pins (IO
HIGH)
LOW, an d WE LOW).
) and Write
through IO7) is then written into the location specified on the
address pins (A
through A16).
0
Read from the device by taking Chi p En ab l e (CE) and Output
Enable (OE
) LOW while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins appears on the IO pins.
0
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
7
8
ROW DECODER
A
A
CE
WE
OE
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
128K x 8
ARRAY
COLUMN DECODER
9
12
10
A
A
14
11
A
A13A
A
A15A
SENSE AMPS
POWER
DOWN
16
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05464 Rev. *E Revised February 22, 2007
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Pin Configuration
CY7C1019D
SOJ/TSOPII
Top View
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
A
A
A
OE
IO
IO
V
V
IO
IO
A
A
A
A
A
16
15
14
13
7
6
SS
CC
5
4
12
11
10
9
8
IO
IO
V
V
IO
IO
WE
A
A
A
A
CE
CC
SS
A
A
A
A
1
0
1
2
3
2
4
3
5
6
0
7
1
8
9
10
2
3
11
12
4
13
5
14
6
15
16
7
Selection Guide
–10 (Industrial) Unit
Maximum Access Time 10 ns
Maximum Operating Current 80 mA
Maximum Standby Current 3 mA
Document #: 38-05464 Rev. *E Page 2 of 11
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CY7C1019D
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DC Voltage Applied to Outputs
in High-Z State
DC Input Voltage
to Relative GND
CC
[2]
...................................–0.5V to VCC + 0.5V
[2]
................................–0.5V to VCC + 0.5V
[2]
... –0.5V to +6.0V
Current into Outputs (LOW) ................................... ..... 20 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ............................. ... ... .................> 200 mA
Operating Range
Range
Industrial –40°C to +85°C 5V ± 0.5V 10 ns
Electrical Characteristics (Over the Operating Range)
Parameter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Output HIGH Voltage IOH = –4.0 mA 2.4 V
Output LOW Voltage IOL = 8.0 mA 0.4 V
Input HIGH Voltage 2.2 V
Input LOW Voltage
Input Leakage Current GND < VI < V
[2]
CC
Output Leakage Current GND < VI < VCC, Output Disabled –1 +1 µA
VCC Operating Supply Current VCC = Max,
I
OUT
f = f
max
= 0 mA,
= 1/t
RC
Ambient
Temperature
V
CC
–10 (Industrial)
Min Max
CC
–0.5 0.8 V
–1 +1 µA
100 MHz 80 mA
83 MHz 72 mA
66 MHz 58 mA
Speed
Unit
+ 0.5 V
I
SB1
I
SB2
Note
2. V
(min) = –2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns.
IL
Automatic CE Power-Down
Current—TTL Inputs
Automatic CE Power-Down
Current—CMOS Inputs
Max VCC, CE > V
VIN > VIH or VIN < VIL, f = f
IH
max
Max VCC, CE > VCC – 0.3V,
V
> VCC – 0.3V, or VIN < 0.3V, f = 0
IN
40 MHz 37 mA
10 mA
3mA
Document #: 38-05464 Rev. *E Page 3 of 11
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CY7C1019D
Capacitance
[3]
Parameter Description Test Conditions Max Unit
C
IN
C
OUT
Thermal Resistance
Parameter Description T e st Con dit ions
Θ
JA
Θ
JC
AC Test Loads and Waveforms
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
Input Capacitance TA = 25°C, f = 1 MHz, VCC = 5.0V 6 pF
Output Capacita nce 8 pF
[3]
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
400-Mil
Wide SOJ
56.29 62.22 °C/W
38.14 21.43 °C/W
TSOP II Unit
(Junction to Case)
[4]
ALL INPUT PULSES
90%
10%
(b)
90%
10%
Fall Time: ≤ 3 ns
OUTPUT
Z = 50
Ω
50Ω
1.5V
30 pF*
3.0V
GND
Rise Time: ≤ 3 ns
(a)
High-Z characteristics:
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
5 pF
R1 480Ω
R2
255Ω
(c)
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are test ed for all speeds using the test load
shown in Figure (c).
Document #: 38-05464 Rev. *E Page 4 of 11
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CY7C1019D
Switching Characteristics (Over the Operating Range)
Parameter Description
Read Cycle
[6]
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
[9]
t
PU
[9]
t
PD
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
VCC(typical) to the first access 100 µs
Read Cycle Time 10 ns
Address to Data Valid 10 ns
Data Hold from Address Change 3 ns
CE LOW to Data Valid 10 ns
OE LOW to Data V alid 5 ns
OE LOW to Low Z 0 ns
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
[7, 8]
[8]
[7, 8]
CE LOW to Power-Up 0 ns
CE HIGH to Power-Down 10 ns
[10, 11]
Write Cycle Time 10 ns
CE LOW to Write End 7 ns
Address Set-Up to Write End 7 ns
Address Hold from Write End 0 ns
Address Set-Up to Write Start 0 ns
WE Pulse Width 7 ns
Data Set-Up to Write End 6 ns
Data Hold from Write End 0 ns
WE HIGH to Low Z
WE LOW to High Z
[8]
[7, 8]
[5]
–10 (Industrial)
Min Max
Unit
5ns
3ns
5ns
3ns
5ns
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
6. t
7. t
8. At any given temperature and voltage condition, t
9. This parameter is guaranteed by design and is not tested.
10.The internal write time of the memory is defined by the overlap of CE
11.The minimum write cycle time for Write Cycle no. 3 (WE
and 30-pF load capacitance.
I
OL/IOH
gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
POWER
, t
HZCE
, and t
HZOE
high impedance state.
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
are specified with a load capacitance of 5 pF as in (c) of “AC Test Loads and Waveforms
HZWE
is less than t
HZCE
controlled, OE LOW) is the sum of t
, t
LZCE
is less than t
HZOE
LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of
LZOE
, and t
HZWE
[4]
” on page 4. Transition is measured when the outputs enter a
is less than t
HZWE
and tSD.
for any given device.
LZWE
Document #: 38-05464 Rev. *E Page 5 of 11
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CY7C1019D
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min Max Unit
V
DR
I
CCDR
[3]
t
CDR
[12]
t
R
Data Retention Waveform
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
VCC for Data Retention 2.0 V
Data Retention Current VCC = VDR = 2.0V, CE > VCC – 0.3V,
V
> VCC – 0.3V or VIN < 0.3V
IN
Chip Deselect to Data Retention Time 0 ns
Operation Recovery Time t
DATA RETENTION MODE
V
V
CC
t
CDR
CE
[13, 14]
DR
> 2V
4.5V4.5V
RC
t
R
3mA
ns
ADDRESS
DATA OUT
PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled)
ADDRESS
CE
OE
DATA OUT
V
CC
SUPPLY
CURRENT
HIGH IMPEDANCE
t
LZCE
t
PU
[14, 15]
t
ACE
t
LZOE
t
OHA
t
DOE
50%
tRC
RC
t
AA
t
RC
t
HZOE
t
DATA VALID
HZCE
t
PD
HIGH
IMPEDANCE
ICC
50%
ISB
Notes
12.Full device operation requires linear V
13.Device is continuously selected. OE
14.WE
is HIGH for Read cycle.
15.Address valid prior to or coincident with CE
ramp from V
CC
, CE = VIL.
DR
transition LOW.
to V
> 50 µs or st able at V
CC(min)
CC(min)
> 50 µs.
Document #: 38-05464 Rev. *E Page 6 of 11
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Switching Waveforms (continued)
Write Cycle No. 1 (CE
ADDRESS
CE
WE
DATA IO
Controlled)
[16, 17]
CY7C1019D
t
WC
t
SCE
t
SA
t
t
AW
t
PWE
SCE
t
SD
DATA VALID
t
HA
t
HD
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
ADDRESS
t
SCE
CE
t
AW
t
SA
WE
OE
DATA IO
NOTE 18
t
HZOE
[16, 17]
t
WC
t
PWE
t
SD
DATAINVALID
t
HA
t
HD
Notes
16.Data IO is high impedance if OE
17.If CE
goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
18.During this period the IOs are in the output state and input signals should not be applied.
= VIH.
Document #: 38-05464 Rev. *E Page 7 of 11
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Switching Waveforms (continued)
Write Cycle No. 3 (WE
ADDRESS
CE
Controlled, OE LOW)
[11, 17]
t
SCE
t
CY7C1019D
WC
t
HA
t
LZWE
t
HD
WE
DATA IO
NOTE 18
t
AW
t
SA
t
HZWE
t
PWE
t
SD
DATA VALID
Truth Table
CE OE WE IO0–IO
7
H X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (I
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)
Mode Power
)
CC
Ordering Information
Speed
(ns)
Ordering Code
10 CY7C1019D-10VXI 51-85033 32-pin (400-Mil) Molded SOJ (Pb-free) Industrial
CY7C1019D-10ZSXI 51-85095 32-pin TSOP Type II (Pb-free)
Please contact your local Cypress sales representative for availability of these parts.
Package
Diagram
Package Type
Operating
Range
Document #: 38-05464 Rev. *E Page 8 of 11
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Package Diagrams
CY7C1019D
Figure 1. 32-pin (400-Mil) Molded SOJ (51-85033)
51-85033-*B
Document #: 38-05464 Rev. *E Page 9 of 11
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Package Diagrams (continued)
Figure 2. 32-pin Thin Small Outline Package Type II (51-85095)
CY7C1019D
All product or company names mentioned in this document may be the trademarks of their respective holders.
51-85095-**
Document #: 38-05464 Rev. *E Page 10 of 11
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodi ed in a Cypress p roduct. Nor do es it conve y or i mply any license u nder p atent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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Document History Page
Document Title: CY7C1019D, 1-Mbit (128K x 8) Static RAM
Document Number: 38-05464
REV. ECN NO. Issue Date
** 201560 See ECN SWI Advance Information data sheet for C9 IPP
*A 233715 See ECN RKF DC parameters are modified as per EROS (Spec # 01-2165)
*B 262950 See ECN RKF Added T
*C 307598 See ECN RKF Reduced Speed bins to -10 and -12 ns
*D 520647 See ECN VKN Converted from Preliminary to Final
*E 802877 See ECN VKN Changed I
Orig. of
Change
Description of Change
Pb-free offering in the Ordering Information
Spec in Switch in g Characteristics t able
Added Data Retention Characteristics table and waveforms
power
Shaded Ordering Information
Removed Commercial Operating range
Removed 12 ns speed bin
Added I
Updated Thermal Resistance table
values for the frequencies 83MHz, 66MHz and 40MHz
CC
Updated Ordering Information Table
Changed Overshoot spec from V
spec from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA
for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz
CC
+2V to VCC+1V in footnote #2
CC
CY7C1019D
Document #: 38-05464 Rev. *E Page 11 of 11
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