Cypress CY7C1018DV33 User Manual

CY7C1018DV33

1-Mbit (128K x 8) Static RAM

Features

• Pin- and function-compatible with CY7C1018CV33

• High speed
—tAA = 10 ns

• Low Active Power
—ICC = 60 mA @ 10 ns

• Low CMOS Standby Power
—I

= 3 mA

SB2

• 2.0V Data retention

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Center power/ground pinout

• Easy memory expansion with CE

and OE options

• Available in Pb-free 32-pin 300-Mil wide Molded SOJ

Logic Block Diagram

Functional Description

[1]

The CY7C1018DV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE

), and tri-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.

Writing to the device is accomplished by taking Chip Enable
(CE

) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
specified on the address pins (A

through I/O7) is then written into the location

0

through A16).

0

Reading from the device is accomplished by taking Chip
Enable (CE
Enable (WE

) and Output Enable (OE) LOW while forcing Write

) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.

The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE

LOW, and WE LOW).

The CY7C1018DV33 is available in Pb-free 32-pin 300-Mil
wide Molded SOJ.

Pin Configuration

SOJ

Top View

A

1

0

A

1

2

A

3

2

A

4

I/O
I/O

V
V

I/O
I/O

WE

CE

CC

SS

A
A
A
A

3

5
6

0

7

1

8
9
10

2
3

11
12

4

13

5

14

6

15
16

7

I/O

I/O
I/O

I/O
I/O
I/O

I/O

I/O

0

1

2

3

4

5

6

7

INPUTBUFFER

A

0

A

1

A

2

A

CE
WE

3

A

4

A

5

A

6

A
A

ROW DECODER

7
8

128K × 8

ARRAY

COLUMN

DECODER

SENSE AMPS

POWER

DOWN

OE

9

10

13

12

11

A

A

A

A

Note

1. For guidelines on SRAM system designs, please refer to the ‘System Design Guidelines’ Cypress application note, a vailable on the internet at www .cypress.com.

16

14

15

A

A

A

A

32
31

30
29

28
27
26
25
24
23
22
21
20
19
18

17

A
A
A

A
OE

I/O
I/O

V
V
I/O
I/O

A
A

A
A

A

16
15
14

13

7
6

SS
CC

5
4

12
11

10
9

8

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05465 Rev. *D Revised November 8, 2006

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CY7C1018DV33

Selection Guide

–10 (Industrial) Unit

Maximum Access Time 10 ns
Maximum Operating Current 60 mA
Maximum Standby Current 3 mA

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V
DC Voltage Applied to Outputs

to Relative GND

CC

[2]

in High-Z State .......................................–0.3V to VCC + 0.3V

[2]

...–0.3V to + 4.6V

DC Input Voltage

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage...........................................> 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current.....................................................> 200 mA

Operating Range

Range

Industrial –40°C to +85°C 3.3V ± 0.3V 10 ns

DC Electrical Characteristics Over the Operating Range

Parameter Description T e st Con dit ion s

V

V

V
V
I

IX

I

OZ

I

CC

I

SB1

I

SB2

OH

OL

IH
IL

Output HIGH Voltage VCC = Min.,

I

= –4.0 mA

OH

Output LOW Voltage VCC = Min.,

I

= 8.0 mA

OL

Input HIGH Voltage 2.0 V
Input LOW Voltage
Input Leakage Current GND < VI < V

[2]

CC

Output Leakage Current GND < VI < VCC, Output Disabled –1 +1 µA
VCC Operating Supply Current VCC = Max.,

I

= 0 mA,

OUT

f = f

MAX

Automatic CE Power-down
Current—TTL Inputs

Automatic CE Power-down
Current—CMOS Inputs

Max. VCC, CE > V
VIN > VIH or VIN < VIL, f = f

Max. VCC, CE > VCC – 0.3V,

> VCC – 0.3V, or VIN < 0.3V, f = 0

V

IN

= 1/t

RC

IH

[2]

................................–0.3V to VCC + 0.3V

Ambient

Temperature

V

CC

–10 (Industrial)

Min. Max.

2.4 V

0.4 V

+ 0.3 V

CC

–0.3 0.8 V

–1 +1 µA

100MHz 60 mA

83MHz 55 mA
66MHz 45 mA
40MHz 30 mA

10 mA

MAX

3mA

Speed

Unit

Note

(min.) = –2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns.

2. V

IL

Document #: 38-05465 Rev. *D Page 2 of 9

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CY7C1018DV33

Capacitance

[3]

Parameter Description T e st Con dit ion s Max. Unit

C

IN

C

OUT

Thermal Resistance

Parameter Description Test Conditions

Θ

JA

Θ

JC

AC Test Loads and Waveforms

* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT

Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V 8 pF
Output Capacitance 8 pF

[3]

400-Mil

Wide SOJ

Thermal Resistance
(Junction to Ambient)

Thermal Resistance

Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board

57.61 °C/W

40.53 °C/W

(Junction to Case)

[4]

ALL INPUT PULSES

90%

10%

(b)

OUTPUT

Z = 50

Ω

50Ω

1.5V

30 pF*

3.0V

GND

Rise Time: 1 V/ns

(a)

90%

Fall Time: 1 V/ns

Unit

10%

High-Z characteristics:

3.3V

OUTPUT

5 pF

R 317 Ω

R2

351Ω

(c)

Notes

3. T ested initially and after any design or process changes that may affect these parameters.

4. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).

Document #: 38-05465 Rev. *D Page 3 of 9

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