Cypress CY7C1018CV33 User Manual

CY7C1018CV33

128K x 8 Static RAM

Features

• Pin- and function-compatible with CY7C1018BV33

•High speed
—tAA = 10 ns

• CMOS for optimum speed/power

• Center power/ground pinout

• Data retention at 2. 0V

• Automatic power-down when deselected

• Easy memory expansion with CE

and OE options

• Available in Pb-free and non Pb-free 300-mil-wide

32-pin SOJ

Functional Description

[1]

The CY7C1018CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE
active LOW Output Enable (OE

), and tri-state drivers. This

), an

Logic Block Diagram

device has an automatic power-down feature that significantly
reduces power consumption when deselected.

Writing to the device is accomplished by taking Chip Enable
(CE

) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
specified on the address pins (A

through I/O7) is then written into the location

0

through A16).

0

Reading from the device is accomplished by taking Chip
Enable (CE
Enable (WE

) and Output Enable (OE) LOW while forcing Write

) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.

The eight input/output pins (I/O
high-impedance state when the device is deselected (CE

through I/O7) are placed in a

0

HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE

LOW, and WE LOW).

The CY7C1018CV33 is available in a standard 300-mil-wide
SOJ.

Pin

Configurations

SOJ

Top View

A

1

0

A

1

2

A

3

2

A

4

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

0

1

2

3

4

5

6

7

INPUT BUFFER

A

0

A

1

A

2

A

3

A

4

A

5

A

6

A
A

CE

WE

OE

Note:

1. For guidelines on SRAM system designs, please refer to the ‘System Design Guidelines’ Cypress application note, avai lable on the internet at www.cypress.com.

ROW DECODER

7
8

128K x 8

DECODER

9

10

A

A

ARRAY

COLUMN

12

A11A13A

SENSE AMPS

POWER

DOWN

14

15

16

A

A

A

CE

I/O
I/O

V
V

I/O
I/O

WE

CC

SS

A
A
A
A

3

5
6

0

7

1

8
9
10

2
3

11
12

4

13

5

14

6

15
16

7

32
31

30
29

28
27
26
25
24
23

22
21

20
19

18
17

A
A
A

A
OE

I/O
I/O

V
V
I/O
I/O

A
A

A
A

A

16
15
14

13

7
6

SS
CC

5
4

12
11

10
9

8

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05131 Rev. *D Revised August 3, 2006

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CY7C1018CV33

Selection Guide

-10 -12 -15 Unit

Maximum Access Time 10 12 15 ns
Maximum Operating Current Comm’l 90 85 80 mA

Ind’l 85 mA

Maximum Standby Current 5 5 5 mA

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V

Relative to GND

CC

DC Voltage Applied to Outputs

[6]

[2]

...–0.5V to + 4.6V

in High-Z State .......................................–0.5V to VCC + 0.5V

DC Input Voltage

[2]

.................................–0.5V to VCC + 0.5V

Electrical Characteristics Over the Operating Range

Parameter Description T est Conditions

V

OH

V

OL

V

IH

V

IL

I

IX

I

OZ

I

CC

I

SB1

I

SB2

Capacitance

Output HIGH V oltageVCC = Min.,

= – 4.0 mA

I

OH

Output LOW Voltage VCC = Min.,

I

= 8.0 mA

OL

Input HIGH Voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 V
Input LOW Voltage
Input Leakage

Current
Output Leakage

Current
VCC Operating

Supply Current

Automatic CE
Power-down Current
—TTL Inputs

Automatic CE
Power-down Current
—CMOS Inputs

[3]

[2]

GND < VI < V

GND < VI < VCC,
Output Disabled

VCC = Max.,
I

= 0 mA,

OUT

f = f

MAX

= 1/t

Max. VCC, CE > V
VIN > VIH or
V

< VIL, f = f

IN

Max. VCC,
CE

> VCC – 0.3V,

> VCC – 0.3V,

V

IN

or V

< 0.3V, f = 0

IN

CC

Comm’l 90 85 80 mA
Ind’l 85 mA

RC

Comm’l 15 15 15 mA

IH

Ind’l 15 mA

MAX

Comm’l 5 5 5 mA
Ind’l 5 mA

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage...........................................> 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current.....................................................> 200 mA

Operating Range

Range Ambient Temperature V

Commercial 0°C to +70°C 3.3V ± 10%
Industrial –40°C to +85°C 3.3V ± 10%

–10 –12 –15

2.4 2.4 2.4 V

0.4 0.4 0.4 V

–0.3 0.8 –0.3 0.8 –0.3 0.8 V

–1 +1 –1 +1 –1 +1 µA

–1 +1 –1 +1 –1 +1 µA

CC

UnitMin. Max. Min. Max. Min. Max.

Parameter Description Test Conditions Max. Unit

C

IN

C

OUT

Notes:

2. V

(min.) = –2.0V for pulse durations of less than 20 ns.

IL

3. Tested initially and after any design or process changes that may affect these parameters.

Input Capacitance TA = 25°C, f = 1 MHz,

V

= 3.3V

Output Capacitance 8 pF

CC

8pF

Document #: 38-05131 Rev. *D Page 2 of 7

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CY7C1018CV33

351Ω

R2

351Ω

R2

[4]

3.0V

GND

Rise Time: 1 V/ns

ALL INPUT PULSES

90%

10%

(b)

90%

10%

Fall Time: 1 V/ns

AC Test Loads and Waveforms

3.3V

OUTPUT

30 pF

High-Z characteristics:

3.3V

OUTPUT

5 pF

R 317Ω

(a)

R 317Ω

(c)

Switching Characteristics

Over the Operating Range

Parameter Description

[5]

-10 -12

-15
UnitMin. Max. Min. Max. Min. Max.

Read Cycle

t

RC

t

AA

t

OHA

t

ACE

t

DOE

t

LZOE

t

HZOE

t

LZCE

t

HZCE

[8]

t

PU

[8]

t

PD

Write Cycle

t

WC

t

SCE

t

AW

t

HA

t

SA

t

PWE

t

SD

t

HD

t

LZWE

t

HZWE

Notes:

4. AC characteristics (except High-Z) for all speeds are tested using the Thè venin load shown in Figure (a). High-Z cha racteristics are tested for all speeds usin g
the test load shown in Figure (c).

5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.

6. t

7. At any given temperature and voltage condition, t

8. This parameter is guaranteed by design and is not tested.

9. The internal Write time of the memor y is defined by the overlap of CE

10. The minimum Write cycle time for Write Cycle No. 3 (WE

, t

HZOE

signals can terminate the Write . The input dat a set-up and h old timing should be referenced to th e leading edge of the signal tha t terminates th e Write.

Read Cycle Time 10 12 15 ns
Address to Data Valid 10 12 15 ns
Data Hold from Address Change 3 3 3 ns
CE LOW to Data Valid 10 12 15 ns
OE LOW to Data Valid 5 6 7 ns
OE LOW to Low-Z 0 0 0 ns

[7]

[6, 7]

[6, 7]

567 ns

333 ns

567 ns

OE HIGH to High-Z
CE LOW to Low-Z
CE HIGH to High-Z
CE LOW to Power-up 0 0 0 ns
CE HIGH to Power-down 10 12 15 ns

[9, 10]

Write Cycle Time 10 12 15 ns
CE LOW to Write End 8 9 10 ns
Address Set-up to Write End 8 9 10 ns
Address Hold from Write End 0 0 0 ns
Address Set-up to Write Start 0 0 0 ns
WE Pulse Width 7 8 10 ns
Data Set-up to Write End 5 6 8 ns
Data Hold from Write End 0 0 0 ns
WE HIGH to Low-Z
WE LOW to High-Z

, and t

HZCE

HZWE

are specified with a load capacitance of 5 pF as in (d) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.

[7]
[6, 7]

333 ns

is less than t

HZCE

controlled, OE LOW) is the sum of t

, t

LZCE

HZOE

LOW and WE LOW. C E and WE must be LOW to initiate a W rite, and the transiti on of any of these

567 ns

is less than t

LZOE

, and t

HZWE

is less than t

HZWE

and tSD.

for any given device.

LZWE

Document #: 38-05131 Rev. *D Page 3 of 7

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