Cypress CY7C1012DV33 User Manual
CY7C1012DV33
12-Mbit (512K X 24) Static RAM
Features
Logic Block Diagram
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
512K x 24
ARRAY
I/O0 – I/O
7
OE
I/O8 – I/O
15
CE1, CE2, CE
3
WE
I/O
16
– I/O
23
CONTROL LOGIC
A
(9:0)
A
(18:10)
■
High speed
❐
tAA = 10 ns
■
Low active power
❐
ICC = 175 mA at 10 ns
■
Low CMOS standby power
❐
I
= 25 mA
SB2
■
Operating voltages of 3.3 ± 0.3V
■
2.0V data retention
■
Automatic power down when deselected
■
TTL compatible inputs and outputs
■
Available in Pb-free standard 119-ball PBGA
Functional Description
The CY7C1012DV33 is a high performance CMOS static RAM
organized as 512K words by 24 bits. Each data byte is separately
controlled by the individual chip selects (CE1, CE2, and CE3).
CE
controls the data on the I/O0 – I/O7, while CE2 controls the
1
data on I/O
I/O
16
that significantly reduces power consumption when deselected.
Writing the data bytes into the SRAM is accomplished when the
chip select controlling that byte is LOW and the write enable input
(WE
) input is LOW. Data on the respective input and output (I/O)
pins is then written into the location specified on the address pins
(A0 – A18). Asserting all of the chip selects LOW and write enable
LOW writes all 24 bits of data into the SRAM. Output enable (OE
is ignored while in WRITE mode.
Data bytes are also individually read from the device. Reading a
byte is accomplished when the chip select cont rolling that byte
is LOW and write enable (WE
remains LOW. Under these conditions, the contents of the
memory location specified on the address pins appear on the
specified data input and output (I/O) pins. Asserting all the chip
selects LOW reads all 24 bits of data from the SRAM.
The 24 I/O pins (I/O
state when all the chip selects are HIGH or when the output
enable (OE) is HIGH during a READ mode. For more information, see the Truth Table on page 8.
– I/O15, and CE3 controls the data on the data pins
8
– I/O23. This device has an automatic power down feature
) HIGH, while output enable (OE)
– I/O23) are placed in a high impedance
0
)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-05610 Rev. *D Revised November 6, 2008
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CY7C1012DV33
Selection Guide
1 2 3 4 5 6 7
A NCAAAAANC
B NC A A CE
1
AANC
C I/O
12
NC CE
2
NC CE
3
NC I/O
0
D I/O
13
V
DD
V
SS
V
SS
V
SS
V
DD
I/O
1
E I/O
14
V
SS
V
DD
V
SS
V
DD
V
SS
I/O
2
F I/O
15
V
DD
V
SS
V
SS
V
SS
V
DD
I/O
3
G I/O
16
V
SS
V
DD
V
SS
V
DD
V
SS
I/O
4
H I/O
17
V
DD
V
SS
V
SS
V
SS
V
DD
I/O
5
J NC V
SS
V
DD
V
SS
V
DD
V
SS
NC
K I/O
18
V
DD
V
SS
V
SS
V
SS
V
DD
I/O
6
L I/O
19
V
SS
V
DD
V
SS
V
DD
V
SS
I/O
7
M I/O
20
V
DD
V
SS
V
SS
V
SS
V
DD
I/O
8
N I/O
21
V
SS
V
DD
V
SS
V
DD
V
SS
I/O
9
P I/O
22
V
DD
V
SS
V
SS
V
SS
V
DD
I/O
10
R I/O
23
A NCNCNC AI/O
11
T NC A A WE AANC
U NC A A OE AANC
Note
1. NC pins are not connected on the die.
Description –10 Unit
Maximum Access Time 10 ns
Maximum Operating Current 175 mA
Maximum CMOS Standby Current 25 mA
Pin Configuration
Figure 1. 119-Ball PBGA (
Top View)
[1]
Document Number: 38-05610 Rev. *D Page 2 of 11
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CY7C1012DV33
Maximum Ratings
Notes
2. V
IL
(min) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns.
3. CE
indicates a combination of all three chip enables. When active LOW, CE indicates the CE1 or CE
2 ,
or CE3 is LOW. When HIGH, CE indicates the CE
1 , CE2 ,
and
CE
3
are HIGH.
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied ............................................–55°C to +125°C
Supply Voltage on V
DC Voltage Applied to Outputs
in High-Z State
DC Input Voltage
Relative to GND
CC
[2]
..................................–0.5V to VCC + 0.5V
[2]
...............................–0.5V to VCC + 0.5V
[2]
....–0.5V to +4.6V
Current into Outputs (LOW) ..................... ... ................20 mA
Static Discharge Voltage............................................>2001V
(MIL-STD-883, Method 3015)
Latch Up Current.....................................................>200 mA
Operating Range
Range
Industrial –40°C to +85°C3.3V ± 0.3V
Ambient
T emperature
V
CC
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
V
V
V
V
I
I
I
I
I
OH
OL
IH
IL
IX
OZ
CC
SB1
SB2
[2]
Output HIGH Voltage VCC = Min, IOH = –4.0 mA 2.4 V
Output LOW Voltage VCC = Min, IOL = 8.0 mA 0.4 V
Input HIGH Voltage 2.0 VCC + 0.3 V
Input LOW Voltage –0.3 0.8 V
Input Leakage Current GND < VI < V
Output Leakage Current GND < V
VCC Operating Supply
Current
Automatic CE Power Down
Current —TTL Inputs
Automatic CE Power Down
Current —CMOS Inputs
VCC = Max, f = f
I
= 0 mA CMOS levels
OUT
Max VCC, CE > V
VIN > VIH or VIN < VIL, f = f
Max VCC, CE > VCC – 0.3V,
V
> VCC – 0.3V, or VIN < 0.3V, f = 0
IN
CC
< VCC, output disabled –1 +1 μA
OUT
MAX
IH
[3]
= 1/t
RC
MAX
–10
Min Max
Unit
–1 +1 μA
175 mA
30 mA
25 mA
Document Number: 38-05610 Rev. *D Page 3 of 11
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CY7C1012DV33
Capacitance
90%
10%
3.0V
GND
90%
10%
All input pulses
3.3V
OUTPUT
5 pF*
(a)
(b)
R1 317 Ω
R2
351Ω
Fall Time:> 1V/ns
(c)
OUTPUT
50Ω
Z0= 50Ω
V
TH
= 1.5V
30 pF*
*
Capacitive Load consists of all
components of the test environment
Rise Time > 1V/ns
*Including jig
and scope
Note
4. Valid SRAM operation does not occur u ntil t he power sup plies ha ve rea ched t he minimum o peratin g V
DD
(3.0V). 100μs (t
power
) after reaching the minimum operating
V
DD
, normal SRAM operation begins including reduction in VDD to the data retention (V
CCDR
, 2.0V) voltage.
Tested initially and after any design or process chang es that may affect these parameters
.
Parameter Description Test Conditions Max Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V 8 pF
I/O Capacitance 10 pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions
Θ
Θ
Thermal Resistance
JA
(junction to ambient)
Thermal Resistance
JC
(junction to case)
Still air, soldered on a 3 × 4.5 inch,
four layer printed circuit board
Figure 2. AC Test Loads and Waveforms
[4]
119-Ball
PBGA
20.31 °C/W
8.35 °C/W
Unit
Document Number: 38-05610 Rev. *D Page 4 of 11
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