Cypress CY7C1007BN, CY7C107BN User Manual

CY7C107BN

CY7C1007BN

1M x 1 Static RAM

Features

•High speed
—t

= 15 ns

AA

• CMOS for optimum speed/power

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

Functional Description

The CY7C107BN and CY7C1007BN are high-performance
CMOS static RAMs organized as 1,048,576 words by 1 bit.
Easy memory expansion is provided by an active LOW Chip
Enable (CE
automatic power-down feature that reduces power
consumption by more than 65% when deselected.

Writing to the devices is accomplished by taking Chip Enable
(CE

) and Write Enable (WE) inputs LOW. Data on the input pin

(D

IN

address pins (A

) and three-state drivers. These devices have an

) is written into the memory location specified on the

through A19).

0

Reading from the devices is accomplished by taking Chip
Enable (CE

) LOW while Write Enable (WE) remains HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the data output
(D

) pin.

OUT

The output pin (D
when the device is deselected (CE
operation (CE

and WE LOW).

) is placed in a high-impedance state

OUT

HIGH) or during a write

The CY7C107BN is available in a standard 400-mil-wide SOJ;
the CY7C1007BN is available in a standard 300-mil-wide SOJ

LogicBlockDiagram Pin Configuration

SOJ

A
A
A
A
A
A

NC
A
A
A
A

D

OUT

WE

GND

10
11
12
13
14
15

16
17

18
19

Top View

1
2
3
4
5
6
7
8
9
10
11
12
13
14

28
27
26
25

24
23
22
21
20
19
18
17
16
15

D

IN

INPUT BUFFER

A

0

A

1

A

2

A

3

A

4

A

5

A

6

A

7

A

8

512 x 2048

ARRA

ROW DECODER

COLUMN

DECODER

Y

D

OUT

SENSE AMPS

POWER

DOWN

CE

V
A
A

A
A
A

A
NC
A
A
A
A
D

CE

CC
9
8

7
6
5

4
3

2
1
0

IN

9

A

A10A11A

13

A12A14A16A

A17A18A

19

15

WE

Selection Guide

7C107BN-15

7C1007BN-15

Maximum Access Time (ns) 15
Maximum Operating Current (mA) 80
Maximum CMOS Standby Current I

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-06426 Rev. ** Revised February 1, 2006

(mA) 2

SB2

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CY7C107BN

CY7C1007BN

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature ..................................-65°C to +150°C

Ambient Temperature with

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current.....................................................>200 mA

Operating Range

Power Applied..............................................-55°C to +125°C

Supply Voltage on V
DC Voltage Applied to Outputs

in High Z State

[1]

DC Input Voltage

Relative to GND

CC

.................................... -0.5V to VCC + 0.5V

[1]

..................................-0.5V to VCC + 0.5V

[1]

.....-0.5V to +7.0V

Commercial 0°C to +70°C 5V ± 10%
Industrial -40°C to +85°C 5V ± 10%

Electrical Characteristics Over the Operating Range

Parameter Description T est Conditions

V

OH

V

OL

V

IH

V

IL

I

IX

I

OZ

I

OS

I

CC

I

SB1

I

SB2

Capacitance

Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 V
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 V
Input HIGH Voltage 2.2 V
Input LOW Voltage
Input Leakage Current GND < VI < V

[1]

CC

Output Leakage Current GND < VI < VCC,

Output Disabled

Output Short Circuit

[3]

Current
VCC Operating Supply

Current
Automatic CE Power-Down

Current— TTL Inputs
Automatic CE Power-Down

Current — CMOS Inputs

[4]

VCC = Max., V

VCC = Max., I

MAX

= 1/t

f = f

= GND -300 mA

OUT

= 0 mA,

OUT

RC

Max. VCC, CE > VIH, VIN >V
V

< VIL, f = f

IN

MAX

Max. VCC, CE > VCC – 0.3V,
V

> VCC – 0.3V or VIN < 0.3V, f = 0

IN

Range Ambient Temperature

7C107BN-15

7C1007BN-15

Min. Max. Unit

+ 0.3 V

CC

-0.3 0.8 V

-1 +1 mA

–5 +5 mA

80 mA

IH

or

20 mA

2mA

[2]

V

CC

Parameter Description Test Conditions Max. Unit

: Addresses Input Capacitance TA = 25 × C, f = 1 MHz,

C

IN

: Controls 10 pF

C

IN

C

OUT

Notes:

(min.) = –2.0V for pulse durations of less than 20 ns.

1. V

IL

is the “Instant On” case temperature.

2. T

A

3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

4. Tested initially and after any design or process ch anges that may affect these parameters.

Output Capacitance 10 pF

V

CC

= 5.0V

7pF

Document #: 001-06426 Rev. ** Page 2 of 7

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CY7C107BN

CY7C1007BN

AC Test Loads and Waveforms

Ω

5V

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

Equivalentto: THÉ VENIN EQUIVALENT

Switching Characteristics

R1 480

R2

255Ω

(a) (b)

OUTPUT 1.73V

167Ω

5V

OUTPUT

5pF

INCLUDING

JIG AND

SCOPE

[5]

Over the Operating Range

Parameter Description Min. Max. Unit

READ CYCLE

t

RC

t

AA

t

OHA

t

ACE

t

LZCE

t

HZCE

t

PU

t

PD

WRITE CYCLE

t

WC

t

SCE

t

AW

t

HA

t

SA

t

PWE

t

SD

t

HD

t

LZWE

t

HZWE

Notes:

5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified

6. At any given temperature and voltage condition, t

7. t

8. The internal write time of the memory is defined by the overlap of CE

and 30-pF load capacitance.

I

OL/IOH

and t

HZCE

of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.

[8]

are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage .

HZWE

Read Cycle Time 15 ns
Address to Data Valid 15 ns
Data Hold from Address Change 3 ns
CE LOW to Data Valid 15 ns
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up 0 ns
CE HIGH to Power-Down 15 ns

Write Cycle Time 15 ns
CE LOW to Write End 12 ns
Address Set-Up to Write End 12 ns
Address Hold from Write End 0 ns
Address Set-Up to Write Start 0 ns
WE Pulse Width 12 ns
Data Set-Up to Write End 8 ns
Data Hold from Write End 0 ns
WE HIGH to Low Z
WE LOW to High Z

HZCE

R1 480Ω

[6]

[6, 7]

[6]
[6, 7]

is less than t

ALL INPUT PULSES

90%

90%

10%

≤ 3

ns

R2

255Ω

3.0V

GND

≤ 3

10%

ns

7C107BN-15

7C1007BN-15

3ns

7ns

3ns

7ns

and t

LZCE

LOW and WE LOW. CE and WE must be LOW to initiate a write, a nd the t ransition of a ny

is less than t

HZWE

for any given device.

LZWE

Document #: 001-06426 Rev. ** Page 3 of 7

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