Cypress CY7C1006D, CY7C106D User Manual

CY7C106D

CY7C1006D

1-Mbit (256K x 4) Static RAM

Features

• Pin- and function-compatible with CY7C106B/CY7C1006B

• High speed

AA =

10 ns

—t

• Low active power

= 80 mA @ 10 ns

—I

CC

• Low CMOS standby power

—I

= 3.0 mA

SB2

• 2.0V Data Retention

• Automatic power-down when deselected

• CMOS for optimum speed/power

• TTL-compatible inputs and outputs

• CY7C106D available in Pb-free 28-pin 400-Mil wide Molded
SOJ package. CY7C1006D available in Pb-free 28-pin
300-Mil wide Molded SOJ package

Logic Block Diagram

Functional Description

[1]

The CY7C106D and CY7C1006D are high-performance
CMOS static RAMs organized as 262,144 words by 4 bits.
Easy memory expansion is provided by an active LOW Chip
Enable (CE

), an active LOW Output Enable (OE), and tri-state
drivers. These devices have an automatic power-down feature
that reduces power consumption by more than 65% when the
devices are deselected. The four input and output pins (IO
through IO3) are placed in a high-impedance state when:

• Deselected (CE

• Outputs are disabled (OE

• When the write operation is active (CE

HIGH)

HIGH)

and WE LOW)

Write to the device by taking Chip Enable (CE) and Write
Enable (WE

) inputs LOW. Data on the four IO pins (IO
through IO3) is then written into the location specified on the
address pins (A

through A17).

0

Read from the device by taking Chip Enable (CE) and Output
Enable (OE

) LOW while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins appears on the four IO pins.

0

0

INPUT BUFFER

A

1

A

2

A

3

A

4

A

5

A

6

A

7

A
A

CE

WE

OE

Note

1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.

8
9

ROW DECODER

256K x 4

ARRAY

COLUMN DECODER

15

12

11

A13A14A

A

A0A10A

A16A

SENSE AMPS

POWER
DOWN

17

IO

0

IO

1

IO

2

IO

3

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05459 Rev. *E Revised February 22, 2007

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CY7C106D

CY7C1006D

Pin Configuration

[2]

SOJ

Top View

A
A
A
A
A
A
A
A
A
A

A

CE
OE

GND

1

0

2

1

3

2

4

3

5

4

6

5

7

6
7

8
9

8

10

9

10

11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

V
A

A
A
A
A
A
A
NC
IO
IO
IO
IO

WE

CC

17

16

15

14

13

12

11

3

2

1

0

Selection Guide

CY7C106D-10

CY7C1006D-10

Maximum Access Time 10 ns

Maximum Operating Current 80 mA

Maximum Standby Current 3 mA

Unit

Note

2. NC pins are not connected on the die.

Document #: 38-05459 Rev. *E Page 2 of 11

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CY7C106D

CY7C1006D

Maximum Ratings

Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V

DC Voltage Applied to Outputs
in High-Z State

Relative to GND

CC

[3]

...................................–0.5V to VCC + 0.5V

[3]

... –0.5V to +6.0V

DC Input Voltage

Current into Outputs (LOW) ........................................ 20 mA

Static Discharge Voltage .......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current .................................................... > 200 mA

Operating Range

Range

Industrial –40°C to +85°C 5V ± 0.5V 10 ns

Electrical Characteristics (Over the Operating Range)

Parameter Description Test Conditions

V

OH

V

OL

V

IH

V

IL

I

IX

I

OZ

I

CC

Output HIGH Voltage IOH = –4.0 mA 2.4 V

Output LOW Voltage IOL = 8.0 mA 0.4 V

Input HIGH Voltage 2.2 V

Input LOW Voltage

Input Leakage Current GND < VI < V

[3]

CC

Output Leakage Current GND < VI < VCC, Output Disabled –1 +1 µA

VCC Operating Supply Current VCC = Max,

I

OUT

f = f

max

= 0 mA,

= 1/t

RC

[3]

............................... –0.5V to VCC + 0.5V

Ambient

Tem per atur e

V

CC

Speed

7C106D-10

7C1006D-10

Unit

Min Max

+ 0.5 V

CC

–0.5 0.8 V

–1 +1 µA

100 MHz 80 mA

83 MHz 72 mA

66 MHz 58 mA

I

SB1

I

SB2

Note

3. V

(min) = –2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns.

IL

Automatic CE Power-Down
Current—TTL Inputs

Automatic CE Power-Down
Current—CMOS Inputs

Max VCC, CE > VIH,
V

Max VCC, CE > VCC – 0.3V,
V

> VIH or VIN < VIL, f = f

IN

> VCC – 0.3V or VIN < 0.3V, f=0

IN

max

40 MHz 37 mA

10 mA

3mA

Document #: 38-05459 Rev. *E Page 3 of 11

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CY7C106D

CY7C1006D

Capacitance

[4]

Parameter Description Test Conditions Max Unit

CIN: Addresses Input Capacitance TA = 25°C, f = 1 MHz, VCC = 5.0V 7 pF

C

: Controls 10 pF

IN

C

OUT

Thermal Resistance

Parameter Description Test Conditions

Θ

JA

Θ

JC

AC Test Loads and Waveforms

* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT

Output Capacitance 10 pF

[4]

300-Mil

Wide SOJ

Thermal Resistance
(Junction to Ambient)

Thermal Resistance

Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board

59.16 58.76 °C/W

40.84 40.54 °C/W

(Junction to Case)

[5]

ALL INPUT PULSES

90%

10%

(b)

OUTPUT

Z = 50

Ω

50 Ω

1.5V

30 pF*

3.0V

GND

Rise Time: ≤ 3 ns

(a)

400-Mil

Wide SOJ

90%

10%

Fall Time: ≤ 3 ns

Unit

High-Z characteristics:

5V

OUTPUT

INCLUDING
JIG AND
SCOPE

5 pF

R1 480Ω

R2

255Ω

(c)

Notes

4. Tested initially and after any design or process changes that may affect these parameters.

5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).

Document #: 38-05459 Rev. *E Page 4 of 11

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