CYPRESS CY7C09349AV, CY7C09359AV User Manual

1

查询CY7C09349A-6AC供应商

CY7C09349AV

CY7C09359AV

3.3V 4K /8K x 18

Synchronous Dual-Port Static RAM

Features

• True dual-ported memory cells which all ow simulta­neous access of the same memory location

• Two Flow-Through/Pipelined devices

—4K x 18 organization (CY7C09349AV)
—8K x 18 organization (CY7C09359AV)

• Three Modes

—Flow-Through
—Pipelined
—Burst

• Pipelined outpu t mode on both ports allo ws fast 83-MHz
operation

• 0.35-micron CMOS for optimum speed/power

v

Logic Block Diagram

• High-speed clock to data access 9 and 12 ns (max.)

• 3.3V Low operating power
—A cti ve = 135 mA ( typi cal)
— Standby = 10 µA (typical)

• Fully synchronous int erf ace for easier operation

• Burst counters increment addresses internally
— Shorten cycle times
—Minimize bus noise
—Supported in Flow-Through and Pi peli ned m odes

• Dual Chip Enables f or easy depth expansi on

• Upper and lower byte controls for bus matching

• Aut omatic power-down

• Commercial and Industrial temperature ranges

Available in 100-pin TQFP

•

R/W

L

UB

L

CE

0L

CE

1L

LB

L

OE

L

FT/Pipe
I/O9L–I/O

I/O0L–I/O

A
CLK

ADS
CNTEN
CNTRST

L

17L

8L

[1] [1]

0L–A11/12L

L

L

L

12/13

L

0/1

9

9

1
0

0/1

1b

0b 1a 0a

ba

Counter/

Address

Register

Decode

I/O

Control

True Dual-Ported

RAM Array

I/O

Control

0/1

1b

0b1a0a

ba

Counter/

Address

Register

Decode

1
0

0/1

9

9

12/13

R/W

CE
CE

FT/Pipe

I/O9R–I/O

I/O0R–I/O

A0R–A

11/12R

CLK

ADS

CNTEN

CNTRST

UB

LB

OE

R
R

0R
1R

R
R

R

17R

8R

R
R
R
R

Notes:

1. A

for 4K; A0–A12 for 8K devices.

0–A11

For the most recent informati on, visit the Cypress web site at www .cypress. com

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Nove mber 13, 2000

CY7C09349AV

CY7C09359AV

Functional Description

A HIGH on CE

down the internal circu itry to reduce the static power consu mp­The CY7C09349AV and CY7C09359AV are high-speed 3.3V
synchronous CMOS 4K and 8K x 18 dual-port static RAMs.
Two ports are provide d, permitt ing i ndependent , si mul taneous
access for rea ds and writes to an y lo catio n in memory.

[2]

Reg­isters on contr ol, addr ess, a nd data lin es allo w f o r mini mal set­up and hold times . In pipelined out put mode, dat a is registere d
for decr ease d cycle t ime . Cloc k to dat a v ali d t
lined). Flow-through mode can also be used to bypass the

= 9 ns (pipe-

CD2

pipelined output register to eliminate access latency. In flow­through mode data will be available t
dress is clocked into the device. Pipelined output or flow­through mode is selected via the FT

= 18 ns after the ad-

CD1

/Pipe pin.

Each port contains a burs t co unter on the i nput address r egis­ter. The internal write pulse width is indep endent of the LOW­to-HIGH tra nsition of the clock signal . The internal write pulse
is self-t imed to allow the sho rtest possible cycle t ime s.

tion. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
pipelined mode, one cycle is required with CE
HIGH to reactivate the outputs.

Counter enabl e inputs are pro vided to sta ll the oper ation of the
address input an d utilize the internal address gener ated by t he
internal counter for fast interleaved memor y applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS
the address counter will increment on each LOW-to-HIGH
transition of that port’s clock signal. This will read/write one
word from/into ea ch su cces siv e addres s locat ion unt il CNTEN
is deasserted. The counter can address the entire memory
array an d will loop back to the start. Counter Reset (CNTRST
is used to reset the burst counter.

All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.

Note:

2. When simultaneously writing to the same location, final value cannot be guaranteed.

or LOW on CE1 for one clock cy cle will power

0

LOW and CE

0

). When the port’s Count Enable (CNTEN) is asserted,

1

)

2

Pin Configuration

A9L
A10L
A11L

[3]

A12L

NC
NC
NC

LBL

UBL
CE0L
CE1L

CNTRSTL

R/WL

OEL

VCC

FT/PIPEL

I/O17L
I/O16L

GND
I/O15L
I/O14L
I/O13L
1/012L
I/O11L
I/O10L

CY7C09349AV

CY7C09359AV

100-Pin TQFP (Top View)

A8L

A7L

A6L

A5L

A4L

A3L

A1L

A2L

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

CY7C09359AV (8K x 18)

CY7C09349AV (4K x 18)

3332313029282726

CLKL

CNTENL

A0L

92 91 90 848587 868889 83 82 81 7678 77798093949596979899100

34 35 36 424139 403837 43 44 45 5048 494746

GND

GND

ADSL

ADSR

CNTENR

A0R

CLKR

A1R

A2R

A3R

A4R

A5R

A6R

A7R

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

A8R
A9R
A10R
A11R

[3]

A12R
NC
NC
NC
LBR
UBR
CE0R
CE1R
CNTRSTR
R/WR
GND
OER
FT/PIPER
I/O17R
GND
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R

VCC

I/O7L

I/O8L

I/O9L

I/O4L

I/O5L

I/O6L

GND

I/O2L

I/O3L

GND

I/O0L

I/O1L

I/01R

I/O0R

I/O4R

I/O2R

I/O3R

VCC

I/O7R

I/O6R

I/O5R

I/10R

I/O9R

I/O8R

Selectio n Guide

CY7C09349AV
CY7C09359AV

-9

f

(MHz) (Pipelined) 67 50

MAX2

Max Access Time (ns) (Clock to Data, Pipelined) 9 12
Typical Operating Current I
Typical Standby Current for I
Typical Standby Current for I

Shaded areas contain advance information.

Note:

3. This pin is NC for CY7C09349AV.

(mA) 135 115

CC

(mA) (Both Ports TTL Level) 20 20

SB1

(µA) (Both P orts CMOS Lev el) 10 µA 10 µA

SB3

3

CY7C09349AV
CY7C09359AV

-12

Pin Definitions

Left Port Right Port Description

A0L–A

12L

ADS

L

CE0L,CE

CLK

L

CNTEN

L

CNTRST

I/O0L–I/O
LB

L

UB

L

OE

L

R/W

L

FT/PIPE

GND Ground Input.
NC No Connect.
V

CC

L

1L

L

17L

A0R–A

12R

ADS

R

CE0R,CE

CLK

R

CNTEN

CNTRST

I/O0R–I/O
LB

R

UB

R

OE

R

R/W

R

FT/PIPE

Address Inputs (A0–A

for 4K, A0–A

11

for 8K devices).

12

Address Strobe I nput. Used as an addr ess qualifier . This signal should be ass erted LOW during
normal read or write transactions. Asserting this signal LOW also loads the burst address
counter with data present on the I/O pins.

Chip Enable Inpu t. To select ei ther the left or right port, both CE0 AND CE1 must be asserted

1R

to their active states (C E

≤ VIL and CE1 ≥ VIH).

0

Clock Signal. This input can be free running or strobed. Maximum clock input rate is f

R

Counter Enable In put. Asserting this signal LOW increments the b urst address coun ter of it s
respectiv e port on each rising edge of CLK. CNTEN
LOW.

Counter Reset Input. Asserting thi s signal LO W resets t he burs t address count er of its res pec-

R

tive port to zero. CNTRST
Data Bus Input/Output (I/O0–I/O15 for x16 devi c es).

17R

is not disab led by asserting ADS or CNTEN.

Lower Byte Select Input. Asserting this signal LOW enables read and write oper ations to the
lower byte (I/O
the LB

and OE signals m ust be asserted to driv e out put dat a on the l ower b yte of the dat a pi ns.

–I/O8 for x18, I/O0–I/O7 for x16) of the memory arra y. For read oper ations both

0

Upper Byte Select Input. Same function as LB, but to the upper byte (I/O
Output Enable Input. Thi s signal must be ass erted LOW to enable t he I/O data pins during read

operations.
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.

For read operations, assert this pin HIGH.
Flow-Through/ Pipelined Select Input. For flow-through mode operation, assert this pin LOW.

R

For pipelined mode operation, assert this pin HIGH.

Power Input.

CY7C09349AV

CY7C09359AV

.

MAX

is disab led if ADS or CNTRST are as serted

8/9L

–I/O

15/17L

).

Maximum Ratings

(Abov e which the useful life may be impair ed. For user guide­lines, not tested.)

Storage Temperature ............ .. .......... ... ...... –65

Ambient Temperature with

Power Applied .............................................–55

Supply Voltage to Gr o u nd Potent ia l ..... ......... . –0.5V to +4.6V

DC Voltage Applied to

Outputs in High Z State ...........................–0.5V to V

DC Input Voltage......................................–0.5V to V

Notes:

4. Industrial parts are available in CY7C09359AV only.

°

C to +150°C

°

C to +125°C

+0.5V

CC

+0.5V

CC

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage .......... ............ ............ .........>2001V

Latch-Up Current .....................................................>200 mA

Operating Range

Range

Commercial 0°C to +70°C 3.3V ± 300 mV
Industrial

[4]

Ambient

Temperature V

CC

–40°C to +85°C 3.3V ± 300 mV

4

CY7C09349AV

CY7C09359AV

Electrical Characteristics

Over the Operating Range

Parameter Description

V
V
V
V
I
I

I

I

I

I

OH
OL
IH

IL
OZ
CC

SB1

SB2

SB3

SB4

Output HIGH Voltage (V
Output LOW Voltage (V

CC

= Min., I

CC

= Min., I

Input HIGH Voltage 2.0 2.0 V
Input LOW Voltage 0.8 0.8 V
Output Leakage Current –10 10 –10 10 µA
Operating Current (V

I

= 0 mA) Outputs Disabled

OUT

Standby Current (Both Ports TTL

[5]

Level)

CEL & CER ≥ VIH, f =f

CC

= Max.,

Standby Current (One Port TTL Lev el)
CE

≥ VIH, f =f

R

Standby Current (Bot h Ports CMOS

[5]

Level)
Standby Current (One Port CMOS

[5]

Level)

MAX

CEL & CER ≥ V

– 0.2V, f = 0

CC

CEL | CER ≥ VIH, f = f

MAX

MAX

CY7C09349AV
CY7C09359AV

-9 -12

Min. Typ. Max. Min. Typ. Max.

= –4.0 mA) 2.4 2.4 V

OH

= +4.0 mA) 0.4 0.4 V

OH

Com’l. 135 230 115 180 mA
Ind.

[4]

155 250 mA

Com’l. 20 75 20 70 mA

[5]

CEL |

[4]

Ind.
Com’l. 95 155 85 140 mA

[4]

Ind.

30 80 mA

95 150 mA
Com’l. 10 500 10 500 µA
Ind.

[4]

10 500 µA
Com’l. 85 115 75 100 mA
Ind.

[4]

85 110 mA

Unit

Capacitance

Parameter Description Test Conditions Max. Unit

C

IN

C

OUT

Note:

5. CE

and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH).

L

Input Capacitance TA = 25°C, f = 1 MHz,

V

= 3.3V

Output Capacitance 10 pF

CC

10 pF

5