CYPRESS CY7C09279, CY7C09289, CY7C09379, CY7C09389 User Manual

25/0251

查询CY7C09279供应商

CY7C09279/89
CY7C09379/89

32K/64K x16/18

Synchronous Dual Port Static RAM

Features

• True dual-ported memory cells which allow simulta­neous access of the same memory location

• Six Flow-Through/Pipelined devices

—32K x 16/18 organization (CY7C09279/379)
—64K x 16/18 organization (CY7C09289/389)

• Three Modes

—Flow-Through
—Pipelined
—Burst

• Pipelined output mode on both ports allows fast 100­MHz cycle tim e

• 0.35-micron CMOS for optimum speed/power

• High-speed clock to data access 6.5
(max.)

[1]

/7.5/9/12 ns

• Low operating power
—Active = 195 mA (typical)

—Standby = 0.05 mA (typical)

• Fully synchronous interface for easier operation

• Burst counters increment addresses internally
—Shorten cycle times
—Minimize bus noise
—Supported in Flow-Through and Pipelined modes

• Dual Chip Enables for easy depth expansion

• Upper and Lower Byte Controls for Bus Matching

• Automatic power-down

• Commercial and Industrial temperature ranges

• Available in 100-pin TQFP

• Pin-compatible and functi onally equivalent to IDT70927

and IDT709279

Logic Block Diagram

R/W

L

UB

L

CE

0L

CE

1L

LB

L

OE

L

FT/Pipe
I/O

I/O0L–I/O
A0L–A

CLK
ADS
CNTEN
CNTRST

L

[2]

–I/O

8/9L

15/17L

[3]

7/8L

[4] [4]

14/15L

L

L

L

L

8/9

8/9

15/16

1
0

0/1

1b

0b 1a 0a

0/1

ba

Counter/

Address

Register

Decode

I/O

Control

True Dual-Ported

RAM Array

I/O

Control

0/1

1b

0b1a0a

ba

Counter/

Address

Register

Decode

R/W

R

UB

R

CE

1
0

0/1

8/9

I/O

–I/O

8/9R

8/9

I/O0R–I/O

15/16

A0R–A

CNTRST

CE

LB

OE

FT/Pipe

[2]

15/17R

[3]

7/8R

14/15R

CLK

ADS

CNTEN

0R
1R

R
R

R

R
R
R
R

Notes:

1. See page 6 for Load Conditions.
–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.

2. I/O

8

3. I/O

–I/O7 for x16 devices. I/O0–I/O8 for x18 devices.

0

4. A

for 32K; A0–A15 for 64K devices.

0–A14

For the most recent information, visit the Cypress web site at www.cypress.com

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06040 Rev. ** Revised September 19, 2001

CY7C09279/89

CY7C09379/89

Functional Description

The CY7C09279/89 and CY7C09379/89 are high-speed syn­chronous CMOS 32K, an d 64K x 16 /18 dual-p ort static RAMs.
Two po rts are prov ided, permitting i ndependent, s imultaneou s
access for reads and writes to any loca tion in mem ory.

[5]

Reg­isters on control, address, a nd data li nes allow fo r minimal set­up and hold times. In pipelin ed output mode, data is registered
for decreased cycle time. Clock to data valid t
(pipelined). Flow-through mode can also be used to bypass

CD2

= 6.5 ns

[1]

the pipelined output register to eliminate access latency. In
flow-through mode da ta will be avail able t
address is clocked into the device. Pipelined output or flow­through mode is selected via the FT

/PIPE pin.

= 15 ns after the

CD1

Each port contains a bu rst co un ter on the i nput a ddress re gis­ter. The internal write pulse width is independent of the LOW­to-HIGH transition of the cl ock si gn al. The internal write puls e
is self-timed to allow the shortest possible cycle times.

Pin Configurations

100-Pin TQFP (Top View)

A8L

A7L

A6L

A5L

A4L

CNTRSTL

[7]

FT/PIPEL

A10L
A11L
A12L
A13L
A14L

A15L

UBL
CE0L
CE1L

VCC

R/WL

OEL

GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L

A9L

NC
NC

LBL

A3L

A1L

A2L

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

24
25

CY7C09289 (64K x 16)
CY7C09279 (32K x 16)

3332313029282726

CLKL

CNTENL

A0L

92 91 90 848587 868889 83 82 81 7678 77798093949596979899100

34 35 36 424139 403837 43 44 45 5048 494746

A HIGH on CE
down the internal circ uitry to reduce the static power consump-

or LOW on CE1 for one clock cycl e will po wer

0

tion. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
pipelined mode, one c ycl e is req uired wi th CE
HIGH to reactivate the outputs.

LOW and CE

0

Counter enable input s are provided to s tall the operation of the
address input and uti lize the internal address generated b y the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe

). When the port’s Count Enable (CNTEN) is asserted,

(ADS
the address counter will increment on each LOW-to-HIGH
transition of that port’s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST
is used to reset the burst counter.

All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.

GND

ADSR

ADSL

CLKR

CNTENR

A0R

A1R

A2R

A3R

A4R

A5R

A6R

A7R

A8R

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

A9R
A10R
A11R
A12R
A13R
A14R

[6][6]

A15R
NC
NC
LBR
UBR
CE0R
CE1R
CNTRSTR
GND
R/WR
OER
FT/PIPER
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R

1

)

[7]

VCC

I/O7L

I/O8L

Notes:

5. When writing simultaneously to the same location, the final value cannot be guaranteed.

6. This pin is NC for CY7C09279.

7. For CY7C09279, pin #18 connected to V
through device.

I/O9L

is equivalent to an IDT x16 pipelined device; connecting pin #18 and #58 to GND is equivalent to an IDT x16 flow-

CC

I/O4L

I/O5L

I/O6L

GND

I/O2L

I/O3L

GND

I/O0L

I/O1L

I/O0R

I/01R

I/O4R

I/O2R

I/O3R

VCC

I/O7R

I/O6R

I/O5R

NC

I/O9R

I/O8R

Document #: 38-06040 Rev. ** Page 2 of 18

Pin Configurations (continued)

A8L

A7L

A6L

A9L
A10L
A11L
A12L
A13L
A14L

A15L

LBL

UBL
CE0L
CE1L

CNTRSTL

R/WL

OEL

VCC

FT/PIPEL

I/O17L
I/O16L

GND
I/O15L
I/O14L
I/O13L
1/012L

I/O11L
I/O10L

[8]

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

100-Pin TQFP (Top View)

A5L

A4L

A3L

A1L

A2L

CLKL

CNTENL

A0L

92 91 90 848587 868889 83 82 81 7678 77798093949596979899100

GND

ADSL

CY7C09389 (64K x 18)
CY7C09379 (32K x 18)

34 35 36 424139 403837 43 44 45 5048 494746

3332313029282726

GND

CY7C09279/89

CY7C09379/89

CNTENR

CLKR

A0R

A1R

A2R

A3R

A4R

A5R

A6R

A7R

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

A8R
A9R
A10R
A11R
A12R
A13R
A14R

[8]

A15R
LBR
UBR
CE0R
CE1R
CNTRSTR
R/WR
GND
OER
FT/PIPER
I/O17R
GND
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R

ADSR

I/O9L

I/O8L

VCC

I/O7L

I/O6L

I/O5L

I/O4L

I/O3L

I/O2L

GND

I/O1L

I/O0L

GND

I/O0R

I/01R

I/O2R

I/O3R

I/O4R

I/O5R

I/O6R

VCC

I/O7R

I/O8R

I/O9R

I/10R

Selection Guide

CY7C09279/89
CY7C09379/89

(MHz) (Pipelined) 100 83 67 50

f

MAX2

Max Access Time (ns)

[1]

-6

6.5 7.5 9 12

(Clock to Data, Pipelined)
Typical Operating Current I
Typical Standby Current for I

(Both Ports TTL Level)
Typical Standby Current for I

(Both Ports CMOS Level)

Note:

8. This pin is NC for CY7C09379.

(mA) 250 235 215 195

CC

SB1

SB3

(mA)

(mA)

45 40 35 30

0.05 0.05 0.05 0.05

Document #: 38-06040 Rev. ** Page 3 of 18

CY7C09279/89
CY7C09379/89

-7

CY7C09279/89
CY7C09379/89

-9

CY7C09279/89
CY7C09379/89

-12

Pin Definitions

Left Port Right Port Description

A0L–A

15L

ADS

L

CE0L,CE

CLK

L

CNTEN

L

CNTRST

I/O0L–I/O
LB

L

UB

L

OE

L

R/W

L

FT/PIPE

GND Ground Input.
NC No Connect.
V

CC

L

1L

L

17L

A0R–A

15R

ADS

R

CE0R,CE

CLK

R

CNTEN

CNTRST

I/O0R–I/O
LB

R

UB

R

OE

R

R/W

R

FT/PIPE

Address Inputs (A0–A

for 32K, A0–A

14

for 64K devices).

15

Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part usin g an exter nally supplied address. Ass erting this s ignal LOW a lso loads t he
burst counter with the address present on the address pins.

Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted

1R

to their active states (CE0 ≤ VIL and CE1 ≥ VIH).
Clock Signal. This input can be free running or strobed. Maximum clock input rate is f

R

Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each risi ng edge of CLK. CNTEN
LOW.

Counter Reset Input. As serting this s ignal LO W res ets th e burst a ddress counter of its respe c-

R

tive port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
Data Bus Input/Output (I/O0–I/O15 for x16 devices).

17R

Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the
lower byte. (I/O

and OE signals must be asserted t o drive output data on the lowe r byte o f the da ta pins.

the LB

–I/O8 for x18, I/O0–I/O7 for x16) of the memory array . For read operations both

0

Upper Byte Select Input. Same function as LB, but to the upper byte (I/O
Output Enable Input. This signa l must be asserted LOW to enable the I/O da ta pins during read

operations.
Read/Write Enable Inp ut. Thi s s ign al is asserte d LO W to write t o the du al po rt me mo ry arra y.

For read operations, assert this pin HIGH.
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.

R

For pipelined mode operation, assert this pin HIGH.

Power Input.

CY7C09279/89

CY7C09379/89

.

MAX

is disabled if ADS or CNTRST are asserted

8/9L

–I/O

15/17L

).

Maximum Ratings

(Above which the useful life may be im pai red. For user guide­lines, not tested.)

Storage Temperature................................. –65

Ambient Temperature with Power Applied..–55°C to +125°C

Supply Voltage to Ground Potential...............–0.3V to +7.0V

DC Voltage Applied to

Outputs in High Z State.................................–0.5V to +7.0V

DC Input Voltage............................................–0.5V to +7.0V

Note:

9. Industrial parts are available in CY7C09289 and Cy7C09389 only

°C to +150°C

Output Current into Outputs (LOW).............................20 mA

Static Discharge Voltage ...........................................>1100V

Latch-Up Current.....................................................>200 mA

Operating Range

Range

Commercial 0°C to +70°C 5V ± 10%
Industrial

[9]

Ambient

Temperature V

CC

–40°C to +85°C 5V ± 10%

Document #: 38-06040 Rev. ** Page 4 of 18

Electrical Characteristics Ov er the Op erat ing Range

[1]

-6

Parameter Description

V

V

V
V
I

OZ

I

CC

I

SB1

OH

OL

IH
IL

Output HIGH Voltage

= Min., IOH= –4.0 mA)

(V

CC

Output LOW V o lta ge
(VCC= Min., IOH= +4.0 mA)

Input HIGH Vo ltage 2.2 2.2 2.2 2.2 V
Input LOW Voltage 0.8 0.8 0.8 0.8 V
Output Leakage Current –10 10 –10 10 –10 10 –10 10 µA
Operating Current

=Max.,

(V

CC

=0mA)

I

OUT

Outputs Disabled
Standby Current (Both

Ports TTL Level)

[10]

CEL & CER ≥ VIH,
f=f

MAX

I

SB2

Standby Current (One
Port TTL Level)

[10]

CEL | CER ≥ VIH,
f=f

MAX

I

SB3

I

SB4

Standby Current (Both
Ports CMOS Level)
CEL & CER ≥ V

0.2V, f = 0
Standby Current (One

Port CMOS Level)

CC

[10]

–

[10]

CEL | CER ≥ VIH,
f=f

MAX

Com’l. 250 450 235 420 215 360 195 300 mA
Ind.

Com’l. 45 115 40 105 35 95 30 85 mA
Ind.

Com’l. 175 235 160 220 145 205 125 190 mA
Ind.

Com’l. 0.05 0.5 0.05 0.5 0.05 0.5 0.05 0.5 mA
Ind.

Com’l. 160 200 145 185 130 170 110 150 mA
Ind.

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

2.4 2.4 2.4 2.4 V

[9]

[9]

[9]

[9]

[9]

CY7C09279/89

CY7C09379/89

CY7C09279/89
CY7C09379/89

-7 -9 -12
Unit

0.4 0.4 0.4 0.4 V

245 410 mA

50 110 mA

160 220 mA

0.05 0.5 mA

145 185 mA

Capacitance

Parameter Description Test Conditions Max. Unit

C

IN

C

OUT

Note:

and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH).

10. CE

L

Document #: 38-06040 Rev. ** Page 5 of 18

Input Capacitance TA = 25°C, f = 1 MHz,
Output Capacitance 10 pF

VCC = 5.0V

10 pF

AC Test Loads

OUTPUT

C= 30pF

(a) Normal Load (Load 1)

5V

R1 = 893Ω

R2 = 347

CY7C09279/89

CY7C09379/89

5V

R

= 250Ω

OUTPUT

C=

30 pF

Ω

(b) Thévenin Equivalent (Load1)

TH

V

TH

=1.4V

OUTPUT

C= 5pF

(c)Three-State Delay(Load 2)

(Used for t

CKLZ

, t

OLZ

including scope and jig)

R1 = 893Ω

R2 = 347Ω

, & t

OHZ

AC Test Loads (Applicable to -6 only)

Z0 = 50

Ω

R = 50

OUTPUT

C

(a) Load 1 (-6 only)

Ω

VTH=1.4V

0.60

0.50

0.40

0.30

0.20

[11]

3.0V

GND

≤

3ns

ALL INPUTPULSES

10%

90%

90%

10%

ns

3

≤

0.1 0

(ns) for all -12 access ti mes

∆

0.00
1 0 1 5 20 25 30 35

Capacitance (pF)

(b) Load Derating Curve

Note:

11. Test Conditions: C = 10 pF.

Document #: 38-06040 Rev. ** Page 6 of 18