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CY7C09199V
User Manual
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User Manual
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Cypress CY7C09199V, CY7C09079V, CY7C09179V, CY7C09089V, CY7C09189V User Manual

...
CY7C09079V/89V/99V CY7C09179V/89V/99V
3.3V 32K/64K/128K x 8/9
Synchronous Dual-Port Static RAM

Logic Block Diagram

R/W
L
CE
0L
CE
1L
OE
L
FT/Pipe
L
I/O0L–I/O
7/8L
Control
A
0–A14/15/16L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
R/W
R
1
0
0/1
CE
0R
CE
1R
OE
R
1
0/1
0
FT/Pipe
R
I/O0R–I/O
7/8R
I/O
Control
A
0–A14/15/16R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
1
0
0/1
1
0/1
0
I/O
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
Counter/
Address
Register
Decode
8/9 8/9
[2]
[2]
[3]
[3]
15/16/17
15/16/17
CY7C09079V/89V/99V CY7C09179V/89V/99V

Features

access of the same memory location
■ 6 Flow-Through and Pipelined devices
■ 32K x 8/9 organizations (CY7C09079V/179V)
■ 64K x 8/9 organizations (CY7C09089V/189V)
■ 128K x 8/9 organizations (CY7C09099V/199V)
■ 3 Modes
■ Flow-Through
■ Pipelined
■ Burst
■ Pipelined output mode on both ports enables fast 100 MHz
operation
■ 0.35-micron CMOS for optimum speed and power
■ High speed clock to data access 6.5[1]/7.5[1]/9/12 ns (max.)
■ 3.3V low operating power
■ Active= 115 mA (typical)
■ Standby= 10 μA (typical)
■ Fully synchronous interface for easier operation
■ Burst counters increment addresses internally
■ Shorten cycle times
■ Minimize bus noise
■ Supported in Flow-Through and Pipelined modes
■ Dual Chip Enables for easy depth expansion
■ Automatic power down
■ Commercial and Industrial temperature ranges
■ Available in 100-pin TQFP
■ Pb-free packages available
Notes
1. See page 6 for Load Conditions. –I/O7 for x8 devices, I/O0–I/O8 for x9 devices.
2. I/O
0
3. A
0–A14
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-06043 Rev. *C Revised December 10, 2008
for 32K, A0–A15 for 64K, and A0–A16 for 128K devices.
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CY7C09079V/89V/99V CY7C09179V/89V/99V

Functional Description

1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
NC
NC
A7R
A8R
A9R
A10R
A15R
A12R
A14R
GND
NC
NC
CE
0R
A13R
A11R
NC
NC
CE1R
CNTRST
R
R/WR
OER
FT
/PIPER
GND
NC
A16R
58
57
56
55
54
53
52
51
NC
NC
A7L
A8L
A9L
A10L
A15L
A12L
A14L
VCC
NC
NC
CE0L
A13L
A11L
NC
NC
CE1L
CNTRSTL
R/W
L
OEL
FT
/PIPEL
NC
NC
A16L
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
NCNCA6L
A5L
A4L
A3L
CLKL
A1L
CNTENL
GND
ADSR
A0R
A1R
A0L
A2L
CLKR
CNTENR
A2R
A3R
A4R
A5R
A6RNCNC
ADSL
34 35 36 424139 403837 43 44 45 5048 494746
NC
NC
NC
I/O7R
I/O6R
I/O5R
I/01R
I/O3R
I/O2R
GND
VCC
GND
I/O2L
VCC
I/O4R
I/O0L
I/O1L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
NC
GND
I/O0R
3332313029282726
[5]
[5]
[6]
[6]
[7]
[7]
The CY7C09079V/89V/99V and CY7C09179V/89V/99V are high speed synchronous CMOS 32K, 64K, and 128K x 8/9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.
[4]
Registers on control, address, and data lines enable minimal setup and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid t used to bypass the pipelined output register to eliminate access
CD2
= 6.5 ns
latency. In flow-through mode, data is available t the address is clocked into the device. Pipelined output or
[1]
(pipelined). Flow-through mode can also be
= 18 ns after
CD1
flow-through mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address register.
The internal write pulse width is independent of the LOW-to-HIGH transition of the clock signal. The internal write pulse is self-timed to enable the shortest possible cycle times.

Pin Configurations

Figure 1. 100-Pin TQFP (Top View) - CY7C09099V (128K x 8), CY7C09089V (64K x 8),CY7C09079V (32K x 8)
A HIGH on CE the internal circuitry to reduce the static power consumption. The
or LOW on CE1 for one clock cycle powers down
0
use of multiple Chip Enables enables easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the address input and use the internal address generated by the internal counter for fast interleaved memory applications. A port’s burst counter is loaded with the port’s Address Strobe (ADS
). When the port’s Count Enable (CNTEN) is asserted, the address counter increments on each LOW-to-HIGH transition of that port’s clock signal. This reads/writes one word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory array and loops back to the start. Counter Reset (CNTRST
) is used to reset the
burst counter. All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Notes
4. When writing simultaneously to the same location, the final value cannot be guaranteed.
5. This pin is NC for CY7C09079V.
6. This pin is NC for CY7C09079V and CY7C09089V.
7. For CY7C09079V and CY7C09089V, pin #23 connected to V compatible with an IDT 5V x16 flow-through device.
Document #: 38-06043 Rev. *C Page 2 of 21
CC
is pin compatible with an IDT 5V x8 pipelined device; connecting pin #23 and #53 to GND is pin
[+] Feedback
CY7C09079V/89V/99V CY7C09179V/89V/99V

Pin Configurations (continued

1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
NC
NC
A7R
A8R
A9R
A10R
A15R
A12R
A14R
GND
NC
NC
CE0R
A13R
A11R
NC
NC
CE1R
CNTRSTR
R/WR
OER
FT/PIPER
GND
NC
A16R
58
57
56
55
54
53
52
51
NC
NC
A7L
A8L
A9L
A10L
A15L
A12L
A14L
VCC
NC
NC
CE0L
A13L
A11L
NC
NC
CE1L
CNTRSTL
R/WL
OEL
FT/PIPEL
NC
NC
A16L
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
NCNCA6L
A5L
A4L
A3L
CLKL
A1L
CNTENL
GND
GND
CNTENR
A0R
A0L
A2L
ADSR
CLKR
A1R
A2R
A3R
A4R
A5R
A6R
NC
ADSL
34 35 36 424139 403837 43 44 45 5048 494746
NC
NC
I/O8R
I/O7R
I/O6R
I/O5R
I/01R
I/O3R
I/O2R
GND
VCC
GND
I/O2L
VCC
I/O4R
I/O0L
I/O1L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
I/O8L
GND
I/O0R
3332313029282726
[8]
[8]
[9][9]
Figure 2. 100-Pin TQFP (Top View0 - CY7C09199V (128K x 9), CY7C09189V (64K x 9),CY7C09179V (32K x 9)
Document #: 38-06043 Rev. *C Page 3 of 21
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CY7C09079V/89V/99V CY7C09179V/89V/99V
Notes
8. This pin is NC for CY7C09179V.
9. This pin is NC for CY7C09179V and CY7C09189V

Selection Guide

Description
(MHz)
f
MAX2
(Pipelined)
Max. Access Time
CY7C09079V/89V/99V
CY7C09179V/89V/99V-6
100 83 67 50
6.5 7.5 9 12
CY7C09079V/89V/99V
[1]
CY7C09179V/89V/99V-7
(ns) (Clock to Data, Pipelined)
Typical Operating Current I
CC
(mA)
Typical Standby Current for I (mA) (Both Ports
SB1
175 155 135 115
25 25 20 20
TTL Level)
Typical Standby Current for I (μA) (Both Ports
SB3
10 μA 10 μA10 μA 10 μA
CMOS Level)

Pin Definitions

Left Port Right Port Description
A0L–A
16L
ADS
L
CE0L,CE
CLK
CNTEN
CNTRST
I/O0L–I/O
OE
R/W
FT/PIPE
1L
L
L
L
8L
L
L
L
GND Ground Input.
NC No Connect.
V
CC
A0R–A
16R
ADS
R
CE0R,CE
CLK
R
CNTEN
CNTRST
I/O0R–I/O
OE
R
R/W
R
FT/PIPE
Address Inputs (A0–A14 for 32K; A0–A15 for 64K; and A0–A16 for 128K devices).
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to access the part using an externally supplied address. Asserting this signal LOW also loads the burst counter with the address present on the address pins.
Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted
1R
to their active states (CE
≤ VIL and CE1 ≥ VIH).
0
Clock Signal. This input can be free running or strobed. Maximum clock input rate is f
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
R
respective port on each rising edge of CLK. CNTEN asserted LOW.
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its
R
respective port to zero. CNTRST
Data Bus Input/Output (I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices).
8R
is not disabled by asserting ADS or CNTEN.
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read operations.
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For read operations, assert this pin HIGH.
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
R
For pipelined mode operation, assert this pin HIGH.
Power Input.
CY7C09079V/89V/99V CY7C09179V/89V/99V
[1]
-9
is disabled if ADS or CNTRST are
CY7C09079V/89V/99V CY7C09179V/89V/99V
-12
.
MAX
Document #: 38-06043 Rev. *C Page 4 of 21
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CY7C09079V/89V/99V CY7C09179V/89V/99V

Maximum Ratings

Notes
10. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
11. Industrial parts are available in CY7C09099V and CY7C09199V only.
12. CE
L
and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH).
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.
Storage Temperature................................. –65°C to +150°C
Ambient Temperature with Power Applied.. –55
Supply Voltage to Ground Potential................–0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State ...........................–0.5V to V
DC Input Voltage ..................................... –0.5V to V
Output Current into Outputs (LOW)............................. 20 mA
[10]
°C to +125°C
+0.5V
CC
+0.5V
CC

Electrical Characteristics Over the Operating Range

Parameter Description
Static Discharge Voltage............................................ >2001V
Latch-Up Current..................................................... >200 mA

Operating Range

Ambient
Temperature V
–40°C to +85°C 3.3V ± 300 mV
-9 -12
-6
Range
Commercial 0°C to +70°C 3.3V ± 300 mV
Industrial
[11]
CY7C09079V/89V/99V CY7C09179V/89V/99V
[1]
-7
[1]
CC
V
V
V V I
OZ
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
OH
OL
IH
IL
Output HIGH Voltage (V –4.0 mA)
Output LOW Voltage (V +4.0 mA)
= Min. IOH =
CC
= Min. IOH =
CC
Typ
Min
Max
2.4 2.4 2.4 2.4 V
0.4 0.4 0.4 0.4 V
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Input HIGH Voltage 2.0 2.0 2.0 2.0 V Input LOW Voltage 0.8 0.8 0.8 0.8 V Output Leakage Current –10 10 –10 10 –10 10 –10 10 μA Operating Current
(V
= Max. I
CC
Outputs Disabled Standby Current (Both
Ports TTL Level)
≥ VIH, f = f
& CE
R
Standby Current (One Port TTL Level)
≥ VIH, f = f
CE
R
OUT
= 0 mA)
[12]
MAX
[12]
CEL |
MAX
Standby Current (Both Ports CMOS Level) CEL & CER ≥ VCC – 0.2V,
Commercial. 175 320 155 275 135 225 115 205 mA
Industrial
[11]
275 390 185 295 mA
Commercial. 25 95 25 85 20 65 20 50 mA
CEL
Industrial
[11]
85 120 35 75 mA
Commercial. 115 175 105 165 95 150 85 140 mA
Industrial
Commercial. 10 250 10 250 10 250 10 250 μA
[12]
Industrial
[11]
[11]
165 210 105 160 mA
10 250 10 250 μA
f = 0 Standby Current (One
Port CMOS Level)
[12]
CEL | CER ≥ VIH, f = f
Commercial 105 135 95 125 85 115 75 100 mA
MAX
Industrial
[11]
125 170 95 125 mA
Unit

Capacitance

Parameter Description Test Conditions Max Unit
C
IN
C
OUT
Document #: 38-06043 Rev. *C Page 5 of 21
Input Capacitance TA = 25°C, f = 1 MHz,
V
= 3.3V
Output Capacitance 10 pF
CC
10 pF
[+] Feedback
CY7C09079V/89V/99V CY7C09179V/89V/99V
Figure 3. AC Test Loads
(a) Normal Load (Load 1)
R1 = 590Ω
3.3V
OUTPUT
R2 = 435Ω
C= 30
pF
V
TH
=1.4V
OUTPUT
C= 30 pF
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay(Load 2)
R1 = 590Ω
R2 = 435Ω
3.3V
OUTPUT
C= 5pF
R
TH
= 250Ω
(Used for t
CKLZ
, t
OLZ
, & t
OHZ
including scope and jig)
VTH=1.4V
OUTPUT
C
(a) Load 1 (-6 and -7 only)
R = 50
Ω
Z0 = 50
Ω
3.0V
GND
90%
90%
10%
3ns
3
ns
10%
ALL INPUTPULSES
≤
≤
0.00
0.1 0
0.20
0.30
0.40
0.50
0.60
1 0 15 20 25 30 35
Capacitance (pF)
Δ
(ns) for all -7 access times
Note
13. Test Conditions: C = 10 pF.
Figure 4. AC Test Loads (Applicable to -6 and -7 only)
Figure 5. Load Derating Curve
[13]
Document #: 38-06043 Rev. *C Page 6 of 21
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CY7C09079V/89V/99V CY7C09179V/89V/99V

Switching Characteristics Over the Operating Range

Parameter Description
Min Max Min Max Min Max Min Max
f
MAX1
f
MAX2
t
CYC1
t
CYC2
t
CH1
t
CL1
t
CH2
t
CL2
t
R
t
F
t
SA
t
HA
t
SC
t
HC
t
SW
t
HW
t
SD
t
HD
t
SAD
t
HAD
t
SCN
t
HCN
t
SRST
t
HRST
t
OE
[14, 15]
t
OLZ
[14, 15]
t
OHZ
t
CD1
t
CD2
t
DC
[14, 15]
t
CKHZ
[14, 15]
t
CKLZ
Port to Port Delays
t
CWDD
t
CCS
Notes
14. Test conditions used are Load 2.
15. This parameter is guaranteed by design, but it is not production tested.
f
Flow-Through 53 45 40 33 MHz
Max
f
Pipelined 100 83 67 50 MHz
Max
Clock Cycle Time - Flow-Through 19 22 25 30 ns
Clock Cycle Time - Pipelined 10 12 15 20 ns
Clock HIGH Time - Flow-Through 6.5 7.5 12 12 ns
Clock LOW Time - Flow-Through 6.5 7.5 12 12 ns
Clock HIGH Time - Pipelined 4 5 6 8 ns
Clock LOW Time - Pipelined 4 5 6 8 ns
Clock Rise Time 3 3 3 3 ns
Clock Fall Time 3 3 3 3 ns
Address Set-Up Time 3.5 4 4 4 ns
Address Hold Time 0 0 1 1 ns
Chip Enable Set-Up Time 3.5 4 4 4 ns
Chip Enable Hold Time 0 0 1 1 ns
R/W Set-Up Time 3.5 4 4 4 ns
R/W Hold Time 0 0 1 1 ns
Input Data Set-Up Time 3.5 4 4 4 ns
Input Data Hold Time 0 0 1 1 ns
ADS Set-Up Time 3.5 4 4 4 ns
ADS Hold Time 0 0 1 1 ns
CNTEN Set-Up Time 3.5 4.5 5 5 ns
CNTEN Hold Time 0 0 1 1 ns
CNTRST Set-Up Time 3.5 4 4 4 ns
CNTRST Hold Time 0 0 1 1 ns
Output Enable to Data Valid 8 9 10 12 ns
OE to Low Z 2 2 2 2 ns
OE to High Z 1 7 1 7 1 7 1 7 ns
Clock to Data Valid - Flow-Through 15 18 20 25 ns
Clock to Data Valid - Pipelined 6.5 7.5 9 12 ns
Data Output Hold After Clock HIGH 2 2 2 2 ns
Clock HIGH to Output High Z 2 9 2 9 2 9 2 9 ns
Clock HIGH to Output Low Z 2 2 2 2 ns
Write Port Clock HIGH to Read Data Delay 30 35 40 40 ns
Clock to Clock Set-Up Time 9 10 15 15 ns
-6
CY7C09079V/89V/99V CY7C09179V/89V/99V
[1]
-7
[1]
-9 -12
Unit
Document #: 38-06043 Rev. *C Page 7 of 21
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