CYPRESS CY7C09079V, CY7C09089V, CY7C09099V, CY7C09179V, CY7C09189V User Manual

1

查询CY7C91079V供应商

CY7C09079V/89V/99V

PRELIMINARY

Features

• T rue Dual-P orted memory cell s which allow simulta­neous access of the same memory location

• 6 Flow-Through/Pipelined devices

—32K x 8/9 organizations (CY7C09079V/179V)
—64K x 8/9 organizations (CY7C09089V/189V)
—128K x 8/9 organizations (CY7C09099V/199V)

• 3 Modes

—Flow-Through
—Pipelined
—Burst

• Pipelined output mode on both ports allows fast
100-MHz operation

• 0.35-micron CMOS for optimum speed/power

v

Logic Block Diagram

R/W

L

OE

L

CY7C09179V/89V/99V

3.3V 32K/64K/128K x 8/9

Synchronous Dual-Port Static RAM

• High-speed clock to data access 6.5

[1, 2]

(max.)

• 3.3V low operating power
—Active= 115 mA (typical)
— Standby= 10 µA (typ ical)

• Fully synchronous interfa ce for easier operatio n

• Burst coun ters increment addresses internally
—Shorten cycle times

—Minimize bus noise
—Supported in Flow-Through and Pip eli ned m odes

• Dual Chip Enables f or easy depth expansion

• Automatic power-down

• Commercial and Industrial temper ature ranges

Available in 100-pin TQFP

•

/7.5

[2]

/9/12 ns

R/W

OE

R

R

CE

0L

CE

1L

FT/Pipe
I/O0L–I/O

A
CLK
ADS
CNTEN
CNTRST

Notes:

1. Call for availability.

2. See page 6 for Load Conditions.

3. I/O

4. A

L

[3]

7/8L

[4]

0–A14/15/16L

L

L

L

–I/O7 for x8 devices; I/O0–I/O8 for x9 devices.

0

for 32K; A0–A15 for 64K; and A0–A16 for 128K devices.

0–A14

15/16/17

L

Counter/

Address

Register

Decode

1
0

0/1

1

0/1

1
0

0/1

1

0/1

8/9 8/9

0

I/O

Control

I/O

Control

0

Counter/

Address
Register

True Dual-Ported

RAM Array

Decode

15/16/17

CE
CE

FT/Pipe

I/O0R–I/O

[4]

A

0–A14/15/16R

CLK

ADS

CNTEN

CNTRST

0R
1R

R

[3]

7/8R

R
R
R
R

For the most recent information, visit the Cypress web sit e at www.cypress.com

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
September 23, 1999

CY7C09079V/89V/99V

PRELIMINARY

Functional Description

The CY7C09079V/89V/99V and CY7C09179V/89V/99V are
high-speed synchronous CMOS 32K, 64K, and 128K x 8/9
dual-port static RAMs. Two ports are provided, permitting in­dependent, simultaneous access for reads and writes to any
location in memory.
lines allow for m ini m al set-up and hold times. In pipelin ed out­put mode, data is registered for decreased cycle time. Clock
to data valid t
can also be used to bypass the pipelined output register to
eliminate access latency. In flow-through mode data will be
available t

CD1

device. Pipelined output or flow-through mode is selected via
the FT

/Pipe pin.

Each port contains a b urst co unter on t he input address regis­ter. The internal write pulse width is independent of the
LOW-to-HIGH transi tion of the clock signal. The internal write
pulse is self-t imed to allow the shortest possib le cycle times.

Pin Configurations

[5]

Registers on control, address , and data

CD2

= 6.5 ns

[1, 2]

(pipelined). Flow-thro ugh m ode

= 18 ns after the address is clocked into the

100-Pin TQFP

NCNCA6L

A5L

A4L

A3L

A1L

CNTENL

A0L

A2L

(Top View)

CY7C09179V/89V/99V

A HIGH on CE
down the in ternal ci rcuitry to r educe the static power consump­tion. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
pipelined mode, one cycle is requir ed with CE
HIGH to reactiv ate the outputs.

Counter enable inputs are pro vided to sta ll the oper ation of the
address input an d utilize the internal address gener ated b y the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS

). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port’s clock signal. This will read/write one
word from/in to each su cces siv e address locat io n until CNTEN
is deasserted. The counter can address the entire memory
array and will loop bac k to the start. Counter Reset (CNT RST
is used to reset the burst counter.

All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.

CLKL

GND

ADSR

CLKR

ADSL

CNTENR

or LOW on CE1 for one clock cy cle will power

0

0

A0R

A1R

A2R

A3R

A4R

A5R

A6RNCNC

LOW and CE

1

)

CNTRSTL

[8]

FT

A10L
A11L
A12L
A13L
A14L

[6]

A15L

[7]

A16L

CE
CE1L

R/WL

/PIPEL

NC

NC
A7L
A8L
A9L

VCC

NC

NC

NC

NC

OE

NC

NC

92 91 90 848587 868889 83 82 81 7678 77798093949596979899100

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

0L

L

17
18
19
20
21
22
23

24
25

CY7C09099V (128K x 8)

CY7C09089V (64K x 8)
CY7C09079V (32K x 8)

34 35 36 424139 403837 43 44 45 5048 494746

3332313029282726

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

NC
NC
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R

[6]

A15R

[7]

A16R
GND
NC
NC
NC
NC

0R

CE
CE1R
CNTRST
R/WR
OER
FT/PIPER
GND
NC

R

[8]

NC

GND

I/O7L

I/O4L

I/O5L

I/O6L

GND

I/O2L

I/O3L

VCC

GND

I/O0L

I/O1L

I/O0R

Notes:

5. When writing simultaneously to the same location, the final value cannot be guaranteed.

6. This pin is NC for CY7C09079V.

7. This pin is NC for CY7C09079V and CY7C09089V.

8. For CY7C09079V and CY7C09089V , pin #23 connected to V
compatible with an IDT 5V x16 flow-through device.

is pin compatible with an IDT 5V x8 pipelined device; connecting pin #23 and #53 to GND is pin

CC

2

I/01R

NC

NC

VCC

I/O2R

I/O5R

I/O3R

I/O4R

NC

I/O7R

I/O6R

CY7C09079V/89V/99V

Pin Configurations

NC

NC
A7L
A8L
A9L

A10L
A11L
A12L
A13L
A14L

[9]

A15L

A16L

VCC

NC

NC

NC

NC

CE0L
CE1L

CNTRSTL

R/WL

OEL

FT/PIPEL

NC

NC

(continued)

NCNCA6L

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

PRELIMINARY

100-Pin TQFP

(Top View)

A5L

A4L

A3L

A1L

A2L

CLKL

CNTENL

A0L

92 91 90 848587 868889 83 82 81 7678 77798093949596979899100

GND

GND

ADSL

CY7C09199V (128K x 9)

CY7C09189V (64K x 9)
CY7C09179V (32K x 9)

34 35 36 424139 403837 43 44 45 5048 494746

3332313029282726

CY7C09179V/89V/99V

CNTENR

ADSR

A0R

CLKR

A1R

A2R

A3R

A4R

A5R

A6R

NC

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

NC
NC
A7R
A8R
A9R
A10R
A11R
A12R
A13R
A14R

[9]

A15R

[10][10]

A16R
GND
NC
NC
NC
NC
CE0R
CE1R
CNTRSTR
R/WR
OER
FT/PIPER
GND
NC

NC

VCC

GND

I/O7L

I/O8L

I/O4L

I/O5L

I/O6L

GND

I/O2L

I/O3L

I/O1L

GND

I/O0L

I/O0R

I/01R

VCC

I/O3R

I/O2R

I/O6R

I/O5R

I/O4R

NC

I/O8R

I/O7R

Selectio n Guide

CY7C09079V/89V/99V
CY7C09179V/89V/99V

f

(MHz) (Pipel ined) 100 83 67 50

MAX2

Max. Access Time (ns)

[1, 2]

-6

6.5 7.5 9 12
(Clock to Data,
Pipelined)

Typical Operating
Current I

CC

(mA)

T ypical Standby Curren t
for I
Port s TTL Level)

(mA) (Both

SB1

T ypical Standby Curren t
for I

(µA) (Both P orts

SB3

175 155 135 115

25 25 20 20

10 µA10 µA 10 µA10 µA

CMOS Level)

Notes:

9. This pin is NC for CY7C09179V.

10. This pin is NC for CY7C09179V and CY7C09189V.

CY7C09079V/89V/99V
CY7C09179V/89V/99V

[2]

-7

3

CY7C09079V/89V/99V
CY7C09179V/89V/99V

-9

CY7C09079V/89V/99V
CY7C09179V/89V/99V

-12

CY7C09079V/89V/99V

PRELIMINARY

Pin Definitions

Left Port Right Port Description

A0L–A

16L

ADS

L

CE0L,CE

CLK

L

CNTEN

CNTRST

I/O0L–I/O
OE

L

R/W

L

FT/PIPE

GND Ground Input.
NC No Connect.
V

CC

L

1L

L

8L

L

A0R–A

16R

ADS

R

CE0R,CE

CLK

R

CNTEN

CNTRST

I/O0R–I/O
OE

R

R/W

R

FT/PIPE

Address Inputs (A0–A14 for 32K; A0–A15 for 64K; and A0–A16 for 128K devices).
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to

access the part using an e xternally supplied address. Asserting this signal LOW al so loads the
burst counter wit h the address present on the addr ess pins.

Chip Enable Input. To select either the l eft or right port, both CE0 AND CE1 must be asserted to

1R

their active states (CE

≤ VIL and CE1 ≥ VIH).

0

Clock Signal. This input can be free running or strobed. Ma ximum clock input rate is f
Counter Enable In put. Asserting this signal LO W increments the bur st address counter of its

R

respectiv e port on eac h rising ed ge of CLK. CNTEN
LOW.

Counter Reset I nput. Ass erting this si gnal LO W reset s the bu rst addre ss counter of its respecti ve

R

por t to zer o. CNTRS T
Data Bus Input/Output (I/O0–I/O7 for x8 de vices; I/O0–I/O8 for x9 de vices).

8R

is not disabled by asserting ADS or CNTEN.

Output Enable Input. This signal must be asserted LO W to enab le the I/O data pin s during read
operations.

Read/Write Enable I nput. This signal i s asserted LOW t o write to the dua l port memory array. For
read operation s, assert this pin HIGH.

Flow-Through/ Pipelined Sele ct Input. For flow -through mod e operatio n, assert this pin LOW. For

R

pipelined mode operation, assert this pin HIGH.

Power Input.

CY7C09179V/89V/99V

.

MAX

is disab led i f ADS or CNTRST are asse rted

Maximum Ratings

(Abov e which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature................ .. ............ ... –65

Ambient Temperature with Power Applied..–55

Supply Voltage to Ground Potential...............–0.5V to +4.6V

DC Voltage Applied to

Outputs in High Z State ...........................–0.5V to V

DC Input Voltage......................................–0.5V to V

°

C to +150°C

°

C to +125°C

+0.5V

CC

+0.5V

CC

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage .......... ............ .....................>2001V

Latch -U p Cu rre n t....... ......... ... ......... ... .......... .. .......... . >200mA

Operating Range

Ambient

Range

Commercial 0°C to +70°C 3.3V ± 300 mV
Industrial –40

Temperature

°

C to +85°C 3.3V ± 300 mV

V

CC

4

CY7C09079V/89V/99V

Electrical Characteristics

Parameter Description

V

V

V
V
I

OZ

I

CC

I

SB1

I

SB2

I

SB3

I

SB4

OH

OL

IH
IL

Output HIGH Voltage (VCC=Min.,
I

= –4.0 mA)

OH

Output LOW Voltage (VCC=Min.,
I

= +4.0 mA)

OH

Input HIGH Voltage 2.0 2.0 2.0 2.0 V
Input LOW Voltage 0.8 0.8 0.8 0.8 V
Output Leakage Current –10 10 –10 10 –10 10 –10 10 µA
Operating Current

(V

=Max., I

CC

Outputs Disabled
Standby Current (Both

Ports TTL Level)
& CE

≥ VIH, f=f

R

Standby Current (One
Port TTL Level)
CE

≥ VIH, f=f

R

OUT

[11]

MAX

=0 mA)

[11]

MAX

Standby Current (Both
Ports CMOS Level)
CEL & CER ≥ VCC – 0.2V,
f=0

Standby Current (One
Port CMOS Level)

[11]

CEL | CER ≥ VIH, f=f

PRELIMINARY

CY7C09179V/89V/99V

Over the Operating Range

CY7C09079V/89V/99V
CY7C09179V/89V/99V

[1, 2]

-6

Min.

Typ.

Max.

[2]

-7

Min.

Typ.

Max.

-9 -12

Min.

Typ.

Max.

Min.

2.42.42.42.4 V

0.4 0.4 0.4 0.4 V

Com’l. 175 320 155 275 135 225 115 205 mA

Indust. 185 295 mA

Com’l. 25 95 25 85 20 65 20 50 mA

CEL

Indust. 35 75 mA

Com’l. 115 175 105 165 95 150 85 140 mA

CEL |

Indust. 105 160 mA

Com’l. 10 250 10 250 10 250 10 250 µA

[11]

Indust. 10 250 µA

Com’l. 105 135 95 125 85 115 75 100 mA

Indust. 95 125 mA

MAX

Typ.

Max.

Units

Capacitance

Parameter Description Te st Condi tions Max. Unit

C

IN

C

OUT

Note:

11. CE

and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH).

L

Input Capacitance TA = 25°C, f = 1 MHz,

V

= 3.3V

Output Capacitance 10 pF

CC

10 pF

5

CY7C09079V/89V/99V

PRELIMINARY

AC Test Loads

3.3V

R1= 590

OUTPUT

pF

C= 30

R2= 435

(a) Normal Load(Load 1)

AC Test Loads (Applicable to -6 and -7 only)

Z0 = 50

Ω

OUTPUT

C

R = 50

Ω

Ω

Ω

VTH=1.4V

OUTPUT

C=

30 pF

(b) Thévenin Equivalent (Load 1)

[12]

R

TH

=250

Ω

3.0V

GND

V

TH

≤

=1.4V

10%

3ns

CY7C09179V/89V/99V

3.3V

R1= 590

OUTPUT

C= 5pF

(c)Three-State Delay(Load 2)

(Used for t

CKLZ

including scope and jig)

ALL INPUTPULSES

90%

90%

, t

OLZ

10%

R2= 435

, & t

3

ns

≤

Ω

Ω

OHZ

(a) Load 1 (-6 and -7 only)

(ns) for al l -7 access times

∆

0.60

0.50

0.40

0.30

0.20

0.1 0

0.00
1 0 1 5 20 25 30 35

Capacitance (pF)

(b) Load Derating Curve

Note:

12. Test Conditions: C = 10 pF.

6